JPH07162313A - Digital modulation device - Google Patents

Abstract

PURPOSE:To attain the run control of an I-NRZI conversion circuit. CONSTITUTION:Input data are applied to a delay element 13 through a selector 12. An output from the element 13 is applied to an I-NRZI conversion circuit 14 to execute its I-NRZI conversion. A modulation signal output from the circuit 14 and its one-clock delay signal are applied to an exclusive OR circuit 20. An exclusive OR operation result from the circuit 20 indicates an input to the circuit 14 which is necessary for continuing the run of the modulation signal or stopping run continuation. When the selector 12 selects the output of the circuit 20 in each prescribed clock instead of the input data, the run of the modulation signal can be controlled with a prescribed clock period.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulator suitable for a digital magnetic recording / reproducing apparatus and the like.

[0002]

2. Description of the Related Art In recent years, with the progress of digital technology, image information has been digitally processed, and, for example, a digital video tape recorder (hereinafter also referred to as VTR) has been developed. In the transmission and recording of digital signals, it is difficult to transmit or record the signal components in the low frequency region with high efficiency. Therefore, modulation to a balanced code for suppressing the signal components in the direct current and low frequency regions, That is, DC-free modulation is often used.

In magnetic recording, the output characteristics deteriorate as the recording frequency increases. Therefore, in digital recording, it is necessary to increase the minimum magnetization reversal interval, that is, to convert into a modulation signal having a large minimum pulse width. Further, similarly, it is impossible to obtain a sufficient output for the components in the DC and low frequency regions. Therefore, it is necessary to reduce the maximum pulse width of the modulation signal, that is, to obtain the DC-free characteristic in which not only the DC component but also the entire low-frequency component is suppressed.

As a means for achieving these conditions, there is the 8-14 modulation method disclosed in Document 1 (Japanese Patent Laid-Open No. 61-196469).

In 8-14 modulation, 8-bit input data is converted into a 14-bit code. In this case, of the 14384 16-bit codes, "1"
The minimum value d of the number of "0" s sandwiched between two is 1, "1"
The maximum number k of "0" s sandwiched between two is 0, the consecutive number s0 of "0" s from the beginning of the code is 1≤s0≤4, and the consecutive number e0 of "0s" at the end of the code is 8-bit input data is expressed using only codes that are 4 or less. The data converted into 14 bits is NRZI modulated and then output. The NRZI modulation is to invert the recording level at the front end of the symbol "1".

Since the 14-bit code is limited as described above, the run (the same symbol is continuous) of the data after NRZI modulation is limited. That is, the minimum pulse width is 2 from d = 1 and the maximum pulse width is 9 from k = 8.
Becomes Since 8-bit data is converted into 14-bit data and transmitted, the 1-bit interval after modulation is 8T (T is a data period) / 14, and the minimum pulse width is 2. Therefore, the minimum magnetization reversal interval is about 1 It can be increased to .14T (= 16T / 14). It should be noted that d = 1 at the joint between codes, that is, "1" at the beginning and end of the code.
Is not continuous and k = 8 is satisfied, 1 ≦
s0 <4, 0≤e0 <4 is set.

Further, Document 2 (Japanese Patent Laid-Open No. 3-234146) discloses a new 8-14 modulation system adopted in the format D-3 system of a digital VTR.

In this new 8-14 modulation system, 14
The code converted into bits is modulated based on the NRZ rule. The NRZ rule is to output input data as it is. In the example of Document 2, high-density recording, azimuth recording, and overwriting recording are possible by setting the number of consecutive NRZ-modulated code runs to 2 or more and 7 or less.

As described above, in these examples, the characteristics suitable for magnetic recording are obtained by limiting the number of continuous runs. Generally, in digital transmission, a clock signal is generated from a received signal or a reproduced signal. In this case, when a modulation signal with a high occurrence frequency of long runs is input to the clock generation circuit, the change of the modulation signal is small and the operation tends to be unstable. Thus, run control is a very important issue in digital modulation.

The run limitation in the NRZ conversion and NRZI conversion will be described below using mathematical expressions.

As described above, the NRZ conversion outputs the input symbol as it is. If the n-th bit of the input data is an, the output of the NRZ conversion circuit is also an.
Becomes The continuous run means that consecutive output signals do not undergo bit inversion, that is, adjacent bits have the same symbol. Therefore, in the NRZ conversion, the run continuity is expressed by the following equation (1).

An = an-1 (1) That is, the symbol "0" is set after the symbol "0" as the input data of the NRZ conversion circuit, and the symbol "1" is set.
After the, the run can be continued by setting the symbol "1".

On the other hand, the fact that the runs are not continuous means that the symbols of adjacent bits are different.
Therefore, the run discontinuity in the NRZ conversion is expressed by the following equation (2).

A n ≠ a n-1 (2) That is, the symbol “1” is set after the symbol “0” as the input data of the NRZ conversion circuit, and the symbol “1” is set.
After that, the symbol “0” may be set.

FIG. 3 is a circuit diagram showing an NRZI conversion circuit.

The input bit an is given to the exclusive OR circuit 1. The output of the exclusive OR circuit 1 is output as an output bit bn, and is delayed by one data by the delay device 2 before being given to the exclusive OR circuit 1. That is, when "1" is input, the NRZI conversion circuit inverts and outputs the modulated signal. If the exclusive OR operation is represented by the symbol @, N
The RZI conversion can be represented by the following formula (3).

Bn = an @ bn-1 (3) The fact that runs are consecutive means that adjacent bits have the same symbol, and can be expressed by the following equation (4).

Bn = bn−1 (4) By substituting the equation (3) into the equation (4), the following equation (5) is obtained.

An @ bn-1 = bn-1 an = 0 (5) This expression (5) means that the run can be continued by inputting the bit of the symbol "0" to the NRZI conversion circuit. is doing.

On the other hand, the stop of continuous runs means that adjacent bits are different symbols, and is expressed by the following equation (6).

Bn ≠ bn−1 (6) When Equation (3) is substituted into this Equation (6) and arranged, the following Equation (7) is obtained.

An @ bn-1 ≠ bn-1 an ≠ 0 an = 1 (7) From this equation (7), when the continuous run is stopped,
It can be seen that it is sufficient to input the bit of the symbol "1" to the NRZI conversion circuit.

As described above, in the NRZ conversion and the NRZI conversion, the modulated signal outputs are different for the same input,
Run control methods are different from each other.

By the way, recently, I-NRZI (interleaved NR) using exclusive logic around two clock periods is used.
ZI) transformation may be adopted. Figure 4 shows this IN
It is a block diagram which shows an RZI conversion circuit.

Input data is given to the exclusive OR circuit 5. The output of the exclusive OR circuit 5 is given to the exclusive OR circuit 5 via the delay devices 6 and 7. The modulated output bn corresponding to the input bit an is delayed by 2 bits, and the exclusive OR circuit 27 outputs the input bit an and the output bit bn-2 two bits before.
The exclusive OR of is obtained and output as the output bn.

Also in this I-NRZI modulation, it is necessary to limit the continuity of runs. However, I-NRZI
Run control in modulation has not been established, and because the modulation signal output differs for each method for the same input,
In this I-NRZI modulation, NRZ modulation or NRZ
Since the control of the run in the I modulation cannot be applied, there is a problem that the run is generated indefinitely.

[0027]

As described above, in the above-described conventional digital modulator, the run control in the I-NRZI conversion is not established, and there is a problem that runs are generated indefinitely. It was

It is an object of the present invention to provide a digital modulator capable of controlling a run in I-NRZI conversion.

[Constitution of Invention]

In a digital modulator according to the present invention, an I-NRZI converting means for converting an input signal into an I-NRZI signal and outputting it as a modulated signal, and delaying the modulated signal by one clock period. A first delay means,
The exclusive OR of the modulated signal and the output of the first delay means is obtained, and the exclusive OR operation result is directly output or inverted based on whether or not the runs of the modulated signal are continuous. Exclusive-OR calculating means for outputting, selecting means for switching between input data and output of the exclusive-OR calculating means, and output, the output of this selecting means is delayed by one clock period, and the I-NRZI converting means is provided. And a second delay means provided to the.

[0030]

In the present invention, when the selecting means selects the input data, the input data is supplied to the I-NRZI converting means through the second delay means, and the I-NRZI converting means converts the input data into the I-NRZI converting data. To do. The first delay means is I
The modulated signal from the -NRZI conversion means is delayed by one clock period, and the exclusive logic operation means obtains the exclusive OR of the modulated signal and the one clock delay signal. The result of the exclusive OR operation is I-N for making the runs of the modulation signal continuous.
The input of the RZI conversion means is shown, and the inverted output of the exclusive OR operation result is I for stopping the continuous run of the modulation signal.
The input of the -NRZI conversion means is shown. The selection means selects the output of the exclusive OR operation means at a predetermined timing to control the run of the modulation signal.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital modulator according to the present invention. In this embodiment, the continuation of runs is forcibly stopped at a predetermined bit interval.

Input data is input to the input terminal 11. This input data is composed of 8-bit valid data and 1-bit invalid data. Input data is selector
It is supplied to the I-NRZI conversion circuit 14 via 12 and the delay element 13. Selector 12 is AND gate 15, 16, OR gate
The input data is given to one input end of the AND gate 15.

An input terminal is provided at the other input end of the AND gate 15.
Timing pulse is given via 19. Timing pulse is low level (hereinafter,
It becomes "L" and becomes high level (hereinafter,
This signal is "H". The timing pulse from the input terminal 19 passes through the inverter 18 and the AND gate 16
It is also given to one input terminal. The inverter 18 inverts the timing pulse and outputs it. The other input terminal of the AND gate 16 is also given the output of the exclusive OR circuit 20 described later. The AND gate 15 passes the input data when the timing pulse is "H", and the AND gate 16 passes the output of the exclusive OR circuit 20 when the timing pulse is "L". The NOR gate 17 gives the outputs of the AND gates 15 and 16 to the delay element 13. The delay element 13 is a selector 12 at clock timing.
To the I-NRZI conversion circuit 14.

The I-NRZI conversion circuit 14 has the same structure as that of FIG. 4, and is composed of the exclusive OR circuit 5 and the delay devices 6 and 7. The output of the delay element 13 is given to one input terminal of the exclusive OR circuit 5, and the output of the exclusive OR circuit 5 is delayed by the delay units 6 and 7 for 2 bits and then the other input of the exclusive OR circuit 5 is provided. Give to the edge. The I-NRZI conversion circuit 14 outputs the output of the exclusive OR circuit 5 to the output terminal 21 as a modulation signal output.

In this embodiment, the output of the exclusive OR circuit 5 and the output of the delay device 6 are also output to the exclusive OR circuit 20. The exclusive OR circuit 20 performs an exclusive OR operation on two inputs, inverts the operation result, and outputs it to the selector 12.

By the way, if the output bit for the n-th bit an input to the I-NRZI conversion circuit 5 is bn, then bn can be expressed by the following equation (8).

Bn = an @ bn-2 (8) The fact that the runs are not continuous means that the following expression (9) is established.

Bn ≠ bn + 1 (9) Substituting equation (8) into equation (9) and rearranging yields equation (10) below.

An @ bn-2 ≠ an + 1 @ bn-1 an + 1 ≠ an @ bn-2 @ bn-1 (10) This expression (10) is an exclusive logic of bits an and bn-2. I-NRZI conversion of the inverted output of the exclusive OR operation of the sum operation result and the bit bn-1, that is, the inverted output of the exclusive OR operation of the output of the exclusive OR circuit 5 and the output of the delay device 6. It is shown that the continuous run can be stopped by applying the input to the circuit 14. In the present embodiment, the operation of the above formula (10) is performed using the exclusive OR circuit 20.

Next, the operation of the embodiment thus constructed will be described with reference to the timing chart of FIG. 2A shows a clock, FIG. 2B shows a timing pulse, FIG. 2C shows input data, and FIG. 2D shows a modulation signal output. 2 (e) shows the output bn-2 of the delay device 7, FIG. 2 (f) shows the output bn-1 of the delay device 6, and FIG. 2 (g) shows the I-NRZI conversion circuit 14.
The input an of is shown.

Input data input through the input terminal 11 is supplied to the I-NRZI conversion circuit 14 through the selector 12 and the delay element 13. The input data shown in FIG.
Has one bit of valid data and one bit of invalid data,
The valid data is input at the timing corresponding to the “H” period of the timing pulse in FIG. 2B, and the invalid data is input at the timing corresponding to the “L” period of the timing pulse. The selector 12 inputs the input data via the delay element 13 only during the "H" period of the timing signal shown in FIG.
Output to the -NRZI conversion circuit 14. That is, during the "H" period of the timing signal, the AND gate 15 passes the valid data and outputs it through the OR gate 17. The I-NRZI conversion circuit 14 I-NRZI converts the input data and outputs it to the output terminal 21 as a modulated signal output.

On the other hand, the AND gate 15 blocks passage of input data during the "L" period of the timing signal. During this period, a timing pulse of “H” is supplied to the AND gate 16 via the inverter 18, and the signal supplied to the other input terminal of the AND gate 16 is output to the delay element 13 via the OR gate 17. .

The output of the exclusive OR circuit 20 is applied to the other input terminal of the AND gate 16. The exclusive OR circuit 20 is given the output of the exclusive OR circuit 5 and the output of the delay device 6 from the I-NRZI conversion circuit 14, and performs the exclusive OR operation shown on the right side of the above equation (10). Then, the inverted output of the calculation result is output to the AND gate 16. During the "L" period of the timing pulse, the output of the exclusive OR circuit 20 is the delay element 13
Is supplied to the I-NRZI conversion circuit 14 via. Expression (1
0) indicates a condition for stopping the continuation of runs, and by making the output of the exclusive OR circuit 20 the input of the I-NRZI conversion circuit 14, the modulated signal output is forcibly inverted and Continuity stops.

For example, as shown in FIG. 2, at the timing A within the "H" period of the timing pulse, I-N
The input data of the symbol "0" (FIG. 2C) is delayed by the delay element 13 and input to the RZI conversion circuit 14 (FIG. 2G). At this timing, the output of the delay device 7 is also the symbol "0" (Fig. 2 (e)), and the modulated signal output is the symbol "0" as shown in Fig. 2 (d). Input data (invalid data) after the next timing B
Is also a symbol "0" (FIG. 2C), and when this input data is input to the I-NRZI conversion circuit 14, 0 runs of the modulation signal output are continuous. On the other hand, in the present embodiment, at the timing B, the selector 12 selects the output of the exclusive OR circuit 20 by the "L" timing pulse. At timing B, the output of the exclusive OR circuit 20 is the symbol "1" as shown in FIG. By the exclusive OR operation of this symbol “1” and the symbol “0” from the delay unit 7 (FIG. 2 (e)),
The I-NRZI conversion circuit 14 obtains the modulated signal output of the symbol "1" (FIG. 2 (d)). In this way, the continuous run is forcibly stopped.

As shown in FIG. 2, the modulation signal output is always bit-inverted even during the "L" period of another timing pulse, and the continuous run is stopped.

As described above, in this embodiment, the exclusive OR circuit 20 performs the operation of the above formula (10), and the operation result is selected at the timing of the timing pulse.
By inputting 12 to the I-NRZI conversion circuit, the continuous run of the modulation signal output is forcibly stopped at the timing pulse cycle. In this way, it is possible to control the run with an extremely simple circuit configuration.

Although the negative output exclusive OR circuit 20 is used in the above embodiment, it is also possible to forcibly make the runs continuous by using the positive output exclusive OR circuit. The continuous run means that the following formula (11) is established.

Bn = bn + 1 (11) By substituting the above equation (8) showing the I-NRZI conversion equation into this equation (11) and arranging it, the conditional equation (12) for continuous runs is obtained. To be

An @ bn-2 = an + 1 @ bn-1 an + 1 = an @ bn-2 @ bn-1 (12) This equation (12) replaces the exclusive OR circuit 20 of FIG. It is shown that the runs of the modulation signal output can be made continuous by using an exclusive OR circuit of positive output. That is, in the present embodiment, the upper and lower limits of the run can be easily limited by using the exclusive OR circuits of the positive and negative outputs in combination.

[0050]

As described above, according to the present invention, I
This has the effect that runs can be controlled in one NRZI conversion.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital modulator according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing an NRZI conversion circuit.

FIG. 4 is a block diagram showing an I-NRZI conversion circuit.

[Explanation of symbols]

5 ... Exclusive OR circuit, 12 ... Selector, 14 ... I-NRZ
I conversion circuit, 20 ... Exclusive OR circuit

Claims (1)

[Claims] 1. An I-NRZI conversion means for I-NRZI converting an input signal and outputting it as a modulation signal, a first delay means for delaying the modulation signal by one clock period, the modulation signal and the first The exclusive OR with the output of the delay unit 1 is output, and the exclusive OR operation result is output as it is or is inverted and output based on whether or not the runs of the modulation signal are to be continued. Computing means, selecting means for switching and outputting input data and output of the exclusive OR computing means, and output of this selecting means delayed by one clock period
And a second delay means for supplying the NRZI conversion means.