JPH05205407A - Digital signal magnetic recorder - Google Patents

Abstract

PURPOSE:To reduce the number of DC control bits by obtaining the total electric charge quantity of the current waveform of each digital signal block and compar ing it with the total electric charge quantity of the next block ahead to deter mine a 2-bit pattern. CONSTITUTION:A DC control 2-bit pattern inserting circuit 4 obtains a total electric charge quantity B of each digital signal block passing a 1-7 modulator 3 and compares an absolute value A(+) of A+B and an absolute value A(-) of A-B with each other in accordance with this quantity B and a total electric charge quantity A of the next block ahead. In the case of A(+)<=A(-), pattern '00' is inserted; and in the case of A(+)>A(-), the last bit of the preceding block and the first bit of the current block are referred to insert connection pattern '01' or '10', thereby reducing the DC component of the digital signal. By this reduction method, the DC component of the digital signal is reduced by the small number of bits, namely, two bits. The DC component of the reproduced signal is reduced also by the same processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC component control device added to reduce a DC component contained in digital data when magnetically recording a digital signal or an image signal converted into a digital signal.

[0002]

2. Description of the Related Art A digital modulation system related to the present invention will be described first. The conversion table is shown in Table 1.

[0003]

[Table 1]

Digitized image data is divided into 2-bit data, 2-bit data is converted into 3-bit data according to a conversion table, and recorded on a magnetic tape. However, as shown in the table, the conversion pattern is changed according to the value of the next two bits after the two bits so that 1 is not continuous in the converted digital data. When it is "1", the recording current is reversed and recording is performed. The magnetization reversal width at this time is 4/3 times longer than that when the image data is directly recorded. However, as shown in the conversion table Table 1, the converted digital data contains a DC component. In the transmission system and the recording system, it is often impossible to transmit and record the DC component.
Reducing the DC component is an important issue.

As a conventional technique for reducing the DC component, for example, there is one disclosed in Japanese Patent Laid-Open No. 61-245720. In this system, the DC component of the digital signal is removed while keeping the condition that the maximum number of consecutive 0s (run length) in the digital modulation system is limited. For this reason, the influence of the past digital signal until the digital signal is transmitted or recorded is stored, an additional bit (two bits) is inserted for each block composed of a plurality of digital signals, and the block before the connection is connected. It has been proposed to perform an operation of changing the last 4 bits and the first 4 bits of a block with a predetermined logic. Although ideal in terms of performance, there are problems that the memory circuit becomes large in order to see the influence of past digital signals, and further modification of the modulated digital signal complicates the demodulation circuit.

[0006] As a simple method, the 3-bit insertion method is a technical report of the Television Society of Japan (Vol. 14, No. 48 pp13).
-18, published September 14, 1990).
In this conventional example, 3-bit data is inserted for every predetermined number of data in the direction of canceling the DC component.

As another method of giving the digital modulation method, there is a case as shown in Table 2, but since it is the same as Table 1 in principle, the following description is based on Table 1.

[0008]

[Table 2]

[0009]

In the prior art, three bits are assigned as DC control data.
This number of bits does not record information. In order to efficiently record information on a magnetic tape, it is an object of the present invention to limit the number of DC control bits to 2 bits and simplify the DC reduction circuit in consideration of the magnetic recording process.

[0010]

As in the conventional recording method, a none return zero inversion (NRZI: No) is used.
n Return Zero Inversion) Record, that is, data 1
At this time, the recording current is inverted and the recording method of retaining the recording current at the data 0 is adopted, and two bits are used as the DC control recording bit. In two data blocks linked by a DC control bit, the sum of the charge values of the recording current in each data block is calculated. A, respectively
When B, it is calculated which of A + B and AB is closer to 0. When + is selected, the control recording bit is “00”, and when − is selected, it is “10” or “01”. .. The selection of "10" and "01" is determined in consideration of the fact that the "11" pattern does not occur at the connection point between the data and the control bit after modulation.

[0011]

When the sum of charges of the two data blocks is a value close to zero when A + B, "00" is selected as the control recording bit. Since it is NRZI recording, no reversal of the recording current occurs, and the connection is made only by extending the run length of the code at the connection point. In the case of AB, when a value close to zero is obtained,
As the control recording bit, "10" or "01" is selected. When the recording data immediately before the control recording bit is "0", "10" is selected, and when it is "1", "01" is selected. As a result, "11" is prohibited on the recording bit, and the shortest recording current reversal interval is always secured for two bits. Further, since "1" is included in the control recording bit, the recording current is inverted, and A-B is realized.

When the influence of the DC component of the magnetic recording / reproducing system is examined in detail, first, it is possible to transmit a considerably low frequency component in the recording system by devising a circuit. However, the magnetic recording process by the magnetic head and the magnetic tape is affected by the low frequency component. At this time, several bits (5-10
A bit). On the other hand, when the winding type magnetic head is used in the reproducing system, the output is in proportion to the frequency, so that the existence of the low frequency component is a big problem. However, since the influence on the reproducing side can be corrected by the equalization circuit, it does not have to be considered so much recently. Therefore, it is necessary to consider the DC components in several bits (5 to 10 bits) before and after the recording bit that affects the magnetic recording process. Therefore, in the present invention, only that block and the previous block are considered.

[0013]

EXAMPLES The present invention will be described in more detail by way of examples. FIG. 1 is a signal system diagram of a recording section of a digital signal recording apparatus according to the present invention. Reference numeral 1 is an interface circuit with an external device, 2 is a circuit for adding an error correction code for correcting a code error generated in a recording / reproducing system of a tape head on the reproducing side, 3 is a 1-7 modulation circuit, and 4 is direct current control. It is a 2-bit pattern insertion circuit for use. The modulated signal is connected to the data block by the DC control 2-bit pattern insertion circuit and has a reduced DC component.

FIG. 2 is a detailed signal system diagram of the DC control 2-bit pattern insertion circuit. 4-1 is an input terminal for the modulated digital signal. The input signal is the delay circuit 4-
At 3, the signal delayed by one bit clock is subjected to an exclusive OR operation, and converted into NRZL format data corresponding to the recording current waveform. The up / down counter 4-4 operating with the bit clock is set to N
Control with RZL data. That is, 1 in the NRZL signal
In the case of, the counter value is increased, and in the case of 0, the counter value is decreased to obtain the total charge amount V of the recording current waveform. The counter is reset at block intervals. The total charge amount V _n is stored in the latch memory 4-5 for each block. The sign of the total charge amount of the immediately preceding block is controlled by the result of the comparison circuit 4-8. In the arithmetic circuit 4-7, the total charge amount B of the immediately preceding block and the current charge amount A = V _n to the absolute value A of B + A
The absolute value A (-) of (+) and BA is calculated and output.
The two values are compared by the comparison circuit 4-8, and when A (+) is small or equal, the connection pattern generation circuit 4-10 generates the connection pattern 00. In the latch and sign control circuit 4-6, the sign of the latch contents remains unchanged. On the contrary, when A (-) is small, the latch circuit 4-
At 9, the connection bit of the modulation signal for each block is fetched, and the connection pattern 01 or 10 is generated by referring to this connection data. Table 3 summarizes these connection methods. The latch and sign control circuit 4-6 reverses the sign of the latch contents.

[0015]

[Table 3]

An example is provided for further explanation. However, this is a case where the number of bits after modulation of one block is 18 bits and the data after modulation (NRZI display) is given as follows. In the n-1th block, 010010010000101000 is converted into 001010000010100001 in the nth block, the output of the circuit 4-2 is 011100011111001111 110011111100111110, and the latch output 4-6 and the latch output 4-5 are +6 (n-2 block). The relationship with and is ignored here, and it is assumed that there is no code control), and +8. | A + B | = 14 | AB | = 2. On the other hand, the latch circuit 4-9 fetches data (after modulation) at the block boundary, that is, the last data 0 of the (n-1) th block and the first data 0 of the nth block.
Therefore, 01 is selected as the DC control bit.

Including the DC control bit, n-1 again
When the data of the block and the n block are described, the DC component is suppressed, such as the (n-1) th block 010010010000101000 DC control bit 01 the nth block 001010000010100001.

The switch circuit 4-11 is a circuit for switching the memories 4-12 and 4-13 for each block.
The data after modulation for each block is temporarily stored in the memory,
After inserting the connection pattern given by the connection pattern generation circuit 4-10, it is supplied to the output terminal 4-15.

As described above, according to the present invention, direct current control can be performed with two bits, and the circuit can be simplified by performing direct current control in the preceding and following blocks. One block in the above example
Although it is set to 8 bits, it is natural to select 36 or 72 according to the margin of the recording device. In particular, its value is not limited.

[0020]

According to the present invention, the DC component of the modulated digital signal can be suppressed with two bits and as few additional bits as possible.

[Brief description of drawings]

FIG. 1 is a system diagram of a recording apparatus according to an embodiment of the present invention.

FIG. 2 is a detailed signal system diagram of a main circuit section in the embodiment of FIG.

[Description of Codes] 1 ... Interface circuit with external device, 2 ... Circuit for adding error correction code for correcting code error generated in recording / reproducing system of tape head on reproducing side, 3 ... 1-7 modulation circuit 4, 2-bit pattern insertion circuit for DC control.

Claims (1)

[Claims] 1. A digital signal as a two-bit pattern for connecting blocks of a plurality of digital signals when the polarity of the current is inverted by the digital signal 1 and the previous state is held by the signal 0 for recording. , 00, 01 or 1
A digital signal magnetic recording apparatus characterized in that 0 is selected and used, and in terms of selection, the absolute value of the sum and difference of the total charge amounts of the block and the preceding block are compared.