JPH07161967A - Composite semiconductor device - Google Patents

Abstract

PURPOSE:To make the voltage between the terminals of a composite semiconductor device low, by providing a second conduction type third semiconductor layer having a high impurity concentration in a first semiconductor layer while it is separated from others, and by providing a second conduction type sixth semiconductor layer having a notch part for contacting the first semiconductor layer with a fifth semiconductor layer. CONSTITUTION:A P2<+>-layer (P-base layer) 6 in an IGBT and a P<->-layer (P-base layer) 9 in a thyristor region are so provided that they are separated from each other, and a notch part 9a is provided in the P<->-layer 9. When an n2<+>-layer (n-emitter layer) 8 in the thyristor region is contacted partly with an n<->-layer (n-base layer) 2, a thyristor current flows only through the MIS channel of one MISFET (MTR1). Therefore, the ON-voltage of a composite semiconductor device can be made low.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite semiconductor device, and more particularly to reducing the on-resistance when the semiconductor device is turned on and off by a control voltage supplied to an insulated gate, and has a high withstand voltage characteristic or The present invention relates to a composite semiconductor device having large current characteristics.

[0002]

2. Description of the Related Art Generally, a semiconductor switching element used in a power conversion device such as an inverter device is a semiconductor switching device having a high speed switching characteristic and a low loss characteristic in response to a demand for higher performance of the power conversion device. Development is flourishing.

Recently, an insulated gate bipolar transistor (IGBT) has attracted attention as a semiconductor switching element having such characteristics. This IGBT is a metal oxide semiconductor field effect transistor (MISFET).
Compared with, it has the advantage that the voltage between terminals when on, that is, the resistance when on, can be made as low as possible, and it has excellent high-speed switching characteristics even when compared with current control type devices such as gate turn-off thyristors (GTO thyristors). Since the structure of the gate circuit is simple and can be downsized, the range of applications is expanding, centering on inverter devices with relatively low power. is there.

Such an IGBT is disclosed in, for example, I.S.P.S.D. (1991), pages 220 to 225 (Proceedings of 1991).
International Symposium
on Power Semiconductor De
vice & ICs, Tokyo, pp. 220-2
25) and the like.

FIG. 15 is a schematic sectional view showing an example of the configuration of such a known IGBT, and FIG. 16 is an equivalent circuit diagram of the known IGBT shown in FIG.

In FIG. 15, 100 is a semiconductor substrate, 1
01 is one main surface of the semiconductor substrate 100, 102 is the other main surface of the semiconductor substrate 100, 103 is an n-type low impurity concentration layer (n-layer, first semiconductor layer), 104 is the n-layer 10.
3, an n-type impurity concentration layer (n layer, second semiconductor layer) higher than the n − layer 103, adjacent to the one main surface 101 side,
Reference numeral 105 denotes a first p-type high impurity concentration layer (p + layer, third semiconductor layer) adjacent to one main surface 101 side of the n layer 104, and 106 denotes an n− layer 1 on the other main surface 102 side.
A p-type layer (p layer, fourth semiconductor layer) provided in 03,
Reference numeral 107 denotes an n-type high impurity concentration layer (n + layer, fifth semiconductor layer) provided in the p layer 106, and reference numeral 108 denotes a cathode electrode (K which is arranged so as to contact the p layer 106 and the n + layer 107, respectively). ), 109 is an anode electrode (A) disposed in contact with the p + layer 105, and 110 is at least the p layer 10
6 is an insulated gate electrode (G) disposed on the surface of the insulating film 111 via the insulating film 111.

Further, in FIG. 16, TR1 is a p + layer 1
05, an n-layer 103 and a p-layer 106, and TR2 is an n-layer 103, a p-layer 106 and an n + layer 1.
07 is an npn transistor, MTR1 is an insulated gate electrode (G) 110, an n + layer 107, a p + layer 106, n.
N is a n-channel MISFET made of a layer 103, r is a lateral resistance of the p layer 106, R is an internal resistance of the n-layer 103, and the IGBT shown in FIGS.
A composite semiconductor device in which an ET (MTR1) and a pnp transistor (TR1) are combined is configured.

The IGBT (composite semiconductor device) having the above structure operates as follows.

First, when the IGBT is turned on, a negative potential is applied to the cathode electrode (K) 108, a positive potential is applied to the anode electrode (A) 109, and a cathode electrode is applied to the insulated gate electrode (G) 110. A potential more positive than the potential of (K) 108 is applied. At this time, an inversion layer (channel) is formed on the surface portion of the p layer 106 below the insulated gate electrode (G) 110, and the n + layer 107 and the n− layer 103 are short-circuited to each other, and an n channel MISFET ( MTR1)
Are turned on, the electrons (MIS current) injected from the cathode electrode (K) 108 through the n-channel MISFET (MTR1) p through the n-layer 103.
The holes flow into the 1+ layer 105, while holes are injected into the n− layer 103 from the p1 + layer 105. As a result, n-layer 1
No. 03 causes conductivity modulation due to the accumulation of these carriers, and the internal resistance R of the n− layer 103 decreases, so
T is turned on. In this case, since the lateral resistance r in the p layer 106 is designed to be sufficiently small, the parasitic thyristor (the two transistors T 1 and T 2) is composed of the n + layer 107, the p layer 106, the n− layer 103, and the p + layer 105.
R1 and TR2) are difficult to operate.

On the other hand, when the IGBT is turned off, the potential of the insulated gate electrode (G) 110 is made equal to the potential of the cathode electrode (K) 108, or more than the potential of the cathode electrode (K) 108. Also to a negative potential.
At this time, the p layer 1 below the insulated gate electrode (G) 110
The inversion layer (channel) formed on the surface portion of 06 disappears, and the electron injection path from the n + layer 107 to the n− layer 103 is blocked, so that the p1 + layer 105 to the n− layer 10
The injection of holes up to 3 is also eliminated, and this IGBT is turned off.

As described above, the IBGT having the above structure is
By injecting holes from the p1 + layer 105 to the n− layer 103, conductivity modulation of the n− layer 103, that is, its internal resistance R
The known MIS
Compared with the FET, there is an advantage that the resistance when turned on, that is, the voltage between terminals can be reduced. In addition, I
BGT is n, which is the emitter of the bipolar transistor.
The electrons of the + layer 107 are instantaneously injected or blocked by the potential of the insulated gate electrode (G) 110,
It becomes possible to perform high-speed switching operation close to that of MISFET.

Next, in addition to the above-mentioned IGBT, in recent years, a new type of composite semiconductor device has been proposed in which thyristor control is performed by an insulated gate electrode. , I.S.P.S.D. (1992) pp. 256-260 (P
rosecedings of 1992 Intern
national Symposium on Powe
rSemiconductor Device & I
Cs, Tokyo, pp. 256-260).

FIG. 17 is a schematic cross-sectional view showing the structure of the composite semiconductor device disclosed above, and FIG. 18 is an equivalent circuit diagram of the semiconductor device disclosed above.

In FIG. 17, 112 is a semiconductor substrate, 1
13 is one main surface of the semiconductor substrate 112, 114 is the other main surface of the semiconductor substrate 112, 115 is an n-type low impurity concentration layer (n-layer, first semiconductor layer), 116 is n-layer 11
5, an n-type impurity concentration layer (n layer, second semiconductor layer) higher than the n − layer 115, adjacent to the one main surface 113 side,
Reference numeral 117 denotes a first p-type high impurity concentration layer (p1 + layer, third semiconductor layer) adjacent to one main surface 113 side of n layer 116, and 118 denotes n− layer 1 on the other main surface 114 side.
The second p-type high impurity concentration layer (p2 +
P, a fourth semiconductor layer), and 119 are p-type low impurity concentration layers (n-layer 115 adjacent to the p2 + layer 118 and the p2 + layer 118) in the n− layer 115 on the other main surface 114 side. p− layer, fifth semiconductor layer), 120 is p2 + layer 1
18 and the p− layer 119, which is formed in a crotch manner on the p2 + layer 1
A first n-type impurity concentration layer higher than 18 (n1 + layer, sixth
Semiconductor layer) of the n1 + layer 1 in the p- layer 119.
20 separated from 20 and higher than the p − layer 119
N-type impurity concentration layer (n2 +, seventh semiconductor layer), 12
2 is the p− layer 11 between the n1 + layer 120 and the n2 + layer 121.
The first insulated gate electrodes (G1) and 123, which are formed to face each other on the exposed surface of 9 through an insulating film (not shown), are n-
A second insulated gate electrode (G2) and 124 are formed on the exposed surface of the p − layer 119 between the layer 115 and the p 2 + layer 118 so as to face each other via an insulating film (not shown).
8 and the cathode electrode (K) in contact with the n1 + layer 120,
125 is an anode electrode (A) in contact with the p1 + layer 117
Is.

Further, in FIG. 18, TR1 is a first p-layer formed of a p1 + layer 117, an n- layer 115 and a p- layer 119.
np transistor, TR2 is n-layer 115, p-layer 11
9, a first npn transistor composed of the n2 + layer 121, which constitutes a thyristor. MTR
1 is the first insulated gate electrode (G1) 122, n1 + layer 1
20, p− layer 119, n2 + layer 121
The channel MISFET and MTR2 are the second insulated gate electrode (G2) 123, the n2 + layer 121, the p− layer 119, and n.
A second n-channel MISFET consisting of layer 115. Further, TR3 includes p1 + layer 117, n− layer 115,
a second pnp transistor made of the p2 + layer 118, T
R4 is an n− layer 115, a p2 + layer 118, and an n1 + layer 120.
A second npn transistor consisting of, which constitutes a parasitic thyristor. Note that r1 is the p-layer 1
19 is a lateral resistance, r2 is a lateral resistance of the p2 + layer 118, and R is an internal resistance of the n− layer 115.

The composite semiconductor device having the above structure operates as follows.

First, when the composite semiconductor device is turned on, a negative potential is applied to the cathode electrode (K) 124 and a positive potential is applied to the anode electrode (A) 125.
A positive potential higher than the potential of the cathode electrode (K) 124 is applied to each of the first insulated gate electrode (G1) 122 and the second insulated gate electrode (G2) 123. At this time, an inversion layer (channel) is formed on the surface portion of the p − layer 119 below each of the first insulated gate electrode (G1) 122 and the second insulated gate electrode (G2) 123, and n1 is formed.
Between the + layer 120 and the n2 + layer 121, and the n2 + layer 1
21 and the n − layer 115 are respectively short-circuited, and the first
Since both the n-channel MISFET (MTR1) and the second n-channel MISFET (MTR2) are turned on, the first n-channel MISFET (MTR1) and the second n-channel MISFET (MTR1) from the cathode electrode (K) 124 are turned on.
Electrons injected through the SFET (MTR2) (MIS
Current) flows through the n− layer 115 into the p1 + layer 117, while holes are injected from the p1 + layer 117 into the n− layer 115. The hole current due to this hole injection is p
Reaching the layer 119, from which the cathode electrode (K) 124
When flowing in the direction, the lateral resistance r1 of the p-layer 119 causes a potential difference in the p-layer 119. When this potential difference exceeds the diffusion potential between the p- layer 119 and the n2 + layer 121 (about 0.7 V at room temperature in silicon), electrons are directly injected from the n2 + layer 121 into the n- layer 115. , By this, the first pnp transistor (TR1)
And a first npn transistor (TR2) ignite, and the composite semiconductor device is turned on. In this case, the lateral resistance r2 of the p2 + layer 118 is p
Since the 2+ layer 118 has a high impurity concentration, it is sufficiently small, and the parasitic thyristor including the second pnp transistor (TR3) and the second npn transistor (TR4) is hard to turn on.

On the other hand, when the composite semiconductor device is turned off, the potentials of the first insulated gate electrode (G1) 122 and the second insulated gate electrode (G2) 123 are made equal to the potential of the cathode electrode (K) 124. The potential is set to be negative or more negative than the potential of the cathode electrode (K) 124.
At this time, the p − layer 11 under the first insulated gate electrode (G1) 122 and the second insulated gate electrode (G2) 123 is formed.
9 Since the inversion layer (channel) formed on the surface portion disappears and the electron injection from the n2 + layer 121 to the n− layer 115 is blocked, the hole injection from the p1 + layer 117 to the n− layer 115 is also performed. It disappears, and this composite semiconductor device is turned off.

Since this composite semiconductor device (MIS gate type thyristor) uses the thyristor function,
From the cathode electrode (K) 124 to the first n-channel MIS
Since electrons supplied to the n2 + layer 119 through the FET (MTR1) spread laterally in the n2 + layer 119, the voltage between terminals at the time of on (resistance at the time of on) is known as I
It has an advantage that it can be made smaller than the GBT. Also,
This composite semiconductor device has a first insulated gate electrode (G1).
Since it can be turned on / off by applying / removing a potential of a predetermined polarity to 122 and the second insulated gate electrode (G2) 123, the structure of the gate circuit can be extremely simplified like the known IGBT. There is.

[0020]

However, in these composite semiconductor devices, the IGBT is difficult to deal with high breakdown voltage and large current as described below, and is applied to an inverter device handling a large amount of electric power. However, there is a problem that the MIS gate type thyristor is difficult to fire.

That is, FIG. 5B is an operation explanatory view showing the result of the current stream line simulation on the cathode side in the ON state of the IGBT.

As shown in FIG. 5B, the electrons flowing from the cathode electrode (K) 108 into the n − layer 103 through the inversion layer (channel) are insulated gate electrodes (G) 11
The n + storage layer formed on the surface of the n− layer 103 immediately below 0 spreads slightly in the lateral direction, but the resistance of the n + storage layer is large, so that it does not spread sufficiently. For this reason, in a portion away from the cathode electrode (K) 108 (a lower portion of the right side insulated gate electrode 110 in FIG. 16), it is difficult for current to flow, and the on-voltage increases. on the other hand,
Also in the lower region of the p layer 106, a current hardly flows due to depletion due to the potential drop of the n − layer 105. These phenomena occur remarkably as the n-layer 105 has a low impurity concentration and a high breakdown voltage. That is, the higher the breakdown voltage of the IGBT, the longer the length of the insulated gate electrode (G) 110 needs to be, and as a result, the lateral spread of the current in the n− layer 105 becomes worse. . In short, this is equivalent to a decrease in the supply of electrons from the cathode electrode (K) 108 side, so that the conductivity modulation effect in the n − layer 105 is reduced and the on-voltage in the IGBT is increased. When the withstand voltage is increased, it becomes difficult to process a large amount of electric power.

Further, the MIS gate type thyristor is
At the time of turn-on, the first insulated gate electrode (G
1) An inversion layer (channel) is formed on the surface of the p − layer 119 below the 122 and the second insulated gate electrode (G2) 123, and the first n-channel MISFET (MTR1) and the second n-channel are formed. Since the MISFET (MTR2) is turned on and the n1 + layer 120 and the n2 + layer 121 are short-circuited and the n2 + layer 121 and the n− layer 115 are short-circuited, electrons (MIS current) are generated in the cathode electrode (K).
Implanted from 124 into n-layer 115. At this time,
As is clear from the equivalent circuit shown in FIG.
The IS current is the first n-channel MISFET (MTR
1) and the second n-channel MISFET (MTR2) pass through the two inversion layers (channels), the channel resistance of these inversion layers limits the magnitude of the current. The magnitude of the hole current injected into 115 is also reduced, and the first pnp transistor (TR1) and the second npn transistor (TR2) are also included.
A thyristor consisting of is difficult to fire. In order to prevent this, the area (channel width) of the second n-channel MISFET (MTR2) is widened, or the n2 + layer 1 is formed.
Although it is conceivable to reduce the area of No. 21, since these means are nothing but to reduce the arrangement area of the thyristor region through which the main current flows in the entire composite semiconductor element, the inter-terminal voltage (ON time) is turned on. Resistance becomes large, and problems similar to those of known IGBTs occur.

The present invention eliminates the above-mentioned problems, and an object thereof is to reduce the voltage between terminals at the time of ON (resistance at the time of ON), and to achieve high breakdown voltage and large current. To provide a composite semiconductor device.

[0025]

In order to achieve the above object, the present invention provides a semiconductor substrate having a pair of main surfaces, a first semiconductor layer of a first conductivity type having a low impurity concentration, and one of A second semiconductor layer of the second conductivity type having a high impurity concentration, which is disposed adjacent to the first semiconductor layer on the main surface of the second semiconductor layer, and one side of the semiconductor substrate in the first semiconductor layer on the other main surface. A plurality of strip-shaped high-concentration second-conductivity-type third semiconductor layers that are parallel to each other and are spaced apart from each other, and the longitudinal direction in each of the plurality of third semiconductor layers. A fourth semiconductor layer of the first conductivity type having a high impurity concentration provided along the first semiconductor layer on the other main surface, and a third semiconductor layer having two side edges in the third semiconductor layer. The high impurity concentration At least a first-conductivity-type fifth semiconductor layer is provided between the first semiconductor layer and the fifth semiconductor layer, and is in direct contact with the first semiconductor layer and the fifth semiconductor layer. A semiconductor substrate composed of a sixth semiconductor layer of the second conductivity type having a low impurity concentration having one cutout portion, and a first semiconductor element arranged in a low resistance contact state with the second semiconductor layer on the one main surface. Main electrode, a second main electrode arranged in low resistance contact with each of the third semiconductor layer and the fourth semiconductor layer on the other main surface, and the fourth main electrode on the other main surface. A semiconductor layer and a control electrode facing the third semiconductor layer between the fifth semiconductor layer and the exposed third semiconductor layer.

In order to achieve the above-mentioned object, the present invention is a semiconductor substrate having a pair of main surfaces, a first semiconductor layer of the first conductivity type having a low impurity concentration, and one main surface. The second semiconductor layer of the second conductivity type having a high impurity concentration disposed adjacent to the first semiconductor layer and the first semiconductor layer on the other main surface are provided in parallel to one side of the semiconductor substrate. A strip-shaped high impurity concentration second conductive type third semiconductor layer, and a high impurity concentration first conductive type fourth semiconductor layer provided in the third semiconductor layer along the longitudinal direction thereof.
Second semiconductor layer and the first semiconductor layer on the other main surface, the first conductivity type of high impurity concentration provided so that one side edge portion is in contact with the side edge portion of the third semiconductor layer. A fifth semiconductor layer, and a high-concentration first-conductivity-type sixth semiconductor layer, which is arranged in parallel with the fifth semiconductor layer in the first semiconductor layer on the other main surface, The first
Between the semiconductor layer and the sixth semiconductor layer, one side edge portion of which is provided so as to contact the side edge portion of the fifth semiconductor layer, and a high impurity concentration second conductivity type seventh A semiconductor layer,
An eighth semiconductor layer of the second conductivity type, which is provided on the inner surface of the third semiconductor layer between the fourth semiconductor layer and the fifth semiconductor layer and has a low impurity concentration; and the fifth semiconductor A semiconductor substrate, which is provided on the inner surface of the seventh semiconductor layer between the second semiconductor layer and the sixth semiconductor layer, and includes a ninth semiconductor layer of the first conductivity type having a high impurity concentration, and the one main surface. In a low resistance contact state on the second semiconductor layer in
Main electrode, a second main electrode arranged in a low resistance contact state with each of the third semiconductor layer and the fourth semiconductor layer on the other main surface, and the second main electrode on the other main surface. A fourth semiconductor layer and a first semiconductor layer, which is disposed so as to face the eighth semiconductor layer exposed between the fifth semiconductor layer and the fourth semiconductor layer.
Second control electrode and a second control electrode facing the ninth semiconductor layer exposed between the fifth semiconductor layer and the sixth semiconductor layer. Prepare

[0027]

According to the first means, since only one MISFET is provided in the IGBT formation region, the electrons supplied from the cathode electrode through the channel of the MISFET sufficiently spread in the thyristor formation region. As a result, the inter-terminal voltage (resistance when on) of the composite semiconductor device when it is on can be made sufficiently low. Further, the first semiconductor layer (n− layer) and the fifth semiconductor layer (n2− layer) are provided between the first semiconductor layer (n− layer) and the fifth semiconductor layer (n2 + layer).
Since the sixth semiconductor layer (p− layer) having at least one cutout portion that directly contacts the + layer) is provided, the n− layer (n emitter layer) in the thyristor formation region is partially n.
It comes into contact with the 2+ layer (n base layer), and the MIS current required to ignite the thyristor region is one MIS.
Since it flows only through the channel resistance of the FET, the thyristor can be easily ignited by providing a relatively small IGBT region or MIS region, and the thyristor exists in the IGBT region.
Both the IGBT current and the thyristor current can be controlled by the individual MISFETs, and as a result, the composite semiconductor device can have a high breakdown voltage and a high current.

Further, according to the second means, the first semiconductor layers (n-layer) are provided on the surface of the first semiconductor layer (n-layer) so as to be spaced apart from each other.
A conductive type fourth semiconductor layer (n1 + layer) having a high impurity concentration,
Fifth semiconductor layer (n2 + layer), sixth semiconductor layer (n3 +)
Layers) respectively, and at least between the fourth semiconductor layer (n1 + layer) and the fifth semiconductor layer (n2 + layer), the second conductive type third semiconductor layer (p2 +) having a high impurity concentration is provided.
Layer), and between the fifth semiconductor layer (n2 + layer) and the sixth semiconductor layer (n3 + layer), the second conductivity type eighth low impurity concentration layer.
Although the first and second MISFETs are formed by providing the semiconductor layer (p-layer) of the first MISFET, the MIS current required to ignite the thyristor region is the first MISFE.
The first semiconductor layer (n−
Layer), the thyristor can be easily ignited, while the thyristor current (electron current) flows through the first and second MISFETs, but the second MISFET.
Since the FET is a depletion type with a small channel resistance, it is substantially equivalent to that flowing through the first MISFET, and the inter-terminal voltage (ON resistance) of the composite semiconductor device at ON time can be made sufficiently low. As a result, it is possible to increase the breakdown voltage and current of the composite semiconductor device.

[0029]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows the structure of a first embodiment of a composite semiconductor device according to the present invention. FIG. 1A is a schematic perspective sectional view in which a cathode electrode and an insulating film are partially removed. , (B) are plan views in which the cathode electrode and the insulating film are also partially removed.

In FIGS. 1A and 1B, 1 is a semiconductor substrate, 1a is one main surface thereof, 1b is the other main surface thereof, and 2 is adjacent to one main surface 1a side of the semiconductor substrate 1. The n-type low impurity concentration layer (n-layer, first semiconductor layer) 3 is an n-type impurity layer (n-layer) having a higher concentration than the n-layer 2 adjacent to the one main surface 1a side of the n-layer 2. , The first semiconductor layer), 4
Is a first p-type high impurity layer (p1 + layer, second semiconductor layer) adjacent to one main surface 1a of the n layer 3, and 5 is a semiconductor substrate in the n− layer 2 on the other main surface 1b. Two strip-shaped p-type impurity layers (p layer, third semiconductor layer) provided in parallel to one pair of opposing sides and spaced apart from each other;
Reference numeral 6 denotes two strip-shaped second p-type high impurity layers (p2 + layer, third semiconductor layer) also provided in a part of the two strip-shaped p layers 5 along the longitudinal direction of the p layer 5. , 7 are two strip-shaped first n-type high impurity layers (n1 + layer, fourth semiconductor layer) provided in a part of the two strip-shaped p2 + layers 6 along the longitudinal direction of the p2 + layer 6. ), 8 is the other main surface 1b
In the n-layer 2 in which the two edges are two strips of p.
A second n-type high impurity concentration layer (n2 + layer, fifth semiconductor layer) 9 is provided between the n− layer 2 and the n2 + layer 8 so as to be in contact with the opposite side edges of the layer 5, respectively. The
A p-type low impurity concentration layer (p- layer, sixth semiconductor layer) having a plurality of cutouts 9a for partially directly contacting the n− layer 2 and the n2 + layer 8, 10 is the n1 + layer 7 and the n2 + layer 8 Between the two elongated insulating gate electrodes (G) placed on the surface of the p layer 5 exposed between the insulating layer 11 and the insulating layer 11 and a part of the exposed surface of the n1 + layer 7 and two insulating gate electrodes. Gate electrode (G) 10
An insulating film provided so as to cover the exposed surface of the n2 + layer 8, and 13 are anode electrodes (A) provided in a low resistance contact state on one main surface 1a side of the p1 + layer 4;
Is a cathode electrode (K) provided on each exposed surface of the p2 + layer 6 and the n1 + layer 7 in a low resistance contact state and covering the insulating film 12.

The n− layer 2 and the n layer 3 form a first semiconductor layer, and the p layer 5 and the p2 + layer 6 form a third semiconductor layer. n− layer 2, n layer 3, p1 + layer 4, p layer 5,
The p2 + layer 6, the n1 + layer 7, the n2 + layer 8 and the p− layer 9 constitute the semiconductor substrate 1 as a whole. The plurality of cutouts 9a provided in the p- layer 9 are formed in a strip shape, and are substantially orthogonal to the pair of opposed sides of the semiconductor substrate 1, that is, in the longitudinal direction of the insulated gate electrode (G) 12. Insulated gate electrode (G) that extends in a direction substantially orthogonal to each other
They are arranged at equal intervals along the longitudinal direction of 12. In this case, in the arrangement portion of the p− layer 9, the p− layer 9 is interposed between the n− layer 2 and the n2 + layer 8, but the cutout portion 9 of the p− layer 9 is formed.
In the arrangement portion of a, the n− layer 2 and the n2 + layer 8 are notched 9a.
Are directly connected through. Further, the two insulated gate electrodes (G) 12 are electrically connected to each other at a position not shown.

Next, FIG. 2 shows the line A- shown in FIG.
It is a cross-sectional view of an A line portion and a BB line portion,
FIG. 3 is a cross-sectional view of the CC line portion shown in FIG.

2 and 3, in FIG. 1 (a),
The same components as those shown in (b) are designated by the same reference numerals.

Then, as shown in FIG. 2 and FIG.
The p-layer 9 includes the n-layer 2 except for the portion where the cutout 9a is arranged.
And n2 + layer 8 interposed between the n− layer 2 and the n2 + layer 8
Although the direct contact with and is avoided, the disposition portion of the cutout portion 9a of the p − layer 9 is configured such that the n − layer 2 and the n 2+ layer 8 are in direct contact with each other.

FIG. 4 is a circuit diagram showing an electrically equivalent circuit of the composite semiconductor device shown in FIGS. 1 (a) and 1 (b).

In FIG. 4, TR1 is p1 + layer 4, n-
First pnp transistor consisting of layer 2, p-layer 9, T
R2 is a first npn transistor composed of an n− layer 2, a p− layer 9 and an n2 + layer 8, and TR3 is a p1 + layer 4, an n− layer 2,
Second pnp transistor, TR4, consisting of p2 + layer 6
Is a second n formed of the n− layer 2, the p2 + layer 6, and the n1 + layer 7.
pn transistor, MTR1 is an insulated gate electrode (G) 1
0, n1 + layer 7, p layer 5, and n2 + layer 8 are n channel MISFETs, r ₀ is a lateral resistance in the p− layer 9,
r ₁ is the lateral resistance in the p2 + layer 6, R is the internal resistance of the n− layer 2, and the same components as those shown in FIGS. 1A and 1B are denoted by the same reference numerals. ing.

Then, the first pnp transistor (TR
1) and the first npn transistor (TR2) form a thyristor, and an n-channel MISFET (M
TR1) and the second pnp transistor (TR3) and the second npn transistor (TR4)
T is formed.

Thus, this composite semiconductor device is shown in FIG.
As can be seen from the equivalent circuit of 1), the IGBT and the thyristor can be regarded as a composite semiconductor device in which their cathode sides are commonly connected by a MISFET (MTR1).

Here, the operation of the composite semiconductor device having the above structure will be described.

First, when the composite semiconductor device is turned on, a negative potential is applied to the cathode electrode (K) 14 and a positive potential is applied to the anode electrode (A) 13, and the insulated gate electrode (G) 10 is applied. A potential more positive than the potential of the cathode electrode (K) 14 is applied. At this time, an inversion layer (channel) is formed on the surface portion of the p layer 5 below the insulated gate electrode (G) 10, and the n1 + layer 7 and the n2 + layer 8 are connected via this inversion layer, and n Channel MISFET (MT
Since R1) turns on, the cathode electrode (K) 14 to n
Electrons (MIS current) injected through the channel MISFET (MTR1) flow from the n2 + layer 8 through the n− layer 2 into the p1 + layer 4, and the first npn transistor (TR1) is turned on to turn on the p1 + layer. Holes (hole current) from 4 are injected into the n-layer 2. This hole current is then transferred to the p-layer 9 and the n-channel MISFET.
When flowing into the p layer 5 through (MTR1), the potential of the p− layer 9 rises due to the large lateral resistance r ₀ in the p layer 5, and a potential difference is generated between the p− layer 9 and the n2 + layer 8. When this potential difference exceeds the diffusion potential between the p− layer 9 and the n2 + layer 8 (in silicon, about 0.7 V at room temperature), the first npn transistor (TR2) is turned on, and electrons are n2 + layer 8. From the first pnp transistor (TR1).
And a first npn transistor (TR2) ignite a thyristor, and the composite semiconductor device is turned on.

In this case, the lateral resistance r of the p2 + layer 6 is
₁ is sufficiently small because the p2 + layer 6 has a high impurity concentration, and n1 + layer 7, p2 + layer 6, n− layer 2, p1 + layer 4
The parasitic thyristor consisting of is extremely difficult to turn on. Further, the n layer 3 having a relatively high impurity concentration is
A hole injection efficiency is suppressed in the pn transistor (TR1) and the second npn transistor (TR3), which is inserted to prevent the parasitic thyristor from latching up and to reduce the loss caused by the tail current at turn-off. There is something. Therefore, the impurity concentration and the thickness of the n layer 3 are appropriately set according to the required characteristics of the composite semiconductor device. The means for suppressing the hole injection efficiency is not limited to the means for setting the n-layer 3, and other means having the same function may be used. For example, the n layer 3 may be partially short-circuited to the anode electrode (A) 13 or the p1 + layer 4 and n
The junction of the layer 2 may be provided with known means for reducing the minority carrier lifetime.

On the other hand, when the composite semiconductor device is turned off, the applied potential of the insulated gate electrode (G) 10 is changed to
The applied potential is the same as that of the cathode electrode (K) 14 or is more negative than the applied potential of the cathode electrode (K) 14. At this time, the inversion layer (channel) formed on the surface portion of the p layer 5 below the insulated gate electrode (G) 10 disappears, and the injection of electrons flowing from the n1 + layer 7 to the n2 + layer 8 is blocked, Accordingly, the injection of electrons flowing from n2 + layer 8 to n− layer 2 is blocked, so that the injection of holes from p1 + layer 4 to n− layer 2 is also stopped, and this composite semiconductor device is turned off.

Next, FIG. 5A is a state explanation showing the result of the current streamline simulation on the cathode side when the composite semiconductor device is in the ON state in the partial cross section taken along the line BB of the composite semiconductor device shown in FIG. It is a figure.

In FIG. 5A, FIGS. 1A and 1B are shown.
The same components as the components shown in FIG.

As shown in FIG. 5A, this composite semiconductor device has a cathode electrode compared with the current stream line on the cathode side when the known IGBT shown in FIG. Since the electrons supplied from the (K) 14 through the channel of the MISFET (MTR1) have spread sufficiently in the thyristor region and are flowing uniformly, the voltage across the terminals at the time of the on-state (when the on-state is higher than that of the known IGBT). Resistance) can be made sufficiently low. In addition, this composite semiconductor device is a p− having a plurality of notches 9a between the n2 + layer 8 and the n− layer 2.
Layer 9 is inserted and arranged, and n2 + layer 8 and n− in the thyristor region are arranged.
Since a part of the MISFET (MTR1) is brought into contact with the layer 2, it is possible to control both the MIS current and the thyristor current. That is, the MIS current required to fire the thyristor is
Only one channel resistance of the ET (MTR1) needs to be passed, while the thyristor current is also MISFET (MTR1).
Since only one channel resistance of 1) is passed, the thyristor can be easily ignited only by having a small MISFET region (channel width). And MI
If the SFET region (channel width) can be made small, the area of the thyristor region in the entire composite semiconductor device can be made large, and thereby the inter-terminal voltage (ON resistance) at ON time can be sufficiently reduced. Therefore, it is possible to easily achieve high breakdown voltage or high current of the composite semiconductor device. Further, compared with the known semiconductor device, the installation area of the insulated gate electrode (G) 10 can be remarkably reduced, so that the charging / discharging current of the gate can be reduced, and the switching operation can be speeded up and the gate circuit can be downsized. There is also an advantage.

In addition to this, this composite semiconductor device can be easily turned on / off by applying / removing a potential of a predetermined polarity to the insulated gate electrode (G) 10, and
Since the saturation characteristic of the n-channel MISFET (MTR1) is used, it has a characteristic that it has a current limiting action despite the thyristor operation. In general,
When commercializing this composite semiconductor device, as shown in FIG.
The structure shown in (b) is used as one cell, and hundreds to tens of thousands of the cells are integrated in the same semiconductor substrate.
Connections are made so that they operate in parallel, but in this parallel operation, if each cell has a current limiting effect, current will concentrate in a specific one cell or a small number of cells. Since each cell evenly shares the current, there is also an advantage that it is possible to prevent the destruction of the composite semiconductor device due to the current concentration.

Next, FIG. 6, FIG. 7, and FIG. 8 are second, third, and fourth structures in which the notch portion of the p- layer 9 and the arrangement position are changed in the composite semiconductor device shown in FIG. 9 is a schematic plan view showing an example of FIG. 9A, FIG. 9B, FIG.
Is the AA line portion, the BB line portion, the CC line portion, the DD line portion and the E- of FIG. 6, FIG. 7 and FIG.
6 to 9 (a), (b), and (c), which are cross-sectional views of the E line portion, 9b is a second shape notch, 9c is a third shape notch, and 9d is a fourth shape. In addition, the same components as those shown in FIGS. 1A and 1B are denoted by the same reference numerals.

The second shape notch 9b is formed in a short strip shape, and is substantially orthogonal to the pair of opposed sides of the semiconductor substrate 1, that is, substantially in the longitudinal direction of the insulated gate electrode (G) 12. The insulating gate electrode (G) 12 extends in the width direction of the p − layer 9 in the direction orthogonal to each other, and
Are arranged at equal intervals along the longitudinal direction. The notch 9c of the third shape is formed in a long strip shape, extends in a direction parallel to a pair of opposite sides of the semiconductor substrate 1, that is, in the longitudinal direction of the insulated gate electrode (G) 12, and has p− Layer 9
Are arranged along the middle portion in the width direction. Also, the fourth
The notch 9d has a circular shape and is parallel to a pair of opposing sides of the semiconductor substrate 1, that is, along the longitudinal direction of the insulated gate electrode (G) 12 and in the p-layer 9. They are arranged at equal intervals in the middle portion in the width direction.

In this case, as shown in FIGS. 6 and 9A and 9B, the second shape notch 9b is formed by n2 + layers 8 and n.
-The contact portion with the layer 2 is limited to the portion adjacent to the insulated gate electrode (G) 10, and such a cutout portion 9 is formed.
When the p-layer 9 having b is used, as compared with the case where the p-layer 9 having the cutout portion 9a shown in FIGS. 1A and 1B is used, the arrangement region of the p-layer 9, that is, Since the non-contact portion between the n2 + layer 8 and the n− layer 2 can be increased, the voltage between terminals when the composite semiconductor device is on (resistance when it is on) can be reduced. In addition, as shown in FIGS. 7 and 9C,
The notch 9c having the third shape is provided at a contact portion between the n2 + layer 8 and the n− layer 2 at a portion separated from the insulated gate electrode (G) 10 and at a strip portion parallel to the insulated gate electrode (G) 10. However, since the thyristor region adjacent to the n-channel MISFET (MTR1) can be enlarged by using the p − layer 9 having such a cutout 9c, the inter-terminal voltage (on-state) of the composite semiconductor device (on Resistance) can be reduced. 8 and 9 (a),
As shown in (c), the notch 9d of the fourth shape has n2 +
The contact portion between the layer 8 and the n-layer 2 is connected to the insulated gate electrode (G).
When the p− layer 9 having such cutouts 9d is used, the p− layer 9 is provided so as to be isolated and scattered in a portion apart from 10, as in the case of using the cutouts 9b having the third shape.
The arrangement region of the layer 9, that is, the non-contact portion between the n2 + layer 8 and the n− layer 2 can be increased, and moreover, as in the case of using the notch 9c of the fourth shape, the n-channel MISFET (MTR
Since the thyristor region adjacent to 1) can be enlarged, the voltage between terminals when the composite semiconductor device is on (resistance when it is on) can be reduced.

The shape of the notch provided in the p-layer 9 is as follows.
The cutout portion 9a shown in FIGS. 1A and 1B and the cutout portions 9b, 9c, and 9d having the second to fourth shapes are not limited to the cutout portions 9a, 9c, and 9d, and cutout portions having other shapes may be provided. . in this case,
If the total area of the cutouts in the p- layer 9 is reduced, that is, the area of the contact portion between the n2 + layer 8 and the n- layer 2 is reduced, the inter-terminal voltage of the composite semiconductor device (the on-state resistance) is reduced. ) Can be reduced and the risk of lowering the breakdown voltage is reduced, which is preferable.

Therefore, in this composite semiconductor device,
Within the range that does not impair the ignition and extinction characteristics, the p-layer 9
It is desirable to adopt a planar structure in which the total area of the cutout portions is minimized.

Next, FIG. 10 is a schematic sectional view showing the structure of a second embodiment of the composite semiconductor device according to the present invention.

In FIG. 10, 15 is the other main surface 1b.
On the n− layer 2, the third n-type high impurity concentration layer (n3 + layer, sixth semiconductor layer) spaced apart from the n2 + layer 8 is provided between the n2 + layer 8 and the n3 + layer 15, and n −
P interposed between the layer 2 and the n3 + layer 15 respectively
The type impurity layer (p layer, seventh semiconductor layer) 17, 17 is a second p type low impurity concentration layer (p2−) provided on the surface of the p2 + layer 6 exposed between the n1 + layer 7 and the n2 + layer 8. Layer, eighth semiconductor layer), 18 is a fourth n-type impurity layer (n4 layer, ninth semiconductor layer) provided on the surface of the p layer 16 exposed between the n2 + layer 8 and the n3 + layer 15. , 19 is a first insulated gate electrode (G1) mounted and formed on the surface of the p2-layer 17 via the insulating layer 11, and 20 is an insulating layer 1 on the surface of the n4 layer 18.
Second insulated gate electrode (G
2), and MTR1 is the first insulated gate electrode (G1)
19, n1 + layer 7, p2 + layer 6 provided with p2-layer 17,
The first MISFET MTR2 formed of the n2 + layer 8 is the second M formed of the second insulated gate electrode (G2) 20, the p layer 16 provided with the n2 + layer 8 and the n4 layer 18, and the n3 + layer 15.
It is an ISFET, and other components that are the same as those shown in FIGS. 1A and 1B are denoted by the same reference numerals.

The difference between the second embodiment and the above-mentioned first embodiment is that the first embodiment has a p- having a notch 9a between the n- layer 2 and the n2 + layer 8. Whereas the layer 9 is provided, the second embodiment does not provide such a p-layer 9 and the first embodiment has a second MISFET.
The second embodiment has only the second MISFET (MTR2), whereas the second embodiment has no (MTR2). Since there is no difference in structure between them, further description of the structure of the second embodiment will be omitted.

FIG. 11 is a circuit diagram showing an electrically equivalent circuit of the composite semiconductor device shown in FIG.

In FIG. 11, TR1 is the p1 + layer 4, n
A first pnp transistor consisting of layer 2 and p layer 16;
TR2 is a first npn transistor including the n− layer 2, p layer 16 and n3 + layer 15, TR3 is a second pnp transistor including the p1 + layer 4, n− layer 2 and p2 + layer 6, and T3.
R4 is a second layer composed of the n− layer 2, the p2 + layer 6, and the n1 + layer 7.
Npn transistor, MTR1 is a p provided with a first insulated gate electrode (G1) 19, an n1 + layer 7, and a p2-layer 17.
A first MISFET M composed of a 2+ layer 6 and an n2 + layer 8,
TR2 is the second insulated gate electrode (G2) 20, n2 + layer 8, and second MISFET including the n3 + layer 15 provided with the n4 + layer 18, and r ₀ is the lateral resistance in the p layer 16, r ₁ Is the lateral resistance in the p2 + layer 6, and the same components as those shown in FIG. 10 are denoted by the same reference numerals.

Then, the first pnp transistor (TR
1) and the first npn transistor (TR2) form a thyristor, and the first MISFET (MTR
2), the second pnp transistor (TR3) and the second
An IGBT is formed by the npn transistor (TR4).

Also in this embodiment, as shown in the equivalent circuit of FIG. 11, the IGBT and the thyristor are commonly connected on the cathode side thereof by the first MISFET (MTR1) to form a composite semiconductor device. is there.

FIG. 12 is a characteristic diagram showing the operating state of the composite semiconductor device of the second embodiment.
(A) shows the flow of carriers in the composite semiconductor device,
(B) shows the impurity concentration distribution in the cross section of the AA line and the cross section of the BB line.

As can be seen from FIG. 12B, the p2-layer 17 provided on the surface of the p2 + layer 6 has a low impurity concentration in the cross-section of the line AA, and as a result, n The threshold voltage of the channel MISFET (MTR1) is adjusted to a predetermined value. Further, in the cross section of the B-B line, the n layer MISFET (MTR) is provided by the n layer 18 provided on the surface of the p layer 16.
2) is a depletion type or normally-on type. In this case, these MISFETs (MTR1, M
TR2) first and second insulated gate electrodes (G1, G
2) 19 and 20 are electrically connected to each other at a position not shown.

Here, the operation of the composite semiconductor device of the second embodiment having the above-mentioned structure is as follows.

First, when the composite semiconductor device is turned on, a negative potential is applied to the cathode electrode (K) 14 and a positive potential is applied to the anode electrode (A) 13, respectively.
Further, a positive potential higher than that of the cathode electrode (K) 14 is applied to the second insulated gate electrodes (G1, G2) 19 and 20. At this time, p on the lower side of the first insulated gate electrode (G1) 19 is
Since the inversion layer (channel) is formed in the 2-layer 17 and the n1 + layer 7 and the n2 + layer 8 are connected through this channel, the first MISFET (MTR1) is turned on.
From the cathode electrode (K) 14 to the first MISFET (MT
The electrons (MIS current) injected through R1) are n2
Flows from the + layer 8 through the n − layer 2 into the p1 + layer 4, and the first pnp transistor (TR1) is turned on,
Holes (hole current) are injected from the p1 + layer 4 into the n− layer 2. At this time, when this hole current flows into the p layer 16, the potential of the p layer 16 rises due to the lateral resistance r ₀ , and a potential difference occurs between the p layer 16 and the n3 + layer 15. Then, when this potential difference exceeds the diffusion potential of the p layer 16 and the n3 + layer 15 (in silicon, about 0.7 V at room temperature), the first npn transistor (TR2) is turned on and the cathode electrode (until that time). (K) The electrons flowing from the n3 + layer 15 through the first MISFET (MTR1) and the second MISFET (MTR2) that are also in the ON state are injected from the n3 + layer 15 into the n− layer 2 directly. Therefore, the first pnp transistor (TR1) and the second npn transistor (TR2)
The thyristor consisting of ## EQU1 ## is ignited, and this composite semiconductor device is turned on.

In this case, the lateral resistance r ₁ of the p2 + layer 6
Is sufficiently small because the p2 + layer 6 has a high impurity concentration, and the parasitic thyristor including the n1 + layer 7, the p2 + layer 6, the n− layer 2, and the p1 + layer 4 is extremely difficult to turn on.

On the other hand, when the composite semiconductor device is turned off, the first and second insulated gate electrodes (G1, G
2) Make the potentials of 19 and 20 equal to the potential applied to the cathode electrode (K) 14, or make the cathode electrode (K) 1
The applied potential of 4 is made negative. At this time, the inversion layer (channel) formed in the p2-layer 17 below the first insulated gate electrode (G1) 19 disappears, and the n1 + layers 7 to n are formed.
The injection of electrons flowing into the 2+ layer 8 is blocked, and the first MIS
The FET (MTR1) is turned off. As a result, electrons (MIS current) flowing from the n1 + layer 7 to the n− layer 2 and n
1+ layer 7 through n2 + layer 8 and n3 + layer 15 to n−
Since the electrons (MIS current) flowing in the layer 2 are cut off together, holes are not injected from the p1 + layer 4 to the n− layer 2 and the composite semiconductor device is turned off.

In this case, the second n-channel MISFET
Since the (MTR2) is a depletion type, it is difficult to turn it off, but the first n-channel MISFET (MTR2)
If 1) is turned off, the composite semiconductor device is turned off, so there is no particular problem.

As described above, in the composite semiconductor device according to the second embodiment, the MIS current required for firing the thyristor is the first n-channel MISFET (MTR).
1) only needs to pass through the channel resistance of 1), while the thyristor current is the first n-channel MISFET (MTR).
1) and 2 of the second n-channel MISFET (MTR2)
Must pass through one channel, but the second n-channel M
Since the ISFET (MTR2) is a depletion type, its channel resistance is extremely small, so that the thyristor current is substantially equal to the first n-channel MISFET (MT).
It becomes equivalent to R1) passing through only the channel resistance, and it is possible to sufficiently reduce the voltage between terminals at the time of on (resistance at the time of on), and easily achieve high breakdown voltage or large current of the composite semiconductor device. be able to.

Also, the composite semiconductor device of the second embodiment has the same polarity as the first and second insulated gate electrodes (G1, G2) 19, 20 as in the first embodiment. It can be easily turned on / off by applying / removing a potential, and the first n-channel MISFET (MT
Since the saturation characteristic of R1) is utilized, it has a current limiting action despite the thyristor operation. Therefore, in the case where one cell having the structure shown in FIG. 10 is integrated, hundreds to tens of thousands of the cells are integrated in the same semiconductor substrate, and the cells are connected to operate in parallel. Also, since each cell has its own current limiting effect, the current is not concentrated in a specific one cell or a small number of cells, and each cell evenly shares the current,
There is an advantage that the composite semiconductor device can be prevented from being destroyed due to current concentration.

Furthermore, this second embodiment is based on the above-mentioned first embodiment.
Compared with the embodiment described above, the ignition characteristics of the thyristor and the reproducibility of the on-voltage are excellent, and there is an advantage that it is easy to manufacture. That is, in the first embodiment, the formation positions of the notches 9a to 9d in the p− layer 9, that is, the n2 + layer 8 are formed.
If the portion directly contacting the n-layer 2 is displaced to the left or right due to the relationship of the photomask alignment accuracy when the p-layer 9 is formed, the size of the cutouts 9a to 9d (the portion directly contacting). Alternatively, the distance between the cutouts 9a to 9d (the portion that directly contacts) and the insulated gate electrode (G) 10 deviates from the designed value. As a result, the MIS current for firing the thyristor fluctuates each time the composite semiconductor device is manufactured, or the magnitude of the thyristor current changes, and the ON voltage fluctuates each time the composite semiconductor device is manufactured. There are cases. On the other hand, in the second embodiment, the contact portion between the n− layer 2 and the n2 + layer 8 can be manufactured by the gate self-alignment technique, so that the first mask can be manufactured independently of the alignment accuracy of the photomask. And the second
Of the insulated gate electrodes (G1, G2) 19 and 20. Therefore, in the second embodiment, the area and the position of the portion where the n− layer 2 and the n2 + layer 8 are in contact do not vary each time the composite semiconductor device is manufactured, and the characteristics and quality are constant. A composite semiconductor device can be obtained.

In addition to this, the second embodiment has the first n
The threshold voltage of the channel MISFET (MTR1) is p
It is controlled by the impurity concentration of the p2-layer 17 provided on the surface of the 2+ layer 6, and does not depend on the impurity concentration of the p2 + layer 6. Therefore, the impurity concentration of the p2 + layer 6 can be set sufficiently high, and moreover, it can be provided so as to surround the n1 + layer 7. Since the lateral resistance r ₁ of the p2 + layer 7 below the n1 + layer 7 can be made smaller than that of the first embodiment described above, the n1 + layer 7, the p2 + layer 6, the n− layer 2 and the p1 + layer are formed. The parasitic thyristor made of the layer 4 is extremely difficult to turn on, and is characterized in that it can achieve a larger current.

In this case, the p2-layer 17 provided on the surface of the p2 + layer 6 and the n4 layer 1 provided on the surface of the p layer 16
8 is formed by providing the p2 + layer 6 and the p layer 16 and then ion-implanting a compensation n-type impurity into the surface thereof.
They can be formed simultaneously and easily and do not require any special manufacturing technique.

The means for ion-implanting the n-type impurity for compensation into the respective surfaces of the p2 + layer 6 and the p layer 16 can be similarly applied to the first embodiment described above. That is, FIG.
The p-layer 5 shown in (a) is made to have a high impurity concentration, or the p-layer 5 is replaced with a p2 + layer 6, and a compensation n-type impurity is ion-implanted into the surface of the p-layer 5 to obtain a lower impurity concentration. This can be realized by providing the p layer.

Next, FIG. 13 is a structural diagram showing a structural example of a composite semiconductor device similar to that of the second embodiment.
Is a schematic sectional perspective view, and (b) is a schematic plan view.

In FIG. 13, reference numeral 21 denotes an insulating film, and the other constituent elements that are the same as those shown in FIG. 10 are given the same reference numerals. 13 (a) and 13 (b), the cathode electrode (K) and the insulating film are partially removed to make the internal structure easy to understand.

The difference between this configuration example and the second embodiment is that the cathode electrode (K) 14 is arranged as follows.
In this configuration example, ohmic contact is made to the n1 + layer 7 and the p2 + layer 6, respectively, and the first and twelfth insulated gate electrodes (G1, G2) 19, 20 and the n2 + layers 8, n3 are formed.
The + layer 15 is electrically insulated from each other by the insulating film 21 and is provided so as to cover the entire surface of the other main surface 1b, whereas the second embodiment has the n1 + layer 7 and the p2 + layer 6 respectively. Only the ohmic connection is made, and it is not extended to parts other than the connection part, and in addition,
There is no structural difference between this structural example and the second embodiment.

According to this configuration example, the cathode electrode (K)
Not only fine processing of 14 is unnecessary, but the electric resistance between the cathode electrode (K) 14 and the n1 + layer 7 and the p2 + layer 6 can be reduced, and the efficiency of heat radiation from the semiconductor substrate 1 can be improved. . In this configuration example as well, the first and second insulated gate electrodes (G1, G2) 1
Reference numerals 9 and 20 are connected to each other at locations not shown.

Subsequently, FIG. 14 is an electric circuit diagram showing an example of an inverter device for driving a motor constructed by using the composite semiconductor device of the present invention.

In FIG. 14, T ₁ and T ₂ are a pair of DC terminals connected to a DC power source, and T ₃ , T ₄ and T ₅ are the same number of AC terminals as the number of AC side phases connected to a three-phase induction motor. , S
W ₁₁ , SW ₁₂ , SW ₂₁ , SW ₂₂ , SW ₃₁ , SW ₃₂ are the composite semiconductor devices of the present invention, D ₁₁ , D ₁₂ , D ₂₁ , D ₂₂ , D ₃₁ ,
D ₃₂ is a flywheel diode, SB ₁₁ , SB ₁₂ , S
B ₂₁ , SB ₂₂ , SB ₃₁ , and SB ₃₂ are snubber circuits configured by connecting a capacitor in series to a parallel circuit of a diode and a resistor.

Then, the composite semiconductor device SW ₁₁ of the present invention,
Two of SW ₁₂ , SW ₂₁ , SW ₂₂ , SW ₃₁ , and SW ₃₂ are connected in series to form a series connection circuit for three phases, and the series connection circuit is connected between the pair of DC terminals T ₁ and T ₂ . Connected. In this case, two composite semiconductor devices SW ₁₁ and S
The series connection points of W ₁₂ , SW ₂₁ , SW ₂₂ , SW ₃₁ , and SW ₃₂ are connected to AC terminals T ₃ , T ₄ , and T ₅ , respectively.
Flywheel diodes D ₁₁ , D ₁₂ , D ₂₁ , D ₂₂ , D
₃₁ and D ₃₂ are composite semiconductor devices SW ₁₁ , SW ₁₂ , and S, respectively.
Anti-parallel connection to W ₂₁ , SW ₂₂ , SW ₃₁ , SW ₃₂ , snubber circuits SB ₁₁ , SB ₁₂ , SB ₂₁ , SB ₂₂ , SB ₃₁ , SB ₃₁ , SB.
_{32 is} also a composite semiconductor device SW ₁₁ , SW ₁₂ , SW ₂₁ ,
Connected in parallel to SW ₂₂ , SW ₃₁ , and SW ₃₂ ,
An inverter device for driving a motor is configured.

This electric motor driving inverter device is provided with the composite semiconductor devices SW ₁₁ , SW ₁₂ , SW ₂₁ , SW ₂₂ , of the present invention.
If SW ₃₁ and SW ₃₂ are used, each composite semiconductor device SW ₁₁ ,
SW ₁₂ , SW ₂₁ , SW ₂₂ , SW ₃₁ , SW ₃₂ can be easily turned on / off by applying / removing a potential to the insulated gate electrode (G), and a known device of this type, for example, Unlike the GTO thyristor, there is no need to flow a large amount of current into or out of the gate electrode, and the gate circuit can be extremely simplified. In addition, each composite semiconductor device SW ₁₁ , SW ₁₂ , SW ₂₁ ,
SW ₂₂ , SW ₃₁ , and SW ₃₂ are built-in MISFE
Since the saturation characteristic of T (MTR1) is used, it is possible to give a current limiting action despite performing the thyristor operation, and to make a large current with a low ON voltage, and
It is possible to control at high speed without destroying the composite semiconductor device.

Therefore, in the inverter device for driving the electric motor,
Compared to the case of using a known device of this type, for example, a GTO thyristor, due to the achievement of high frequency and easy controllability,
It is possible to achieve small size, light weight, low loss, low noise, etc. of the inverter device, and also to achieve large capacity and low loss of the inverter device due to low on-voltage compared to the case of using an IGBT, for example. can do.

[0082]

As described above, according to the present invention, the IGB
The p2 + layer (p base layer) 6 in T and the p− layer (p base layer) 9 in the thyristor region are provided separately, and p−
By providing the notch 9a in the layer 9 (p base layer),
The n2 + layer (n emitter layer) 8 in the thyristor region is partially brought into contact with the n− layer (n base layer) 2 so that the thyristor current (electron) is one MISFET (MTR1) MIS.
Since it is made to flow only through the channel, it is possible to obtain a composite semiconductor device that can be easily ignited and can achieve a low on-voltage, thereby achieving a high breakdown voltage or a large current. The effect is that you can do it.

Further, according to the present invention, p2 in the IGBT is
The + layer (p base layer) 6 and the p layer (p base layer) 16 in the thyristor region are connected to the first and second MISFETs (MTRs).
1, the second MISFET (MTR2) adjacent to the thyristor region is formed as a depletion type so that the MIS current (electrons) and the thyristor current (electrons) are substantially separated from each other. Since it is equivalent to the one that flows through only the MIS channel of the MISFET (MTR1) of 1, the ignition is facilitated and the low on-voltage can be achieved, thereby increasing the withstand voltage or the large current. There is an effect that it is possible to obtain a composite semiconductor device capable of

That is, the composite semiconductor device according to the present invention is
Since the thyristor region is added to the IGBT in the best form, the cathode electrode (K) is changed to the MISFET.
The electrons supplied through the MIS channel of (MTR1) spread to the thyristor region and flow sufficiently,
There is an effect that the on-voltage can be made sufficiently low without impairing the firing characteristics.

[Brief description of drawings]

FIG. 1 is a schematic perspective sectional view and a schematic plan view showing the configuration of a first embodiment of a composite semiconductor device according to the present invention.

FIG. 2 is an A- in the first embodiment shown in FIG.
It is a schematic sectional drawing of an A and BB line portion. , C-C
It is a schematic sectional drawing of a line part.

FIG. 3 shows C- in the first embodiment shown in FIG.
It is a schematic sectional drawing of a C line part.

FIG. 4 is an equivalent circuit diagram of a first embodiment of the composite semiconductor device shown in FIG.

FIG. 5 is an on-state current flow diagram in the composite semiconductor device of the present invention and a known composite semiconductor device.

FIG. 6 is a schematic plan view showing a second configuration example in which the configuration and arrangement location of the cutout portion of the P− layer in the first embodiment are changed.

FIG. 7 is a schematic plan view showing a third configuration example in which the configuration and the location of the cutout portion of the P− layer in the first embodiment are changed.

FIG. 8 is a schematic plan view showing a fourth configuration example in which the configuration and the location of the notch portion of the P− layer in the first embodiment are changed.

9 is an A- in each configuration example shown in FIG. 6 to FIG.
It is a schematic sectional drawing of an A, BB, CC, DD, and EE line part.

FIG. 10 is a schematic sectional view showing the structure of a second embodiment of the composite semiconductor device according to the present invention.

11 is an equivalent circuit diagram of the second embodiment of the composite semiconductor device shown in FIG.

12 is a flow chart of carriers in the ON state of the composite semiconductor device shown in FIG. 10 and A-A and B-B thereof.
It is an operation explanatory view showing an impurity concentration distribution of a line portion.

FIG. 13 is a schematic perspective sectional view and a schematic plan view showing a configuration example in which the configuration of the cathode electrode (K) in the second embodiment is changed.

FIG. 14 is a schematic circuit diagram showing an example of the configuration of an inverter device for driving a motor using the composite semiconductor device according to the present invention.

FIG. 15 is a schematic cross-sectional view showing an example of the configuration of a known semiconductor device (IGBT).

16 is an equivalent circuit diagram of the known IGBT shown in FIG.

FIG. 17 is a schematic cross-sectional view showing an example of the configuration of a known composite semiconductor device (insulated gate electrode type thyristor).

18 is an equivalent circuit diagram of the known insulated gate electrode type thyristor shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor base body 1a One main surface of the semiconductor base body 1b The other main surface of the semiconductor base body 2 n-type low impurity concentration layer (n- layer, 1st semiconductor layer) 3 n-type impurity layer (n layer, 1st) Semiconductor layer) 4 first p-type high impurity layer (p1 + layer, second semiconductor layer) 5 p-type impurity layer (p layer, third semiconductor layer) 6 second p-type high impurity layer (p2 + layer) , Third semiconductor layer) 7 first n-type high impurity layer (n1 + layer, fourth semiconductor layer) 8 second n-type high impurity concentration layer (n2 + layer, fifth semiconductor layer) 9 p-type low Impurity concentration layer (p-layer, sixth semiconductor layer) 9a, 9b, 9c, 9d Notch portion 10 Insulated gate electrode (G) 12, 21 Insulating film 13 Anode electrode (A) 14 Cathode electrode (K) 15 Third N-type high impurity concentration layer (n3 + layer, sixth semiconductor layer) 16 p-type impurity layer (p layer, seventh layer) Conductor layer 17 Second p-type low impurity concentration layer (p2-layer, eighth semiconductor layer) 18 Fourth n-type impurity layer (n4 layer, ninth semiconductor layer) 19 First insulated gate electrode ( G1) 20 second insulated gate electrode (G2) TR1 first pnp transistor TR2 first npn transistor TR3 second pnp transistor TR4 second npn transistor MTR1 first n-channel MISFET MTR2 second n-channel MISFET Lateral resistance in r ₁ p 2+ layer 6 R n− internal resistance of layer 2

Claims (13)

[Claims] 1. A semiconductor substrate having a pair of main surfaces, the first semiconductor layer of a first conductivity type having a low impurity concentration, and a high-concentration layer disposed adjacent to the first semiconductor layer on one main surface. A plurality of second conductivity type second semiconductor layers having an impurity concentration and a plurality of semiconductor elements provided in the first semiconductor layer on the other main surface are provided parallel to one side of the semiconductor substrate and separated from each other. A band-shaped third semiconductor layer of high impurity concentration second conductivity type, and a first impurity type first semiconductor type of high impurity concentration provided in each of the plurality of third semiconductor layers along the longitudinal direction thereof. No. 4 semiconductor layer, and the high impurity concentration provided in the first semiconductor layer on the other main surface so that both side edge portions respectively contact opposite side edge portions in the two third semiconductor layers. A first conductive type fifth semiconductor layer, the first semiconductor layer, and A sixth low-impurity-concentration second conductivity type semiconductor device having at least one notch provided between the fifth semiconductor layer and in direct contact with the first semiconductor layer and the fifth semiconductor layer. A semiconductor substrate composed of a semiconductor layer, a first main electrode arranged in low resistance contact with the second semiconductor layer on the one main surface, the third semiconductor layer on the other main surface, and A second main electrode arranged in a low resistance contact state on each of the fourth semiconductor layers and the exposed first main electrode between the fourth semiconductor layer and the fifth semiconductor layer on the other main surface. 3. The composite semiconductor device according to claim 3, further comprising: a control electrode disposed on the semiconductor layer of FIG. 2. The first semiconductor layer is adjacent to the first semiconductor layer portion and the second semiconductor layer, and the second semiconductor layer portion has a higher impurity concentration than the first semiconductor layer portion. And the third semiconductor layer includes a third semiconductor layer portion adjacent to each of the first semiconductor layer portion and the fifth semiconductor layer, and the second semiconductor layer at a position apart from the control electrode. The composite semiconductor device according to claim 1, wherein the composite semiconductor device comprises a fourth semiconductor layer portion that is in contact with the main electrode and has a higher impurity concentration than the third semiconductor layer portion. 3. The notches in the sixth semiconductor layer are band-shaped and extend in a direction orthogonal to one side of the semiconductor substrate, and are regularly provided along one side of the semiconductor substrate. 3. The composite semiconductor device according to claim 1, wherein the composite semiconductor device is a semiconductor device. 4. The composite semiconductor device according to claim 3, wherein each of the band-shaped notches is provided over the entire width of the sixth semiconductor layer. 5. The composite semiconductor device according to claim 3, wherein each of the band-shaped notches is provided in a part of the sixth semiconductor layer in the width direction. 6. The notch in the sixth semiconductor layer is formed in a strip shape extending in parallel to one side of the semiconductor substrate, and is provided at a substantially central portion in the width direction of the sixth semiconductor layer. 3. The composite semiconductor device according to claim 1, wherein the composite semiconductor device is a semiconductor device. 7. The cutout portion of the sixth semiconductor layer is formed in a substantially circular shape, and is regularly provided along one side of the semiconductor substrate. 7. The composite semiconductor device according to any one. 8. The semiconductor substrate is formed and arranged so that an IGBT region and a thyristor region are adjacent to each other to form a composite semiconductor device, and the IGBT region is provided on a pair of main surfaces. The cathode side end region of the thyristor region is directly connected to the main electrode, is connected to the second main electrode via the MISFET region existing in the IGBT region, and the anode side end region is the first side. The composite semiconductor device according to claim 1, wherein the composite semiconductor device is directly connected to the main electrode. 9. A semiconductor substrate having a pair of main surfaces, a first semiconductor layer of a first conductivity type having a low impurity concentration, and a high-level semiconductor layer disposed adjacent to the first semiconductor layer on one main surface. A second semiconductor layer of a second conductivity type having an impurity concentration and a strip-shaped second conductivity type of a high impurity concentration provided parallel to one side of the semiconductor substrate in the first semiconductor layer on the other main surface. A third semiconductor layer, a fourth semiconductor layer of the first conductivity type having a high impurity concentration and provided in the third semiconductor layer along its longitudinal direction, and the first semiconductor layer on the other main surface. The first high impurity concentration first semiconductor layer is provided in the semiconductor layer so that one side edge portion is in contact with the side edge portion of the third semiconductor layer.
A fifth semiconductor layer of a conductivity type and a sixth semiconductor layer of a first conductivity type having a high impurity concentration, which is arranged in parallel and spaced apart from the fifth semiconductor layer in the first semiconductor layer on the other main surface. Between the first semiconductor layer and the sixth semiconductor layer, one side edge portion of which is in contact with the side edge portion of the fifth semiconductor layer. Type seventh semiconductor layer and an eighth surface of the second conductivity type having a low impurity concentration, which is provided on the inner surface of the third semiconductor layer between the fourth semiconductor layer and the fifth semiconductor layer. A semiconductor layer and a ninth semiconductor layer of the first conductivity type, which is provided on the inner surface of the seventh semiconductor layer between the fifth semiconductor layer and the sixth semiconductor layer and has a high impurity concentration. A semiconductor substrate and a first main electrode arranged in low resistance contact with the second semiconductor layer on the one main surface. A second main electrode arranged in a low resistance contact state with each of the third semiconductor layer and the fourth semiconductor layer on the other main surface, and the fourth semiconductor on the other main surface. Between the fifth control layer and the sixth control layer, and the first control electrode opposed to the eighth control layer exposed between the fifth control layer and the fifth control layer. A composite semiconductor device, comprising: a second control electrode disposed so as to face and insulate the exposed ninth semiconductor layer. 10. A portion comprising the fifth semiconductor layer, the sixth semiconductor layer, the seventh semiconductor layer, the ninth semiconductor layer and the second control electrode is a depletion type first. 10. The composite semiconductor device according to claim 9, wherein the MISFET of No. 2 is configured. 11. A composite semiconductor device is formed by arranging the semiconductor substrate such that an IGBT region and a thyristor region are adjacent to each other, and the IGBT region includes the first and second semiconductor regions.
Of the thyristor region, the cathode side end region of which is present in the IGBT region.
FET region and the depletion type second MISF
10. The composite semiconductor device according to claim 9, wherein the composite semiconductor device is connected to the second main electrode via an ET region, and the end region on the anode side is directly connected to the first main electrode. 12. An inverter device having a pair of DC voltage input terminals, an AC voltage output terminal having the same number as the AC output phase, and an inverter unit having the same number as the AC output phase for converting the DC voltage into the AC voltage. 9. Each of the inverter units has a configuration in which two parallel connection circuits of a switching element and a reverse polarity connection diode are connected in series between the pair of DC voltage input terminals, and the switching element has a configuration in which: A power conversion device comprising the composite semiconductor device according to any one of 1. 13. An inverter device having a pair of DC voltage input terminals, an AC voltage output terminal having the same number as the AC output phase, and an inverter unit having the same number as the AC output phase for converting the DC voltage into the AC voltage. 12. Each of the inverter units has a configuration in which two parallel connection circuits of a switching element and a reverse polarity connection diode are connected in series between the pair of DC voltage input terminals, and the switching element has a configuration in which: A power conversion device comprising the composite semiconductor device according to any one of 1.