JPH07161875A - Semiconductor device sealed with resin - Google Patents

Semiconductor device sealed with resin

Info

Publication number
JPH07161875A
JPH07161875A JP5308944A JP30894493A JPH07161875A JP H07161875 A JPH07161875 A JP H07161875A JP 5308944 A JP5308944 A JP 5308944A JP 30894493 A JP30894493 A JP 30894493A JP H07161875 A JPH07161875 A JP H07161875A
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
lead
package
cut
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5308944A
Other languages
Japanese (ja)
Inventor
Tatsumi Sakazume
太津美 坂詰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5308944A priority Critical patent/JPH07161875A/en
Publication of JPH07161875A publication Critical patent/JPH07161875A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the occurrence of the voids of a package, and reduce the impedance of an inner lead, and reduce the short circuit by the foreign matter in the manufacture process, in a semiconductor device sealed with resin. CONSTITUTION:In a semiconductor device sealed with resin, in which a semiconductor pellet 2 is mounted on a tab 4 and the semiconductor pellet 2 and leads 5 are electrically connected with each other, the shape of the package 7, when viewed from above, of a semiconductor device sealed with resin is quadrilateral, and a pair of corners in opposition are cut off on a level that voids do not occur at sealing with resin. Moreover, leads are provided at the section where the corner is cut off.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】樹脂封止型半導体装置の製造方法
に関し、特にボイド(気泡)発生による不良を低減する
必要のある樹脂封止型半導体装置に適用して有効な技術
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a resin-encapsulated semiconductor device, and more particularly to a technique effectively applied to a resin-encapsulated semiconductor device that needs to reduce defects due to voids (air bubbles).

【0002】[0002]

【従来の技術】QFP(Quad Flat Package)構造や
QFJ(Quad Flat J-leaded Package)構造等を採
用する半導体装置は、半導体ペレットを封止するパッケ
ージの平面形状が四辺形で、該パッケージの四辺の夫々
から複数本のアウターリードが出ている。該アウターリ
ードは、インナーリードと一体に構成され、該インナー
リードの一端は、半導体ペレットの外部端子に電気的に
接続されている。
2. Description of the Related Art A semiconductor device adopting a QFP (Quad Flat Package) structure, a QFJ (Quad Flat J-leaded Package) structure, or the like is a quadrilateral plane shape of a package for encapsulating a semiconductor pellet. There are multiple outer leads from each. The outer lead is formed integrally with the inner lead, and one end of the inner lead is electrically connected to the external terminal of the semiconductor pellet.

【0003】前記半導体装置は、前記パッケージの材質
がセラミック製のセラミック封止型半導体装置、所謂C
LCC(Ceramic Leaded Chip Carrier)と、前記
パッケージの材質が樹脂製の樹脂封止型半導体装置、所
謂PLCC(Plastic Leaded Chip Carrier)とが
ある。
The semiconductor device is a ceramic-sealed semiconductor device in which the package material is ceramic, so-called C.
There are an LCC (Ceramic Leaded Chip Carrier) and a so-called PLCC (Plastic Leaded Chip Carrier) in which the package material is a resin.

【0004】前記樹脂封止型半導体装置は、トランスフ
ァモールド法で樹脂封止される。該トランスファモール
ド法を実施するモールド装置は、半導体ペレットを搭載
したリードフレームを挾み込む金型、樹脂タブレットを
加熱溶融させるヒータ、溶融した樹脂を加圧するプラン
ジャ等で構成されている。
The resin-sealed semiconductor device is resin-sealed by a transfer molding method. A molding apparatus for carrying out the transfer molding method is composed of a die for sandwiching a lead frame on which semiconductor pellets are mounted, a heater for heating and melting a resin tablet, a plunger for pressing the melted resin, and the like.

【0005】前記上金型および下金型は、樹脂封止時に
パッケージの成形を行い、前記樹脂タブレットが投入さ
れるポットと、該ポットからつながり溶融した樹脂が移
送されるランナと、ランナにつながるキャビティとが設
けられている。
The upper die and the lower die form a package during resin encapsulation, and connect to a pot into which the resin tablet is put, a runner to which molten resin is transferred from the pot and a runner. A cavity is provided.

【0006】樹脂封止の手順は、まず、半導体ペレット
が搭載されたリードフレームを前記上下金型のキャビテ
ィ部分に挾み込み、予備加熱した樹脂タブレットを金型
のポットに投入し、前記樹脂タブレットを前記ヒータで
加熱溶融させ、プランジャで圧入する。圧入された樹脂
は、ポットからランナに移送され、キャビティに流入さ
れる。そして、樹脂が硬化した後、樹脂とリードフレー
ムの所定の箇所を切断する。
The resin encapsulation procedure is as follows. First, the lead frame on which the semiconductor pellets are mounted is sandwiched in the cavity parts of the upper and lower molds, and a preheated resin tablet is put into the mold pot, and the resin tablet is Is melted by heating with the heater and press-fitted with a plunger. The resin that has been press-fitted is transferred from the pot to the runner and flowed into the cavity. Then, after the resin is cured, the resin and a predetermined portion of the lead frame are cut.

【0007】前記QFPやQFJ等のパッケージを成形
する金型は、キャビティ部分の平面形状が正方形で対向
する一対の角部にランナが接続されており、樹脂封止の
際、樹脂を、一方のランナからを流入し、他方のランナ
から吐出している。
In a mold for molding a package such as QFP or QFJ, a runner is connected to a pair of opposite corners of a cavity having a square planar shape. Inflow from the runner and discharge from the other runner.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、本発明
者はパッケージの角部から樹脂を流入し、樹脂封止を行
う樹脂封止型半導体装置について検討した結果、以下の
問題点を見出した。
However, the present inventor has found the following problems as a result of studying a resin-encapsulated semiconductor device in which resin is injected from the corners of the package to perform resin encapsulation.

【0009】図5に示すように、樹脂封止型半導体装置
の樹脂封止は、パッケージの角部Aから樹脂が流入し、
この角部Aと対向する角部Bから余分な樹脂を吐出して
いたので、流入される樹脂は、前記角部Aと角部Bを結
ぶ対角線上に主な流れをつくる。このため、該対角線上
の流れの側方にあたる角部には、樹脂の充填に時間がか
かり、前記パッケージの寸法が、例えば一辺の長さが2
8mm、40mmと大型のものになると、該樹脂の流れ
の側方にあたる角部にボイド15(気泡)が発生すると
いう問題があった。
As shown in FIG. 5, in resin encapsulation of a resin-encapsulated semiconductor device, resin flows in from a corner A of the package,
Since the excess resin was discharged from the corner B facing the corner A, the inflowing resin makes a main flow on the diagonal line connecting the corners A and B. For this reason, it takes time to fill the resin into the corners on the sides of the diagonal flow, and the size of the package is, for example, one side is 2
When the size is as large as 8 mm or 40 mm, there is a problem that voids 15 (air bubbles) are generated at the corners that are lateral to the flow of the resin.

【0010】また、樹脂封止型半導体装置は、そのパッ
ケージの四辺の夫々からアウターリードがでており、パ
ッケージの角部付近のアウターリードにつながるインナ
ーリードの長さが長く、インナーリードにおけるインピ
ーダンスが大きくなるという問題があった。
Further, in the resin-sealed semiconductor device, outer leads are formed on each of the four sides of the package, the length of the inner leads connected to the outer leads near the corners of the package is long, and the impedance in the inner leads is high. There was a problem of getting bigger.

【0011】本発明の目的は、樹脂封止型半導体装置の
パッケージのボイドの発生を低減できる技術を提供する
ことにある。
An object of the present invention is to provide a technique capable of reducing the occurrence of voids in the package of the resin-sealed semiconductor device.

【0012】本発明の他の目的は、樹脂封止型半導体装
置のインナーリードにおけるインピーダンスを低減でき
る技術を提供することにある。
Another object of the present invention is to provide a technique capable of reducing the impedance in the inner leads of a resin-sealed semiconductor device.

【0013】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0014】[0014]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。
Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

【0015】(1)タブの上に半導体ペレットを装着
し、該半導体ペレットとリードを電気的に接続し、樹脂
で封止した樹脂封止型半導体装置において、前記樹脂封
止型半導体装置のパッケージの平面形状が四辺形状であ
って、対向する一対の角部を樹脂封止時にボイドが発生
しない程度に切り取る。
(1) A resin-sealed semiconductor device in which a semiconductor pellet is mounted on a tab, the semiconductor pellet and the lead are electrically connected, and the resin-sealed semiconductor device is sealed with a resin. Has a quadrilateral planar shape, and a pair of opposing corner portions are cut out to the extent that voids do not occur during resin sealing.

【0016】(2)手段(1)記載の樹脂封止型半導体
装置であって、前記角部を切り取った部分にリードを設
ける。
(2) In the resin-sealed semiconductor device according to the means (1), a lead is provided at a portion where the corner is cut off.

【0017】[0017]

【作用】上述した手段(1)によれば、パッケージの対
向する2つの角部を樹脂封止時にボイド(気泡)が発生
しない程度に切り取る。つまり、前記金型のキャビティ
部において、ランナの接続されない2つの角を落してい
るので、樹脂封止の際、樹脂の流れが円滑になり、ボイ
ドの発生が低減できる。
According to the above-mentioned means (1), the two opposite corners of the package are cut out to the extent that voids (air bubbles) are not generated during resin sealing. In other words, in the cavity of the mold, the two corners to which the runner is not connected are dropped, so that the resin flow becomes smooth during resin sealing, and the occurrence of voids can be reduced.

【0018】手段(2)によれば、手段(1)で角部を
切り取った部分にリードを設けるので、リード本数の減
少を低減できる。
According to the means (2), since the leads are provided at the portions whose corners are cut off by the means (1), the reduction in the number of leads can be suppressed.

【0019】また、角部を切り取った部分にリードを設
けるので、その部分に配置されるインナーリードの長さ
は、従来より短くなり、インナーリード部分のインダク
タンスが低減できる。
Further, since the lead is provided in the portion where the corner is cut off, the length of the inner lead arranged in that portion is shorter than in the conventional case, and the inductance of the inner lead portion can be reduced.

【0020】また、角部を切り取った部分に設けたリー
ドは、インナーリードの長さが従来より短くなるので、
製造工程途中の異物による短絡が低減できる。
In addition, since the length of the inner lead of the lead provided in the part where the corner is cut is shorter than that of the conventional one,
Short circuits due to foreign matter during the manufacturing process can be reduced.

【0021】以下、本発明の構成について、QFP構造
を採用する樹脂封止型半導体装置に本発明を適用した一
実施例とともに説明する。
The structure of the present invention will be described below together with an embodiment in which the present invention is applied to a resin-sealed semiconductor device adopting a QFP structure.

【0022】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、繰り返し
の説明は省略する。
In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and repeated description will be omitted.

【0023】[0023]

【実施例】図1は、QFP構造を採用する樹脂封止型半
導体装置に適用した一実施例を示す斜視図である。
FIG. 1 is a perspective view showing an embodiment applied to a resin-sealed semiconductor device adopting a QFP structure.

【0024】図2は、図1の樹脂封止型半導体装置をC
−C線で切った断面図である。
FIG. 2 shows the resin-sealed semiconductor device of FIG.
It is sectional drawing cut | disconnected by the C line.

【0025】図3は、図1の樹脂封止型半導体装置のリ
ードフレームの構成を示す平面図である。
FIG. 3 is a plan view showing the structure of the lead frame of the resin-sealed semiconductor device of FIG.

【0026】図4は、図1の樹脂封止型半導体装置を樹
脂封止する金型のキャビティ部分の平面図である。
FIG. 4 is a plan view of a cavity portion of a mold for resin-sealing the resin-sealed semiconductor device of FIG.

【0027】図1及び図2に示すように、本実施例の樹
脂封止型半導体装置1は、タブ4の表面上に搭載された
半導体ペレット2の素子形成面に配置される外部端子、
インナーリード5の夫々が電気的に接続され、これらが
パッケージ7で封止される。該パッケージ7は、平面形
状が四辺形状(正方形状)の対向する一対の角部が切り
落された形状となっている。つまり、4つの長辺Lと、
2つの短辺Sとからなる平面形状となり、QFP構造を
採用する樹脂封止型半導体装置の変形である。例えば、
短辺Sの長さは、長辺Lの長さの20%となっている。
As shown in FIGS. 1 and 2, the resin-encapsulated semiconductor device 1 of this embodiment has an external terminal arranged on the element forming surface of the semiconductor pellet 2 mounted on the surface of the tab 4.
The inner leads 5 are electrically connected to each other, and these are sealed with the package 7. The package 7 has a quadrilateral (square) planar shape with a pair of opposing corners cut off. That is, four long sides L and
This is a modification of the resin-encapsulated semiconductor device that has a planar shape composed of two short sides S and adopts a QFP structure. For example,
The length of the short side S is 20% of the length of the long side L.

【0028】前記インナーリード5は、アウターリード
6に機械的かつ電気的に接続され、アウターリード6
は、パッケージの外周(長辺及び短辺の夫々)に配置さ
れる。つまり、四辺形状の対向する一対の角部を切り落
した部分にもアウターリード6が配置されている。
The inner lead 5 is mechanically and electrically connected to the outer lead 6, and the outer lead 6
Are arranged on the outer circumference (each of the long side and the short side) of the package. That is, the outer leads 6 are also arranged at the portions where the pair of opposite corners of the quadrilateral are cut off.

【0029】前記半導体ペレット2は、平面形状が四辺
形状(正方形状)で形成され、単結晶珪素基板を主体に
構成される。この半導体ペレット2の素子形成面には、
所定の回路システムが搭載され、半導体ペレット2の外
部端子は、回路システムが搭載された素子形成面に複数
個配置される。
The semiconductor pellet 2 is formed in a quadrilateral shape (square shape) in a plan view, and is mainly composed of a single crystal silicon substrate. On the element forming surface of the semiconductor pellet 2,
A predetermined circuit system is mounted, and a plurality of external terminals of the semiconductor pellet 2 are arranged on the element formation surface on which the circuit system is mounted.

【0030】前記半導体ペレット2は、タブ4の表面上
に接着層8を介在して固着される。接着層は、例えばA
u−Si共晶合金、Agペースト等が使用される。
The semiconductor pellet 2 is fixed on the surface of the tab 4 with an adhesive layer 8 interposed. The adhesive layer is, for example, A
u-Si eutectic alloy, Ag paste, etc. are used.

【0031】前記半導体ペレット2の外部端子とインナ
ーリード5とはワイヤ9を通して電気的に接続される。
ワイヤ9は、例えばAuワイヤが使用され、熱圧着に超
音波振動を併用したボンディング法でボンディングされ
る。
The external terminal of the semiconductor pellet 2 and the inner lead 5 are electrically connected through a wire 9.
As the wire 9, for example, an Au wire is used, and the wire 9 is bonded by a bonding method using ultrasonic vibration in combination with thermocompression bonding.

【0032】前記タブ、インナーリード5及びアウター
リード6は、リードフレーム3として、一体に成型され
る。リードフレーム3は、Fe−Ni合金(例えばNi
含有量が、42または50%)で形成される。また、こ
れらはCu若しくはCu系合金で形成してもよい。
The tab, the inner lead 5 and the outer lead 6 are integrally molded as a lead frame 3. The lead frame 3 is made of a Fe-Ni alloy (for example, Ni.
Content of 42 or 50%). Also, these may be formed of Cu or a Cu-based alloy.

【0033】図3に示すように、リードフレーム3は、
半導体ペレット2が搭載されるタブ4が中央に設けら
れ、このタブ4は、タブ吊りリード10でリードフレー
ム3の外枠12と接続され支持されている。
As shown in FIG. 3, the lead frame 3 is
A tab 4 on which the semiconductor pellet 2 is mounted is provided in the center, and the tab 4 is connected to and supported by the outer frame 12 of the lead frame 3 by a tab suspension lead 10.

【0034】前記タブ4の周りには、複数本のインナー
リード5がタブ4を囲んで設けられている。このインナ
ーリード5の一端には、アウターリード6が設けられ、
インナーリード5とアウターリード6との間には、樹脂
封止時に樹脂を堰き止める目的で、ダムバー11が設け
られている。
A plurality of inner leads 5 are provided around the tab 4 so as to surround the tab 4. An outer lead 6 is provided at one end of the inner lead 5,
A dam bar 11 is provided between the inner lead 5 and the outer lead 6 for the purpose of blocking the resin during resin sealing.

【0035】前記パッケージ7は、トランスファモール
ド法で成型する。このトランスファモールド法を実施す
るモールド装置は、半導体ペレット2を搭載したリード
フレーム3を挾み込む上金型及び下金型、樹脂タブレッ
トを加熱溶融させるヒータ、溶融した樹脂を加圧するプ
ランジャ等で構成され、前記上金型および下金型は、樹
脂封止時にパッケージ7の成形を行い、前記樹脂タブレ
ットが投入されるポットと、該ポットからつながり溶融
した樹脂が移送されるランナ13と、ランナ13につな
がるキャビティ12とが設けられている。
The package 7 is molded by the transfer molding method. A molding apparatus for carrying out this transfer molding method is composed of an upper mold and a lower mold for sandwiching a lead frame 3 carrying the semiconductor pellets 2, a heater for heating and melting a resin tablet, a plunger for pressurizing the molten resin, and the like. The upper mold and the lower mold mold the package 7 at the time of resin sealing, the pot into which the resin tablet is put, the runner 13 to which the molten resin is transferred from the pot and the runner 13 are connected. And a cavity 12 connected to the.

【0036】図4に示すように、前記樹脂封止型半導体
装置を樹脂封止する金型の平面形状は、樹脂を流入する
ランナ13aがキャビティ14の角部A’に接続され、
余分な樹脂を吐出するランナ13bが、角部A’と対向
する角部B’に接続されている。
As shown in FIG. 4, the planar shape of the mold for resin-sealing the resin-sealed semiconductor device is such that the runner 13a through which the resin flows is connected to the corner A'of the cavity 14,
A runner 13b that discharges excess resin is connected to a corner portion B'opposing the corner portion A '.

【0037】樹脂封止の手順は、まず、半導体ペレット
2が搭載されたリードフレーム3を前記上金型、下金型
で挾み込み、予備加熱した樹脂タブレットを金型のポッ
トに投入し、前記樹脂タブレットを前記ヒータで180
℃程度に加熱溶融させ、プランジャで100〜150k
g/cm2の圧力を加え、樹脂を圧入する。
The resin encapsulation procedure is as follows. First, the lead frame 3 on which the semiconductor pellets 2 are mounted is sandwiched by the upper die and the lower die, and a preheated resin tablet is put into the pot of the die, 180 the resin tablet with the heater
It is heated and melted at about ℃, and 100 ~ 150k with a plunger.
A resin is pressed in by applying a pressure of g / cm 2 .

【0038】圧入された樹脂は、ポットからランナ13
aを移送され、角部A’からキャビティ14に流入し、
余分な樹脂が、角部B’からランナ13bに吐出され
る。
The resin press-fitted from the pot is runner 13
a is transferred and flows into the cavity 14 from the corner A ′,
Excess resin is discharged from the corner B'to the runner 13b.

【0039】パッケージ7は、例えばフェノール硬化型
エポキシ系樹脂が使用される。このフェノール硬化型エ
ポキシ系樹脂は、通常フィラー(酸化珪素粒)、可撓材
(例えばシリコーンゴム)等が添加され、紫外線の吸
収、静電気の防止などを目的としてカーボン粒も併せて
添加される。
For the package 7, for example, phenol-curable epoxy resin is used. A filler (silicon oxide particles), a flexible material (for example, silicone rubber), etc. are usually added to the phenol-curable epoxy resin, and carbon particles are also added for the purpose of absorbing ultraviolet rays and preventing static electricity.

【0040】そして、樹脂が硬化した後、樹脂とリード
フレーム3のダムバー11及びアウターリード6と外枠
12の接続部分を切断し、アウターリード6を折り曲
げ、樹脂封止を完了する。
After the resin is hardened, the connection between the resin and the dam bar 11 of the lead frame 3 and the connecting portion of the outer lead 6 and the outer frame 12 is cut, the outer lead 6 is bent, and the resin sealing is completed.

【0041】以上の説明したように、本実施例の樹脂封
止型半導体装置によれば、パッケージ7の対向する2つ
の角部を樹脂封止時にボイド(気泡)が発生しない程度
に切り取っている。つまり、樹脂封止時に、樹脂が流入
される角部Aと余分な樹脂が吐出される角部Bとを結ぶ
対角線の側方の角部を落しているので、樹脂封止の際、
樹脂の流れが円滑になり、ボイド(気泡)の発生が低減
できる。
As described above, according to the resin-sealed semiconductor device of this embodiment, the two opposite corners of the package 7 are cut to the extent that voids (air bubbles) are not generated during resin sealing. . That is, at the time of resin sealing, the corners on the sides of the diagonal connecting the corner A into which the resin flows and the corner B from which the excess resin is discharged are dropped.
The flow of resin becomes smooth and the generation of voids (air bubbles) can be reduced.

【0042】また、角部を切り取った部分(短辺S)に
アウターリード6を設けているので、角部を切り取った
ことによるリード本数の減少を低減できる。
Further, since the outer leads 6 are provided at the portions where the corners are cut off (short sides S), the reduction in the number of leads due to the cutting off of the corners can be suppressed.

【0043】また、短辺Sにリードを設けるので、短辺
Sに配置されるインナーリード5の長さは、従来の角部
付近に配置されたインナーリードより短くなり、インナ
ーリード5部分のインダクタンスが低減できる。
Further, since the lead is provided on the short side S, the length of the inner lead 5 arranged on the short side S is shorter than that of the conventional inner lead arranged near the corner, and the inductance of the inner lead 5 portion is reduced. Can be reduced.

【0044】また、短辺Sに配置したインナーリード5
が短くなるので、製造工程途中の異物による短絡も低減
できる。
Also, the inner lead 5 arranged on the short side S
As a result, the short circuit due to foreign matter during the manufacturing process can be reduced.

【0045】以上発明者によってなされた発明を実施例
にもとづき具体的に説明したが、本発明は上記実施例に
限定されるものではなく、その要旨を逸脱しない範囲で
種々変更可能であることはいうまでもない。
Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

【0046】例えば、前記短辺Sの長さは、長辺Lの長
さの20%に限定されるものではなく、樹脂封止時にボ
イドが発生しない程度であればよく、短辺Sをより長く
することで、インナーリードが短くできるので、更にイ
ンダクタンスを低減でき、異物による短絡も防止でき
る。
For example, the length of the short side S is not limited to 20% of the length of the long side L, as long as voids do not occur during resin encapsulation. By making the length longer, the inner lead can be shortened, so that the inductance can be further reduced and a short circuit due to foreign matter can be prevented.

【0047】[0047]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。
The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

【0048】1.パッケージのボイドの発生が低減でき
る。
1. Occurrence of package voids can be reduced.

【0049】2.インナーリードにおけるインピーダン
スが低減できる。
2. The impedance in the inner leads can be reduced.

【0050】3.製造工程途中の異物による短絡が低減
できる。
3. Short circuits due to foreign matter during the manufacturing process can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】QFP構造を採用する樹脂封止型半導体装置に
適用した一実施例を示す斜視図、
FIG. 1 is a perspective view showing an embodiment applied to a resin-sealed semiconductor device adopting a QFP structure,

【図2】図1の樹脂封止型半導体装置をC−C線で切っ
た断面図、
2 is a cross-sectional view of the resin-encapsulated semiconductor device of FIG. 1 taken along line C-C,

【図3】図1の樹脂封止型半導体装置のリードフレーム
の構成を示す平面図、
3 is a plan view showing the configuration of a lead frame of the resin-encapsulated semiconductor device of FIG.

【図4】図1の樹脂封止型半導体装置を樹脂封止する金
型のキャビティ部分の平面図、
4 is a plan view of a cavity portion of a mold for resin-sealing the resin-sealed semiconductor device of FIG.

【図5】従来のQFP構造を採用する樹脂封止型半導体
装置を示す斜視図。
FIG. 5 is a perspective view showing a resin-sealed semiconductor device adopting a conventional QFP structure.

【符号の説明】[Explanation of symbols]

1…樹脂封止型半導体装置、2…半導体ペレット、3…
リードフレーム、4…タブ、5…インナーリード、6…
アウターリード、7…パッケージ、8…接着層、9…ワ
イヤ、10…タブ吊りリード、11…ダムバー、12…
外枠、13a、13b…ランナ、14…キャビティ、1
5…ボイド、A、B…角部、L…長辺、S…短辺。
1 ... Resin-encapsulated semiconductor device, 2 ... Semiconductor pellet, 3 ...
Lead frame, 4 ... Tab, 5 ... Inner lead, 6 ...
Outer lead, 7 ... Package, 8 ... Adhesive layer, 9 ... Wire, 10 ... Tab suspension lead, 11 ... Dam bar, 12 ...
Outer frames, 13a, 13b ... Runners, 14 ... Cavities, 1
5 ... Void, A, B ... Corner, L ... Long side, S ... Short side.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 タブの上に半導体ペレットを装着し、該
半導体ペレットとリードを電気的に接続し、樹脂で封止
した樹脂封止型半導体装置において、前記樹脂封止型半
導体装置のパッケージの平面形状が四辺形状であって、
対向する一対の角部を樹脂封止時にボイドが発生しない
程度に切り取ったことを特徴とする樹脂封止型半導体装
置。
1. A resin-sealed semiconductor device in which a semiconductor pellet is mounted on a tab, the semiconductor pellet and the lead are electrically connected, and the resin-sealed semiconductor device is sealed with a resin. The planar shape is a quadrilateral,
A resin-encapsulated semiconductor device, characterized in that a pair of opposite corners are cut to such an extent that no void is generated during resin encapsulation.
【請求項2】 前記請求項1記載の樹脂封止型半導体装
置であって、前記角部を切り取った部分にリードを設け
たことを特徴とする樹脂封止型半導体装置。
2. The resin-encapsulated semiconductor device according to claim 1, wherein a lead is provided in a portion where the corner is cut off.
JP5308944A 1993-12-09 1993-12-09 Semiconductor device sealed with resin Pending JPH07161875A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5308944A JPH07161875A (en) 1993-12-09 1993-12-09 Semiconductor device sealed with resin

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5308944A JPH07161875A (en) 1993-12-09 1993-12-09 Semiconductor device sealed with resin

Publications (1)

Publication Number Publication Date
JPH07161875A true JPH07161875A (en) 1995-06-23

Family

ID=17987141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5308944A Pending JPH07161875A (en) 1993-12-09 1993-12-09 Semiconductor device sealed with resin

Country Status (1)

Country Link
JP (1) JPH07161875A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6787891B2 (en) 2000-12-06 2004-09-07 Medtronic, Inc. Freeform substrates and devices
WO2016181516A1 (en) * 2015-05-13 2016-11-17 三菱電機株式会社 Semiconductor module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6787891B2 (en) 2000-12-06 2004-09-07 Medtronic, Inc. Freeform substrates and devices
US7335530B2 (en) 2000-12-06 2008-02-26 Medtronic, Inc. Freeform substrates and devices
WO2016181516A1 (en) * 2015-05-13 2016-11-17 三菱電機株式会社 Semiconductor module
CN107615478A (en) * 2015-05-13 2018-01-19 三菱电机株式会社 Semiconductor module
US10217683B2 (en) 2015-05-13 2019-02-26 Mitsubishi Electric Corporation Mounted semiconductor module with a mold resin portion

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