JPH07161871A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPH07161871A JPH07161871A JP31018193A JP31018193A JPH07161871A JP H07161871 A JPH07161871 A JP H07161871A JP 31018193 A JP31018193 A JP 31018193A JP 31018193 A JP31018193 A JP 31018193A JP H07161871 A JPH07161871 A JP H07161871A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- aln
- altin
- substrate
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、基板材料として窒化ア
ルミニウム(AlN)を用いた回路基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board using aluminum nitride (AlN) as a board material.
【0002】[0002]
【従来の技術】近年、コンピュ−タ−や通信機器の重要
部分には、多数のトランジスタや抵抗等を電気回路を達
成するようにむすびつけ、1チップ上に集積化して形成
した大規模集積回路(LSI)が多用されている。この
ため、機器全体の性能は、LSI単体の性能と大きく結
び付いている。2. Description of the Related Art In recent years, a large-scale integrated circuit formed by integrating a large number of transistors, resistors, etc., on one chip in an important part of a computer or communication equipment so as to achieve an electric circuit ( LSI) is frequently used. Therefore, the performance of the entire device is largely linked to the performance of the LSI alone.
【0003】LSI単体の性能向上は、集積度を高める
こと、つまり、素子の微細化により実現できる。このよ
うな微細化により最近のコンピュータシステムにおいて
はクロック周波数100MHz、チップ当たりの消費電
力30W以上の素子が使用されつつある。The performance improvement of the LSI itself can be realized by increasing the degree of integration, that is, by miniaturizing the elements. Due to such miniaturization, in recent computer systems, elements having a clock frequency of 100 MHz and a power consumption of 30 W or more per chip are being used.
【0004】このような素子を実装する基板には、高い
信号伝搬速度と良好な放熱性とが必要とされ、両特性を
向上することは素子特性をシステム特性に反映させるた
めに不可欠なことである。A substrate on which such an element is mounted is required to have a high signal propagation speed and good heat dissipation, and improving both characteristics is indispensable for reflecting the element characteristics on the system characteristics. is there.
【0005】このうち、放熱性に注目すると、基板材料
の候補としては、AlN、BN、ダイヤモンド、ダイヤ
モンドライクカーボン、BeOなどがあるが、製造方法
の容易性、環境におよぼす影響、放熱特性などを考慮す
ると、AlNの使用が望ましい。Of these, when attention is paid to heat dissipation, there are AlN, BN, diamond, diamond-like carbon, BeO, etc. as candidates for the substrate material. However, the ease of the manufacturing method, the influence on the environment, the heat dissipation characteristics, etc. Considering this, use of AlN is preferable.
【0006】ところで、回路基板の製造方法は、同時焼
成法による多層配線基板が一般的であるが、近年の高密
度化の要求から、基板表面に薄膜回路を形成する必要が
生じている。By the way, as a method of manufacturing a circuit board, a multi-layer wiring board by a co-firing method is generally used, but it is necessary to form a thin film circuit on the surface of the board due to the recent demand for higher density.
【0007】薄膜回路の配線材料としては、TiN/N
i/Au、Ti/Pt/Au、Ti/Cu、Cr/C
u、Ti/Alなどの多層金属膜が使用されている。こ
れらの配線材料は、入出力用ピン、リード、シール用リ
ットなどの金属部品をはんだ付けやろう接熱処理により
接合するメタライズ層としても使用されている。TiN / N is used as a wiring material for thin film circuits.
i / Au, Ti / Pt / Au, Ti / Cu, Cr / C
Multi-layer metal films such as u and Ti / Al are used. These wiring materials are also used as a metallization layer for joining metal components such as input / output pins, leads, and sealing rit by soldering or brazing heat treatment.
【0008】このようなメタライズ層としての多層金属
膜を用いて金属部品をAlN回路基板に接合しようとす
ると、この接合時の加熱により、配線層としての多層金
属膜とAlN回路基板との線熱膨脹係数の違いにより、
残留応力や各種の欠陥が生じる。この結果、配線層とし
ての多層金属膜とAlN回路基板との密着性が不十分に
なり、信頼性が低下してしまう。このよう問題は後工程
の熱処理でも生じる。When an attempt is made to bond a metal component to an AlN circuit board by using such a multilayer metal film as a metallized layer, the heating at the time of this bonding causes a linear thermal expansion between the multilayer metal film as a wiring layer and the AlN circuit board. Due to the difference in the coefficient,
Residual stress and various defects occur. As a result, the adhesion between the multi-layer metal film as the wiring layer and the AlN circuit board becomes insufficient, and the reliability deteriorates. Such a problem also occurs in the heat treatment in the subsequent process.
【0009】[0009]
【発明が解決しようとする課題】上述の如く、薄膜回路
の配線材料として、TiN/Ni/Au、Ti/Pt/
Au、Ti/Cu、Cr/Cu、Ti/Alなどの多層
金属膜が使用されていたが、これら多層金属膜はメタラ
イズ層としても用いられていたので、金属部品の接合時
の加熱等において、配線層としての多層金属膜とAlN
基板との密着性が低下し、信頼性が低下するという問題
があった。As described above, TiN / Ni / Au and Ti / Pt / are used as wiring materials for thin film circuits.
Multi-layer metal films such as Au, Ti / Cu, Cr / Cu, and Ti / Al were used, but since these multi-layer metal films were also used as metallization layers, in heating at the time of joining metal parts, etc., Multi-layer metal film as wiring layer and AlN
There is a problem that the adhesion to the substrate is reduced and the reliability is reduced.
【0010】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、多層金属膜とAlN基
板との密着性を改善し、信頼性の高い回路基板を提供す
ることにある。The present invention has been made in view of the above circumstances, and an object thereof is to improve the adhesion between a multilayer metal film and an AlN substrate to provide a highly reliable circuit board. is there.
【0011】[0011]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の回路基板は、窒化アルミニウムからなる
基板(AlN基板)と、このAlN基板の表面の窒化ア
ルミニウムに対してエピタキシャルに形成された窒化チ
タンアルミニウムからなる第1の金属層(AlTiN
層)と、このAlTiN層上に形成されたチタンからな
る第2の金属層(Ti層)と、このTi層上に形成され
た導電層とを備えた構成になっている。In order to achieve the above object, a circuit board of the present invention is formed epitaxially on a substrate (AlN substrate) made of aluminum nitride and aluminum nitride on the surface of the AlN substrate. First metal layer (AlTiN
Layer), a second metal layer (Ti layer) made of titanium and formed on the AlTiN layer, and a conductive layer formed on the Ti layer.
【0012】[0012]
【作用】本発明によれば、AlN基板とTi層との間
に、これらの相互拡散層に相当するAlTiN層が設け
られているので、AlN基板はAlTiN層を介してA
lN基板に強固に密着するようになる。According to the present invention, since the AlTiN layer corresponding to the interdiffusion layer is provided between the AlN substrate and the Ti layer, the AlN substrate is provided with the AlTiN layer via the AlTiN layer.
It comes to firmly adhere to the 1N substrate.
【0013】また、AlN基板に対してAlTiN層が
エピタキシャルに形成されているので、AlN基板とA
lTiN層との界面における格子不整などの界面欠陥が
減少し、AlN基板とAlTiN層との間の密着強度は
強いものとなる。更に、AlN基板とAlTiN層との
界面付近における応力集中が緩和される。これはAlN
基板とTi層との間の高密着強度の維持に寄与する。Since the AlTiN layer is epitaxially formed on the AlN substrate, the AlN substrate and the A
Interface defects such as lattice mismatch at the interface with the 1TiN layer are reduced, and the adhesion strength between the AlN substrate and the AlTiN layer becomes strong. Further, stress concentration near the interface between the AlN substrate and the AlTiN layer is relaxed. This is AlN
It contributes to maintain high adhesion strength between the substrate and the Ti layer.
【0014】なお、AlN基板が多結晶体の場合は、個
々の粒に対応したエピタキシャル膜となる。部分的に非
エピタキシャル膜があっても良く、少なくとも面積比で
50%以上がエピタキシャル成長していれば良い。When the AlN substrate is a polycrystal, it becomes an epitaxial film corresponding to each grain. There may be a partial non-epitaxial film, as long as at least 50% or more of the area ratio is epitaxially grown.
【0015】[0015]
【実施例】以下、図面を参照しながら実施例を説明す
る。図1は、本発明の一実施例に係る回路基板の構成を
示す断面図である。図中、1はAlN基板を示してお
り、このAlN基板1上にはその表面のAlNに対して
エピタキシャルなAlTiN層2が設けられている。こ
のAlTiN層2上にはTi層3を介して導電層4が設
けられている。Embodiments will be described below with reference to the drawings. FIG. 1 is a sectional view showing the structure of a circuit board according to an embodiment of the present invention. In the figure, reference numeral 1 denotes an AlN substrate, and an AlTiN layer 2 which is epitaxial with respect to AlN on its surface is provided on this AlN substrate 1. A conductive layer 4 is provided on the AlTiN layer 2 with a Ti layer 3 interposed therebetween.
【0016】ここで、エピタキシャルなAlTiN層2
とは、例えば、AlN基板1に対して以下のような関係
があるものである。すなわち、AlTiN層2の結晶構
造および面方位の少なくとも一方が、AlN基板1のそ
れと同じであり、且つAlTiN層2の一方向の格子定
数が、AlN基板1のそれの0.85以上1.15以
下、望ましくは0.90以上1.1以下になっているこ
とである。Here, the epitaxial AlTiN layer 2 is formed.
Means, for example, the following relationship with the AlN substrate 1. That is, at least one of the crystal structure and the plane orientation of the AlTiN layer 2 is the same as that of the AlN substrate 1, and the unidirectional lattice constant of the AlTiN layer 2 is 0.85 or more and 1.15 of that of the AlN substrate 1. Hereafter, it is preferably 0.90 or more and 1.1 or less.
【0017】ここで、格子定数の範囲を0.85以上
1.15以下にしたのは、0.85未満および1.15
を越えるあたりから、AlN基板1とAlTiN層2と
の界面における格子不整合が大きくなるからである。Here, the range of the lattice constant is 0.85 or more and 1.15 or less is less than 0.85 and 1.15.
This is because the lattice mismatch at the interface between the AlN substrate 1 and the AlTiN layer 2 becomes large from the point above.
【0018】なお、AlTiN層2のAl、Tiおよび
Nの組成比は結晶構造および格子定数によって決定さ
れ、AlN基板1とAlTiN層2との密着強度が損な
われないものであれば良い。The composition ratio of Al, Ti and N of the AlTiN layer 2 is determined by the crystal structure and the lattice constant, as long as the adhesion strength between the AlN substrate 1 and the AlTiN layer 2 is not impaired.
【0019】このように構成された回路基板によれば、
AlN基板1の表面のAlNに対してエピタキシャル
な、換言すれば、AlN基板1と同じ或いは近似な結晶
構造、面方位、格子定数を有するAlTiN層2がAl
基板1上に設けられているので、AlN基板1とAlT
iN層2との界面における欠陥が減少し、AlN基板1
とAlTiN層2との密着強度が向上する。According to the circuit board thus configured,
The AlTiN layer 2 that is epitaxial with respect to the AlN on the surface of the AlN substrate 1, in other words, has the same or similar crystal structure, plane orientation, and lattice constant as the AlN substrate 1 is Al.
Since it is provided on the substrate 1, the AlN substrate 1 and the AlT
The defects at the interface with the iN layer 2 are reduced, and the AlN substrate 1
The adhesion strength between AlTiN layer 2 and AlTiN layer 2 is improved.
【0020】また、AlN基板1とTi層3との間に
は、これらの相互拡散層に相当するAlTiN層2が設
けられているので、AlN基板1はAlTiN層2を介
してAlN基板1に強固に密着するようになる。Further, since the AlTiN layer 2 corresponding to the mutual diffusion layer is provided between the AlN substrate 1 and the Ti layer 3, the AlN substrate 1 is connected to the AlN substrate 1 via the AlTiN layer 2. It comes to firmly adhere.
【0021】次に図1の回路基板の製造方法について述
べる。まず、AlN基板1上にAlTiN層2を形成す
るが、AlN基板1としては熱伝導率が30〜310W
m-1K-1の範囲のものが望ましい。これは以下の理由に
よる。Next, a method of manufacturing the circuit board shown in FIG. 1 will be described. First, the AlTiN layer 2 is formed on the AlN substrate 1. The AlN substrate 1 has a thermal conductivity of 30 to 310 W.
It is preferably in the range of m -1 K -1 . This is for the following reason.
【0022】一般に、熱伝導率が高くなるに従いAlN
基板1に含まれる焼結助剤成分は減少する。熱伝導率が
30Wm-1K-1未満の場合には、AlN基板1に含有さ
れる焼結助剤成分が数10at%のレベルとなる。焼結
助剤成分はAlNの結晶粒界に局在し、焼結助剤成分の
増加に伴って局在面積が増大する。Generally, as the thermal conductivity increases, AlN
The sintering aid component contained in the substrate 1 is reduced. When the thermal conductivity is less than 30 Wm -1 K -1 , the sintering additive component contained in the AlN substrate 1 has a level of several tens at%. The sintering aid component is localized in the crystal grain boundaries of AlN, and the localized area increases as the sintering aid component increases.
【0023】このため、熱伝導率が30Wm-1K-1未満の
場合には、AlN基板1の表面には酸化物と窒化物とが
交互に存在するようになり、AlTiN層2の成膜条
件、密着強度などが大きく変動し、面内均一性が劣化
し、信頼性が低下する。Therefore, when the thermal conductivity is less than 30 Wm -1 K -1 , oxides and nitrides are alternately present on the surface of the AlN substrate 1, and the AlTiN layer 2 is formed. Conditions, adhesion strength, etc. vary greatly, in-plane uniformity deteriorates, and reliability decreases.
【0024】一方、熱伝導率が310Wm-1K-1を越え
ると、回路基板を形成する際の焼成条件が複雑になり工
程数が増加し、更に、回路基板に多用される同時焼成基
板では内部導体の抵抗が高くなり、これらの点からAl
N基板1の使用が非実用的となる。On the other hand, if the thermal conductivity exceeds 310 Wm -1 K -1 , the firing conditions for forming the circuit board are complicated and the number of steps is increased. Furthermore, in the co-fired board often used for circuit boards. The resistance of the inner conductor becomes high, and from these points, Al
Use of the N substrate 1 becomes impractical.
【0025】したがって、AlN基板1の熱伝導率は、
上述したように、30〜310Wm-1K-1の範囲が好ま
しく、更に好ましくは、40〜300Wm-1K-1の範囲
である。Therefore, the thermal conductivity of the AlN substrate 1 is
As described above, preferably in the range of 30~310Wm -1 K -1, more preferably, in the range of 40~300Wm -1 K -1.
【0026】また、AlTiN層2の原料としては、例
えば、Alの金属、窒化物、有機金属とTiの金属、窒
化物、有機金属若しくはAlとTiの金属、窒化物、有
機金属などを用いることができる。AlTiN層2の膜
厚は、0.5〜500nm程度とする。As the raw material of the AlTiN layer 2, for example, Al metal, nitride, organic metal and Ti metal, nitride, organic metal or Al and Ti metal, nitride, organic metal, etc. are used. You can The film thickness of the AlTiN layer 2 is about 0.5 to 500 nm.
【0027】AlTiN層2の形成方法としては、反応
スパッタ法、真空蒸着法、クラスタイオンビーム、イオ
ンプレーティンング、イオンミキシンング、ゾルゲル法
などの一般的な成膜技術を用い、必要に応じて、基板温
度、雰囲気、真空度、成膜速度、溶液濃度、ガス組成な
どを調整する。また、AlN基板1上にAlTiの金属
膜を薄膜法などで形成した後、その金属膜を窒化処理す
ることにより間接的にAlTiN層2を形成しても良
い。As a method of forming the AlTiN layer 2, a general film forming technique such as a reactive sputtering method, a vacuum vapor deposition method, a cluster ion beam, an ion plating, an ion mixing, a sol-gel method, etc. is used, and if necessary. , Substrate temperature, atmosphere, degree of vacuum, film formation rate, solution concentration, gas composition, etc. Alternatively, the AlTiN layer 2 may be indirectly formed by forming a metal film of AlTi on the AlN substrate 1 by a thin film method or the like and then nitriding the metal film.
【0028】また、Ti層3は、1〜900nm程度の
厚さに形成する。また、導電層4の材料としては、例え
ば、Au、Cu、Ag、Alから選ばれた少なくとも一
つの材料を用いる。なお、数μm以上の厚い導電膜4が
必要な場合にはめっき法などで形成すると良い。The Ti layer 3 is formed to have a thickness of about 1 to 900 nm. As the material of the conductive layer 4, for example, at least one material selected from Au, Cu, Ag and Al is used. If a thick conductive film 4 having a thickness of several μm or more is required, it may be formed by a plating method or the like.
【0029】また、AlTiN層2、Ti層3、導電層
4を形成する際にリソグラフィ法やリフトオフ法等の使
用が考えられるが、どの方法を使用するかは主に配線ピ
ッチやスルーホール寸法やメタライズ形成に要する工数
条件などにより選定する。Further, when forming the AlTiN layer 2, the Ti layer 3 and the conductive layer 4, it is possible to use a lithographic method or a lift-off method. Which method is mainly used is mainly the wiring pitch and the through hole size. It is selected according to the man-hour conditions required for metallization formation.
【0030】また、AlTiN層2、Ti層3、導電層
4の加工に使用するエッチングは、湿式および乾式のど
ちらでも良い。湿式エッチング法の場合には、例えば、
酸と塩、アルカリと塩のバッファー溶液などを用いれば
良い。一方、乾式エッチング法の場合には、塩素、有機
塩素、弗素、有機弗素などとアルゴンガスとの混合物中
若しくはアルゴンガス中にてプラズマ励起により行なえ
ば良い。The etching used for processing the AlTiN layer 2, the Ti layer 3 and the conductive layer 4 may be either wet or dry. In the case of the wet etching method, for example,
A buffer solution of an acid and a salt or an alkali and a salt may be used. On the other hand, in the case of the dry etching method, it may be performed by plasma excitation in a mixture of chlorine, organic chlorine, fluorine, organic fluorine, etc. and argon gas or in argon gas.
【0031】なお、本実施例の回路基板では、Ti層3
が導電層4に直に接しているが、Ti層3と導電層4と
の間にバリア層を設けても良い。バリア層の材料として
は、例えば、Ni、Pt、Ta、Wから選ばれた少なく
とも一つの材料を用いる。In the circuit board of this embodiment, the Ti layer 3 is used.
Is directly in contact with the conductive layer 4, but a barrier layer may be provided between the Ti layer 3 and the conductive layer 4. As the material of the barrier layer, for example, at least one material selected from Ni, Pt, Ta, and W is used.
【0032】本発明者等は、本実施例の回路基板の評価
を行なってみた。回路基板の種類は表1に示すように1
0個であり、また、AlTiN層、Ti層はスパッタ法
により形成した。パラメータは、AlN基板の熱伝導率
と、AlTiN層の組成と、AlTiN層をスパッタ形
成するときの原料ガスの流量比、ターゲットパワー、基
板温度および圧力と、Ti層の膜厚、Ti層をスパッタ
形成するときのターゲットパワーおよび圧力と、導電層
の材料および膜厚である。The present inventors evaluated the circuit board of this embodiment. The type of circuit board is 1 as shown in Table 1.
The number is 0, and the AlTiN layer and the Ti layer were formed by the sputtering method. The parameters are the thermal conductivity of the AlN substrate, the composition of the AlTiN layer, the flow rate ratio of the source gas when forming the AlTiN layer by sputtering, the target power, the substrate temperature and the pressure, the thickness of the Ti layer, and the sputtering of the Ti layer. The target power and pressure when forming, and the material and film thickness of the conductive layer.
【0033】[0033]
【表1】 [Table 1]
【0034】また、配線ピッチ、配線幅、配線間隔の値
は全ての回路基板で共通で、それぞれ、5mm、2.5
mm、2.5mmである。回路基板の評価は以下のよう
にして行なった。すなわち、回路基板を−65℃30分
〜室温1分〜150℃30分の熱サイクルを10000
回繰り返した後、図2に示すように、コバール板材6
(幅1mm×厚さ0.2mm)をはんだ若しくはろう材
5で回路基板に接合し、ピール強度を測定した。The values of the wiring pitch, the wiring width, and the wiring interval are common to all circuit boards and are 5 mm and 2.5 mm, respectively.
mm and 2.5 mm. The circuit board was evaluated as follows. That is, the circuit board is subjected to a thermal cycle of −65 ° C. for 30 minutes to room temperature for 1 minute to 150 ° C. for 30 minutes for 10,000 times.
After repeating the process, as shown in FIG.
(Width 1 mm × thickness 0.2 mm) was joined to the circuit board with solder or brazing material 5, and the peel strength was measured.
【0035】その結果、どの回路基板でもピール強度の
値は1000g以上であり、密着性に優れ、信頼性が改
善されていることを確認した。また、上記試料(No.
1〜10)を研磨により10〜100μmの厚さに加工
後、イオンミリング加工し、TEM観察用試料を作成し
た。TEMにより加速電圧400keVにて上記TEM
観察用試料を観察し、あわせて電子線回折およびエネル
ギー分散型X線回折を行なって、界面の方位、結晶構
造、組成を求めてみた。その結果を表2に示す。As a result, it was confirmed that the peel strength of all the circuit boards was 1000 g or more, the adhesion was excellent, and the reliability was improved. In addition, the sample (No.
1 to 10) were processed by polishing to a thickness of 10 to 100 μm, and then ion milled to prepare a TEM observation sample. The above TEM with an acceleration voltage of 400 keV by TEM
The observation sample was observed, and electron beam diffraction and energy dispersive X-ray diffraction were also performed to determine the orientation, crystal structure, and composition of the interface. The results are shown in Table 2.
【0036】[0036]
【表2】 [Table 2]
【0037】上記評価からAlTiN層が設けられた基
板では基板と膜との結晶方位が一致し、エピタキシャル
な関係にあることが判明した。一方、AlN基板とTi
層との間にAlTiN層が設けられていない従来の回路
基板についても同様な評価を行なってみた。From the above evaluation, it was found that the substrate provided with the AlTiN layer had an epitaxial relationship because the crystal orientations of the substrate and the film were the same. On the other hand, AlN substrate and Ti
The same evaluation was performed on a conventional circuit board having no AlTiN layer provided between the layers.
【0038】回路基板の種類は表2に示すように5個で
あり、AlTiN層に相当する金属層(AlTiN相当
層)、Ti層はスパッタ法により形成した。パラメータ
は、AlN基板の熱伝導率と、AlTiN相当層の材料
と、AlTiN相当層をスパッタ形成するときのターゲ
ットパワー、基板温度および圧力と、Ti層の膜厚、T
i層をスパッタ形成するときのターゲットパワーおよび
圧力と、導電層の材料および膜厚である。AlTiN相
当層をスパッタ形成するときのスパッタガスはどの回路
基板の場合もArガスである。なお、回路基板の配線ピ
ッチ、配線幅、配線間隔の条件は本発明の回路基板のそ
れらと同じである。As shown in Table 2, there are five kinds of circuit boards, and the metal layer corresponding to the AlTiN layer (AlTiN equivalent layer) and the Ti layer were formed by the sputtering method. The parameters are the thermal conductivity of the AlN substrate, the material of the AlTiN equivalent layer, the target power when the AlTiN equivalent layer is formed by sputtering, the substrate temperature and pressure, the thickness of the Ti layer, T
The target power and pressure when forming the i layer by sputtering, and the material and film thickness of the conductive layer. The sputter gas when forming the AlTiN equivalent layer by sputtering is Ar gas in any circuit board. The conditions of the wiring pitch, wiring width, and wiring interval of the circuit board are the same as those of the circuit board of the present invention.
【0039】[0039]
【表3】 [Table 3]
【0040】従来の回路基板の場合には、表2からピー
ル強度の値は50〜60gであり、本発明に比べて2桁
も小さく、信頼性に劣る回路基板であることが分かる。
更に、TEM観察、電子線回折およびエネルギー分散型
X線回折を行なって、界面の方位、結晶構造、組成を調
べたところ、AlTiN層がない基板では、基板と膜に
特定の方向関係はなかった。また、界面はAl,Ti,
Nを含むアモルファス層が介在していた。In the case of the conventional circuit board, it can be seen from Table 2 that the peel strength value is 50 to 60 g, which is two orders of magnitude smaller than that of the present invention, and the circuit board is inferior in reliability.
Furthermore, TEM observation, electron beam diffraction and energy dispersive X-ray diffraction were performed to examine the orientation, crystal structure, and composition of the interface. In the substrate without the AlTiN layer, there was no specific directional relationship between the substrate and the film. . The interface is Al, Ti,
An amorphous layer containing N was interposed.
【0041】[0041]
【発明の効果】以上詳述したように本発明によれば、A
lN基板とTi層との間に、AlN基板に対してエピタ
キシャルで、AlN基板およびTi層の相互拡散層に相
当するAlTiN層が設けられているので、密着性や界
面欠陥が改善され、回路基板に起因する信頼性の低下を
防止できるようになる。As described above in detail, according to the present invention, A
Since the AlTiN layer corresponding to the interdiffusion layer of the AlN substrate and the Ti layer is provided between the 1N substrate and the Ti layer and is epitaxial with respect to the AlN substrate, the adhesion and the interface defect are improved, and the circuit board is improved. It is possible to prevent a decrease in reliability due to the.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明の一実施例に係る回路基板を示す断面図FIG. 1 is a sectional view showing a circuit board according to an embodiment of the present invention.
【図2】ピール強度の評価に用いた回路基板を示す断面
図FIG. 2 is a sectional view showing a circuit board used for evaluation of peel strength.
1…AlN基板 2…AlTiN層(第1の金属層) 3…Ti層(第2の金属層記) 4…導電層 1 ... AlN substrate 2 ... AlTiN layer (first metal layer) 3 ... Ti layer (second metal layer) 4 ... Conductive layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小岩 馨 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 (72)発明者 岩瀬 暢男 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kaoru Koiwa 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Research and Development Center (72) Inventor Nobuo Iwase Komukai-Toshiba, Kawasaki-shi, Kanagawa Town No. 1 Toshiba Corporation Research & Development Center
Claims (1)
ャルに形成された窒化チタンアルミニウムからなる第1
の金属層と、 この第1の金属層上に形成されたチタンからなる第2の
金属層と、 この第2の金属層上に形成された導電層とを具備してな
ることを特徴とする回路基板。1. A substrate made of aluminum nitride and a first titanium aluminum nitride epitaxially formed on the aluminum nitride on the surface of the substrate.
And a second metal layer made of titanium formed on the first metal layer, and a conductive layer formed on the second metal layer. Circuit board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31018193A JP3322967B2 (en) | 1993-12-10 | 1993-12-10 | Circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31018193A JP3322967B2 (en) | 1993-12-10 | 1993-12-10 | Circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07161871A true JPH07161871A (en) | 1995-06-23 |
JP3322967B2 JP3322967B2 (en) | 2002-09-09 |
Family
ID=18002150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP31018193A Expired - Lifetime JP3322967B2 (en) | 1993-12-10 | 1993-12-10 | Circuit board |
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JP (1) | JP3322967B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10163378A (en) * | 1996-12-04 | 1998-06-19 | Toshiba Corp | Wiring board and its manufacture |
JP2000228568A (en) * | 1999-02-04 | 2000-08-15 | Dowa Mining Co Ltd | Aluminum-aluminum nitride insulating circuit board |
-
1993
- 1993-12-10 JP JP31018193A patent/JP3322967B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10163378A (en) * | 1996-12-04 | 1998-06-19 | Toshiba Corp | Wiring board and its manufacture |
JP2000228568A (en) * | 1999-02-04 | 2000-08-15 | Dowa Mining Co Ltd | Aluminum-aluminum nitride insulating circuit board |
Also Published As
Publication number | Publication date |
---|---|
JP3322967B2 (en) | 2002-09-09 |
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