JPH05129298A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor deviceInfo
- Publication number
- JPH05129298A JPH05129298A JP10135992A JP10135992A JPH05129298A JP H05129298 A JPH05129298 A JP H05129298A JP 10135992 A JP10135992 A JP 10135992A JP 10135992 A JP10135992 A JP 10135992A JP H05129298 A JPH05129298 A JP H05129298A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- orientation
- substrate
- sputtering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に詳細には、半導体チップ上にアルミニウムの
配線(Al配線)を形成する際に用いられる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, it is used for forming aluminum wiring (Al wiring) on a semiconductor chip.
【0002】[0002]
【従来の技術】Al配線形成のためのAl成膜として、
真空蒸着法のほかにスパッタリング法が知られている。
このような成膜法により形成されたAl配線には、エレ
クトロマイグレーション耐性やストレスマイグレーショ
ン耐性の高いことが要求される。2. Description of the Related Art As an Al film formation for forming an Al wiring,
Besides the vacuum vapor deposition method, the sputtering method is known.
The Al wiring formed by such a film forming method is required to have high electromigration resistance and stress migration resistance.
【0003】[0003]
【発明が解決しようとする課題】このため、従来から種
々の改善がなされているが、集積回路の微細化に伴うA
l配線の細線化の下では、いまだ十分とは言えず、半導
体装置の長寿命化の要請の下では、より優れた耐性を実
現することが課題となっている。ところで、Al配線の
エレクトロマイグレーション耐性は、Al膜の配向性に
依存することが、下記の文献『“EFFECT OF
TEXTURE AND GRAlN STRUCTU
RE〜”、75(1981)P.P.253〜259、
ThinSolid Films.』に示されている。
本発明者は、これにもとづき、特にスパッタリング成膜
法によるAl配線のエレクトロマイグレーション耐性の
向上について検討した結果、本発明を完成するに至っ
た。For this reason, various improvements have been made in the past, but with the miniaturization of integrated circuits,
It cannot be said that it is still sufficient under the thinning of the 1-wiring, and under the demand for longer life of the semiconductor device, realization of more excellent durability is an issue. By the way, the electromigration resistance of the Al wiring depends on the orientation of the Al film, as described in the following document "EFFECT OF.
TEXTURE AND GRAlN STRUCTU
RE ~ ", 75 (1981) P.P. 253-259,
ThinSolid Films. ].
Based on this, the present inventor has completed the present invention as a result of examining the improvement of the electromigration resistance of the Al wiring by the sputtering film forming method.
【0004】[0004]
【課題を解決するための手段】本発明に係る半導体装置
の製造方法は、基板上にアルミニウム膜をスパッタリン
グにより成膜する方法において、基板を150℃以上で
あって220℃以下の温度に設定し、2.0%以下の重
量比のシリコンと1.0%以下の重量比の銅を含むアル
ミニウム成膜材を用いてスパッタリングすることを特徴
とする。A method of manufacturing a semiconductor device according to the present invention is a method of forming an aluminum film on a substrate by sputtering, wherein the substrate is set at a temperature of 150 ° C. or higher and 220 ° C. or lower. The sputtering is performed using an aluminum film forming material containing silicon in a weight ratio of 2.0% or less and copper in a weight ratio of 1.0% or less.
【0005】[0005]
【作用】本発明によれば、Al(111)配向性が高
く、かつAl(200)配向性が略ゼロのAl膜を形成
でき、従ってAl配線のエレクトロマイグレーション耐
性を向上させることが可能となる。According to the present invention, an Al film having high Al (111) orientation and almost zero Al (200) orientation can be formed, and therefore, electromigration resistance of Al wiring can be improved. ..
【0006】[0006]
【実施例】Al配線は、一般的には次のようにして形成
される。まず、シリコンウエハなどの基板を用意し、シ
リコン酸化膜を形成する。次に、この基板をスパッタリ
ング装置にセットし、Al配線材をスパッタリング成膜
する。そして、Al膜上にレジストパターンを形成し、
これをマスクとしてAl膜をエッチングすることによ
り、所望パターンのAl配線が得られる。EXAMPLES Al wiring is generally formed as follows. First, a substrate such as a silicon wafer is prepared and a silicon oxide film is formed. Next, this substrate is set in a sputtering apparatus, and an Al wiring material is formed by sputtering. Then, a resist pattern is formed on the Al film,
By etching the Al film using this as a mask, an Al wiring having a desired pattern can be obtained.
【0007】本発明における配線材は、Alを主成分と
し、微量のSiと微量のCuを含む。ここで、Siは重
量比で2.0%以下が望ましく、Cuは重量比で1.0
%以下が望ましい。本発明におけるスパッタリング時の
基板温度は、150℃〜220℃であることが望まし
い。150℃未満ではAl(111)配向度が高くなら
ず、またAl(200)配向度を低く抑えることができ
ないためである。一方、220℃をこえる場合は、Al
(200)配向度は低くできるものの、Al(111)
配向度が高くできないからである。The wiring material in the present invention contains Al as a main component and contains a trace amount of Si and a trace amount of Cu. Here, Si is preferably 2.0% or less by weight ratio, and Cu is 1.0% by weight ratio.
% Or less is desirable. The substrate temperature during sputtering in the present invention is preferably 150 ° C to 220 ° C. This is because if the temperature is lower than 150 ° C., the degree of Al (111) orientation does not become high, and the degree of Al (200) orientation cannot be suppressed low. On the other hand, if the temperature exceeds 220 ° C, Al
Although the degree of (200) orientation can be lowered, Al (111)
This is because the degree of orientation cannot be increased.
【0008】次に、本発明者による具体的実施例を説明
する。まず、サンプルとしては、表面に0.6μmのS
iO2 膜を熱酸化で形成したシリコン基板を用意した。
そして、下記の要件で、1μmのAl膜をスパッタリン
グ成膜により形成した。まず、配線材には、1%のSi
と、0.5%のCuを含むAlを用い、スパッタリング
成膜装置にはマグネトロンスパッタリング装置を用い
た。また、DCスパッタパワーは6[KW]とし、Ar
の流量は50[SCCM]とし、スパッタ圧力は0.5
[Pa]とした。そして、Al配向度はX線回折強度で
示した。その結果を第1図に示す。基板温度を150〜
220℃とすることで、Al(111)配向を高くしな
がら、Al(200)配向を消滅させることが確認でき
た。Next, a concrete example by the present inventor will be described. First, as a sample, S of 0.6 μm on the surface
A silicon substrate having an iO 2 film formed by thermal oxidation was prepared.
Then, under the following requirements, a 1 μm Al film was formed by sputtering. First, for wiring materials, 1% Si
And Al containing 0.5% Cu were used, and a magnetron sputtering apparatus was used as the sputtering film forming apparatus. The DC sputter power is 6 [KW] and Ar is
Flow rate is 50 [SCCM] and the sputter pressure is 0.5
[Pa]. The degree of Al orientation is indicated by X-ray diffraction intensity. The results are shown in FIG. Substrate temperature 150 ~
It was confirmed that by setting the temperature to 220 ° C., the Al (200) orientation was extinguished while the Al (111) orientation was increased.
【0009】次に、120℃、186℃、240℃のそ
れぞれの基板温度で成膜された1.0%のSiと0.5
%のCuを含むAl膜を、通常のパターニング、エッチ
ング方法により配線に形成した後、常温CVD法による
PSG(Phospho Siliate Glas
s)を0.6μm成膜しエレクトロマイグレーション試
験を行った。このとき、配線幅は2.4μm、配線長は
1000μm、試験条件175℃、電流密度1E6A/
cm2 である。この結果を第2図に示す。Al(11
1)配向強度の高い基板加熱温度186℃は長寿命であ
ることが確認された。また、50%故障時間(MTF)
で比較すると120℃で1300Hr、240℃で25
90Hrであるが、186℃では5000Hrであっ
た。Next, 1.0% Si and 0.5 formed at respective substrate temperatures of 120 ° C., 186 ° C. and 240 ° C.
% Cu is formed on the wiring by a normal patterning and etching method, and then PSG (Phospho Silicate Glass) is formed by a room temperature CVD method.
A film having a thickness of 0.6 μm was formed and an electromigration test was conducted. At this time, the wiring width is 2.4 μm, the wiring length is 1000 μm, the test condition is 175 ° C., and the current density is 1E6A /
cm 2 . The results are shown in FIG. Al (11
1) It was confirmed that a substrate heating temperature of 186 ° C. having a high orientation strength has a long life. Also, 50% failure time (MTF)
Comparing with 1300Hr at 120 ℃, 25 at 240 ℃
Although it was 90 hr, it was 5000 hr at 186 ° C.
【0010】従って、上記の結果より、基板温度を15
0〜220℃とすることで、Al(111)配向を高く
しながら、Al(200)配向を消滅させ、エレクトロ
マイグレーション耐性を向上できることが確認された。Therefore, based on the above results, the substrate temperature is set to 15
It was confirmed that by setting the temperature to 0 to 220 ° C., the Al (200) orientation can be eliminated while increasing the Al (111) orientation, and the electromigration resistance can be improved.
【0011】[0011]
【発明の効果】以上、詳細に説明した通り本発明では、
Al(111)配向性が高く、かつAl(200)配向
性が略ゼロのAl膜を形成でき、従ってAl配線のエレ
クトロマイグレーション耐性を向上させることが可能と
なる。このため、半導体装置の信頼性の向上や、長寿命
化に寄与することができる。As described above in detail, according to the present invention,
An Al film having a high Al (111) orientation and a substantially zero Al (200) orientation can be formed, and therefore the electromigration resistance of the Al wiring can be improved. Therefore, the reliability of the semiconductor device can be improved and the life of the semiconductor device can be extended.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明の実施例の結果を示す図である。FIG. 1 is a diagram showing a result of an example of the present invention.
【図2】本発明の実施例のエレクトロマイグレーション
試験の結果を示す図である。FIG. 2 is a diagram showing a result of an electromigration test of an example of the present invention.
Claims (1)
グにより成膜する半導体装置の製造方法において、前記
基板を150℃以上であって220℃以下の温度に設定
し、2.0%以下の重量比のシリコンと1.0%以下の
重量比の銅を含むアルミニウム成膜材を用いてスパッタ
リングすることを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device in which an aluminum film is formed on a substrate by sputtering, wherein the substrate is set to a temperature of 150 ° C. or higher and 220 ° C. or lower, and a weight ratio of 2.0% or lower. A method for manufacturing a semiconductor device, comprising: sputtering using an aluminum film forming material containing silicon and copper in a weight ratio of 1.0% or less.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10135992A JPH05129298A (en) | 1991-04-22 | 1992-04-21 | Method of manufacturing semiconductor device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3-90601 | 1991-04-22 | ||
JP9060191 | 1991-04-22 | ||
JP10135992A JPH05129298A (en) | 1991-04-22 | 1992-04-21 | Method of manufacturing semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05129298A true JPH05129298A (en) | 1993-05-25 |
Family
ID=26432064
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10135992A Pending JPH05129298A (en) | 1991-04-22 | 1992-04-21 | Method of manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05129298A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5747360A (en) * | 1993-09-17 | 1998-05-05 | Applied Materials, Inc. | Method of metalizing a semiconductor wafer |
WO2017010263A1 (en) * | 2015-07-10 | 2017-01-19 | ソニー株式会社 | Solid-state image pickup device, manufacturing method, and electronic equipment |
-
1992
- 1992-04-21 JP JP10135992A patent/JPH05129298A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5747360A (en) * | 1993-09-17 | 1998-05-05 | Applied Materials, Inc. | Method of metalizing a semiconductor wafer |
US5904562A (en) * | 1993-09-17 | 1999-05-18 | Applied Materials, Inc. | Method of metallizing a semiconductor wafer |
WO2017010263A1 (en) * | 2015-07-10 | 2017-01-19 | ソニー株式会社 | Solid-state image pickup device, manufacturing method, and electronic equipment |
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