JP2839523B2 - Dielectric substrate with metal film for matching circuit formation - Google Patents
Dielectric substrate with metal film for matching circuit formationInfo
- Publication number
- JP2839523B2 JP2839523B2 JP1010903A JP1090389A JP2839523B2 JP 2839523 B2 JP2839523 B2 JP 2839523B2 JP 1010903 A JP1010903 A JP 1010903A JP 1090389 A JP1090389 A JP 1090389A JP 2839523 B2 JP2839523 B2 JP 2839523B2
- Authority
- JP
- Japan
- Prior art keywords
- metal film
- dielectric substrate
- matching circuit
- substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Waveguides (AREA)
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は、高周波半導体装置に用いられる内部整合回
路部品の金属膜付き誘電体基板に係り、特に石英ガラ
ス，セラミック当の誘電体基板とこれに接着される金属
膜との接着に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a dielectric substrate with a metal film of an internal matching circuit component used in a high-frequency semiconductor device, and particularly to a quartz glass, a ceramic substrate and the like. The present invention relates to bonding between a dielectric substrate and a metal film bonded thereto.
（従来の技術） 高周波半導体装置に用いられる内部整合回路は、半導
体素子ペレットの持つ特性インピーダンスを50Ωに変換
して、半導体素子ペレットの高周波特性（RF特性）を最
大限に引き出すための回路である。この内部整合回路
は、集中定数回路と分布定数回路に分けられる場合が多
い。この集中定数回路は、インダクタンス成分である金
（Au）ワイヤと、キャパシタンス成分である誘電体基板
等で構成され、半導体素子ペレットの特性インピーダン
スを、インダクタンス成分とキャパシタンス成分で50Ω
になるように大まかな調整を行なうものである。次に分
布定数回路には、50Ωストリップラインに加えてトリミ
ングパターンを有する場合が多い。50Ωストリップライ
ン幅は、整合回路用誘電体基板の厚さ及び誘電率と使用
周波数で決まる。トリミングパターンは、前記集中定数
回路で大まかに調整した特性インピーダンスを、さらに
50Ωに近づけるように微調整するものである。(Prior Art) An internal matching circuit used in a high-frequency semiconductor device is a circuit for converting the characteristic impedance of a semiconductor element pellet to 50 Ω to maximize the high-frequency characteristics (RF characteristics) of the semiconductor element pellet. . This internal matching circuit is often divided into a lumped constant circuit and a distributed constant circuit. This lumped constant circuit is composed of a gold (Au) wire that is an inductance component, a dielectric substrate that is a capacitance component, and the like.
The rough adjustment is made so that Next, the distributed constant circuit often has a trimming pattern in addition to the 50Ω strip line. The 50Ω stripline width is determined by the thickness and dielectric constant of the matching circuit dielectric substrate and the operating frequency. The trimming pattern further includes a characteristic impedance roughly adjusted by the lumped constant circuit,
Fine adjustment is made to approach 50Ω.
（発明が解決しようとする課題） 近年、高周波半導体素子の超高周波化の進歩は目覚ま
しく、これに対応する整合回路の開発も盛んに行われて
いる。使用周波数が20GHzを越える超高周波半導体装置
の分布定数回路の整合回路用基板に、アルミナ基板を用
いた場合には、50Ωストリップライン幅が細くなり、ラ
イン抵抗が大きくなる。このため、内部整合回路の電力
損失は増大し、半導体装置のRF特性の低下を起こし易
い。しかし、石英ガラス基板を分布定数回路の整合回路
用基板に用いた場合には、ストリップライン幅を広くで
きるので、ライン抵抗は小さくできる。つまり、内部整
合回路の電力損失を最少限に押さえることができる。こ
の理由は、次の第１表に示すように、石英ガラス基板は
アルミナ基板に比べ比誘電率が1/2であることによる。(Problems to be Solved by the Invention) In recent years, the progress of ultra-high-frequency semiconductor devices has been remarkable, and matching circuits corresponding thereto have been actively developed. When an alumina substrate is used as a matching circuit substrate of a distributed constant circuit of an ultra-high frequency semiconductor device whose use frequency exceeds 20 GHz, the 50Ω strip line width becomes narrow and the line resistance becomes large. For this reason, the power loss of the internal matching circuit increases, and the RF characteristics of the semiconductor device are likely to deteriorate. However, when a quartz glass substrate is used as a matching circuit substrate for a distributed constant circuit, the line resistance can be reduced because the strip line width can be increased. That is, the power loss of the internal matching circuit can be minimized. The reason for this is that, as shown in Table 1 below, the quartz glass substrate has a relative permittivity that is 1/2 that of the alumina substrate.
また、内部整合回路の集中定数回路で、長いボンディ
ングワイヤの支えとしての補助部材として中継用基板に
アルミナ基板を用いる場合、この基板の上部電極部と対
向する部分の間に発生する寄生容量が大きくなって、整
合回路の広帯域化は難しかった。寄生容量を小さくする
には、この基板を厚くしなければならず、この場合、他
の回路部品との段差が大きくなり、Auワイヤとの接続が
難しくなるという欠点があった。しかしながら、石英ガ
ラス基板を用いる場合には、比誘電率が小さいため基板
が比較的薄くても寄生容量を小さくできるので、整合回
路の広帯域化が可能になると共に、他の回路部品との段
差を小さくできるためにAuワイヤとの接続が容易になっ
た。 In the case where an alumina substrate is used as a relay substrate as an auxiliary member for supporting a long bonding wire in a lumped constant circuit of an internal matching circuit, a parasitic capacitance generated between a portion of the substrate facing the upper electrode portion is large. Thus, it was difficult to increase the bandwidth of the matching circuit. In order to reduce the parasitic capacitance, this substrate must be made thick. In this case, there is a disadvantage that a step with other circuit components becomes large and connection with an Au wire becomes difficult. However, when a quartz glass substrate is used, the parasitic capacitance can be reduced even if the substrate is relatively thin because the relative dielectric constant is small, so that the matching circuit can have a wider band and a step with other circuit components can be reduced. Connection with Au wire became easy because it could be made smaller.
一般に、電子部品用材料の中で広範囲に用いられてい
る石英ガラスやセラミックスからなる誘電体基板は、そ
れが化学的に非常に安定であるために、金属との接着が
極めて難しい。この接着法に関してMo−Mn法、蒸着法な
どの種々の技術が既に開発されている。しかし、これら
はその簡易さ、製品コスト、システムの信頼性など、実
装面で一長一短がある。Mo−Mn法は、最も安定した誘電
体基板への金属の接着方法である。しかし、この場合、
周波数が高くなるに従ってパターンも微細になるので、
この微細加工の点に限界があり、近年の高周波化には対
応が難しくなるという欠点があった。In general, a dielectric substrate made of quartz glass or ceramics, which is widely used as a material for electronic components, is extremely difficult to adhere to a metal because it is chemically very stable. Various techniques such as the Mo-Mn method and the vapor deposition method have already been developed for this bonding method. However, these have advantages and disadvantages in terms of mounting, such as simplicity, product cost, and system reliability. The Mo-Mn method is the most stable method of bonding a metal to a dielectric substrate. But in this case,
Since the pattern becomes finer as the frequency increases,
There is a limit in the point of the fine processing, and there is a disadvantage that it is difficult to cope with the recent increase in the frequency.
他方、蒸着法は微細加工の点で優れており、高周化対
応に最適である。しかし、この方法には、以下に述べる
様なプロセス上の問題がある。まず、前処理工程におい
ては、弗酸処理による誘電体基板表面の腐蝕が必要であ
ること、及び誘電体基板表面の水気を除去するために、
高温に加熱したまま金属を蒸着する必要があることであ
る。このため、特殊な装置が必要となった。さらに悪い
ことに、この様な特殊プロセスを用いても、金属膜と誘
電体基板との接着力に再現性がなく、温度サイクル試
験、ボンディング強度試験で、金属膜が剥れる不良が多
発するという致命的な技術的課題があった。On the other hand, the vapor deposition method is excellent in terms of fine processing, and is most suitable for a high-frequency operation. However, this method has process problems as described below. First, in the pre-treatment step, it is necessary to corrode the dielectric substrate surface by hydrofluoric acid treatment, and to remove moisture on the dielectric substrate surface.
It is necessary to deposit the metal while heating to a high temperature. For this reason, a special device was required. To make matters worse, even if such a special process is used, there is no reproducibility in the adhesive strength between the metal film and the dielectric substrate, and in the temperature cycle test and the bonding strength test, defects that the metal film peels frequently occur. There was a fatal technical challenge.
以上述べたように、従来の高周波用の金属膜付き誘電
体基板の構造では、金属膜と誘電体基板との接着力が弱
く、金属膜の剥れ不良が発生していた。As described above, in the conventional structure of the dielectric substrate with a metal film for high frequency, the adhesive strength between the metal film and the dielectric substrate is weak, and the metal film is poorly peeled.
この発明は上記の欠点を除去するもので、誘電体基板
と金属膜との剥れ不良を排除した整合回路形成用金属膜
付き誘電体基板の構造を提供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a structure of a dielectric substrate with a metal film for forming a matching circuit, which eliminates the above-mentioned disadvantages and eliminates peeling failure between the dielectric substrate and the metal film.
（課題を解決するための手段） 本発明にかかる整合回路形成用金属膜付き誘電体基板
は、ガラス基板と、このガラス基板面に被着された窒化
シリコン膜と、前記ガラス基板と前記窒化シリコン膜と
が被着した被着部分の前記窒化シリコン膜上に被着さ
れ、ワイヤがボンディングされる金属膜とを具備したこ
とを特徴とするものである。(Means for Solving the Problems) A dielectric substrate with a metal film for forming a matching circuit according to the present invention includes a glass substrate, a silicon nitride film deposited on the glass substrate surface, the glass substrate and the silicon nitride film. And a metal film to which a wire is bonded, on the silicon nitride film at a portion where the film is bonded.
（作 用） 本発明の整合回路形成用金属膜付き誘電体基板は、誘
電体基板と金属膜との両方に接着力の強い中間層として
窒化シリコン膜が構成されているので、誘電体基板と金
属膜の剥れ不良がなくなる。(Operation) In the dielectric substrate with a metal film for forming a matching circuit of the present invention, since the silicon nitride film is formed as an intermediate layer having a strong adhesive force on both the dielectric substrate and the metal film, the dielectric substrate The peeling failure of the metal film is eliminated.
（実施例） 以下、本発明にかかる金属膜付き誘電体基板の一実施
例につき第１図を参照して説明する。Example An example of a dielectric substrate with a metal film according to the present invention will be described below with reference to FIG.
第１図に示す金属膜付き誘電体基板は、石英ガラス基
板１の一主面に窒化シリコン膜（Si3N4膜）２を介し
て、チタニウム層（Ti層）３と白金層（Pt層）４と金属
（Au層）５よりなる（積層）金属膜11が形成されたもの
である。上記Si3N4膜２は減圧CVD法により一例の膜厚が
1000Åに、Ti層3,Pt等４はいずれもスパッタ蒸着法によ
り層厚1500Åに、Au層の一部下地層5aはスパッタ蒸着法
により層厚5000Åに夫々が順次積層して形成され、さら
にこのAu層5a上には電解めっき法によってAu層5bが４μ
ｍ厚に被着されてAu層５が構成されている。The dielectric substrate with a metal film shown in FIG. 1 has a titanium layer (Ti layer) 3 and a platinum layer (Pt layer) on one main surface of a quartz glass substrate 1 via a silicon nitride film (Si 3 N 4 film) 2. ) 4 and a metal (Au layer) 5 (laminated) metal film 11 is formed. The above Si 3 N 4 film 2 has an example film thickness by a low pressure CVD method.
The thickness of each of the Ti layer 3 and the Pt 4 is formed to a thickness of 1500 一部 by a sputter deposition method, and the partial underlayer 5 a of the Au layer is formed to a thickness of 5000 順次 by a sputtering deposition method. Au layer 5b is 4μ on layer 5a by electrolytic plating.
The Au layer 5 is formed so as to have a thickness of m.
叙上の構造により、金属膜の剥れ不良は排除された。
この理由は、石英ガラスと窒化シリコン膜の接着力及び
窒化シリコン膜と金属膜の接着力が共に強いためと考え
られる。With the above structure, the peeling failure of the metal film was eliminated.
It is considered that the reason for this is that the adhesion between the quartz glass and the silicon nitride film and the adhesion between the silicon nitride film and the metal film are both strong.
さらに、この構造では、前工程の弗酸処理と蒸着時の
加熱が省略できるという利点も生まれた。In addition, this structure also has an advantage in that the hydrofluoric acid treatment in the previous step and the heating during the vapor deposition can be omitted.
なお、石英ガラス表面と金属膜との間に、中間層とし
て二酸化シリコン膜を有する構造が考えられる。この構
造においては、石英ガラス基板と二酸化シリコン膜との
接着力は充分改善されたが、しかし、金属膜と二酸化シ
リコン膜（SiO2膜）との接着力は改善されず、金属膜の
剥れ不良は相変わらず生じた。これにより、窒化シリコ
ン膜を中間層として用いることに意味があると判断でき
る。Note that a structure having a silicon dioxide film as an intermediate layer between the quartz glass surface and the metal film is conceivable. In this structure, the adhesion between the quartz glass substrate and the silicon dioxide film was sufficiently improved, however, the adhesion between the metal film and the silicon dioxide film (SiO 2 film) was not improved, and the metal film was peeled off. Failure continued to occur. Thus, it can be determined that it is meaningful to use the silicon nitride film as the intermediate layer.
なお、石英ガラスを用いた場合には、従来のアルミナ
基板を用いた場合に比べ比誘電率が半減するため中継用
基板の容量を半分にすることができ、例えば、3GHz帯用
高周波トランジスタの帯域特性は、従来のものに比べ
て、1.2倍に広帯域化ができるなど、大いにい半導体素
子の性能を向上させることができた。When quartz glass is used, the relative dielectric constant is reduced by half compared to the case where a conventional alumina substrate is used, so that the capacity of the relay substrate can be halved. With respect to the characteristics, the performance of the semiconductor device could be greatly improved, for example, the bandwidth could be 1.2 times wider than that of the conventional device.
以上、本発明の実施例として、ボンディングワイヤの
石英ガラスから成る中継用基板について説明したが、こ
れに限定されるものではなく、超高周波半導体装置の内
部整合回路部品用の金属膜付き誘電体基板にも同様の効
果が得られる。As described above, as an embodiment of the present invention, a relay substrate made of quartz glass for bonding wires has been described. However, the present invention is not limited to this, and a dielectric substrate with a metal film for an internal matching circuit component of an ultra-high frequency semiconductor device is used. A similar effect can be obtained.
次に、上記実施例では金属膜として誘電体基板側から
Ti/Pt/Auをこの順に積層した膜を用いた場合を例示した
が、これに限らず、他の金属膜、例えばCr/Auの積層膜
を用いても同様の効果が得られた。Next, in the above embodiment, the metal film is formed from the dielectric substrate side.
The case where a film in which Ti / Pt / Au is laminated in this order is used is exemplified, but the present invention is not limited to this, and similar effects can be obtained by using another metal film, for example, a laminated film of Cr / Au.
上述の如く本発明によれば、石英ガラスなどの誘電体
基板と金属膜との間に窒化シリコン膜を介在させること
により、特別な表面処理を施すことなく金属の接着の信
頼性を高められる金属膜付き誘電体基板が得られる顕著
な効果がある。As described above, according to the present invention, by interposing a silicon nitride film between a dielectric substrate such as quartz glass and a metal film, it is possible to increase the reliability of metal bonding without performing a special surface treatment. There is a remarkable effect that a dielectric substrate with a film can be obtained.
第１図は本発明にかかる金属膜付き誘電体基板の断面図
である。 １……石英ガラス基板、２……Si3N4膜11 ……（積層）金属膜FIG. 1 is a sectional view of a dielectric substrate with a metal film according to the present invention. 1 ...... quartz glass substrate, 2 ...... Si 3 N 4 film 11 ... (laminated) metal film
Claims (1)
れた窒化シリコン膜と、前記ガラス基板と前記窒化シリ
コン膜とが被着した被着部分の前記窒化シリコン膜上に
被着され、ワイヤがボンディングされる金属膜とを具備
した整合回路形成用金属膜付き誘電体基板。1. A glass substrate, a silicon nitride film deposited on the glass substrate surface, and a silicon nitride film deposited on a portion where the glass substrate and the silicon nitride film are deposited, A dielectric substrate with a metal film for forming a matching circuit, comprising: a metal film to which wires are bonded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1010903A JP2839523B2 (en) | 1989-01-19 | 1989-01-19 | Dielectric substrate with metal film for matching circuit formation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1010903A JP2839523B2 (en) | 1989-01-19 | 1989-01-19 | Dielectric substrate with metal film for matching circuit formation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02191349A JPH02191349A (en) | 1990-07-27 |
| JP2839523B2 true JP2839523B2 (en) | 1998-12-16 |
Family
ID=11763256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1010903A Expired - Lifetime JP2839523B2 (en) | 1989-01-19 | 1989-01-19 | Dielectric substrate with metal film for matching circuit formation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2839523B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6350397B1 (en) | 1999-03-10 | 2002-02-26 | Aspen Research Corporation | Optical member with layer having a coating geometry and composition that enhance cleaning properties |
| US8299873B2 (en) * | 2008-12-23 | 2012-10-30 | International Business Machines Corporation | Millimeter wave transmission line for slow phase velocity |
| GB2488515B (en) * | 2011-02-11 | 2015-05-20 | Teraview Ltd | A test system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60133758A (en) * | 1983-12-21 | 1985-07-16 | Seiko Epson Corp | Manufacture of mos type semiconductor device |
-
1989
- 1989-01-19 JP JP1010903A patent/JP2839523B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02191349A (en) | 1990-07-27 |
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