JPH02191349A - Dielectric substrate with metal film - Google Patents
Dielectric substrate with metal filmInfo
- Publication number
- JPH02191349A JPH02191349A JP1090389A JP1090389A JPH02191349A JP H02191349 A JPH02191349 A JP H02191349A JP 1090389 A JP1090389 A JP 1090389A JP 1090389 A JP1090389 A JP 1090389A JP H02191349 A JPH02191349 A JP H02191349A
- Authority
- JP
- Japan
- Prior art keywords
- metal film
- dielectric substrate
- film
- substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 55
- 239000002184 metal Substances 0.000 title claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 44
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 21
- 238000000034 method Methods 0.000 abstract description 14
- 230000007547 defect Effects 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract 3
- 239000010936 titanium Substances 0.000 abstract 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 229910052697 platinum Inorganic materials 0.000 abstract 1
- 229910052719 titanium Inorganic materials 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 10
- 239000010931 gold Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 238000010306 acid treatment Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、高周波半導体装置に用いられる内部整合回路
部品の金属膜付き誘電体基板に係り、特に石英ガラス、
セラミック等の誘電体基板とこれに接着される金属膜と
の接着に関する。Detailed Description of the Invention [Object of the Invention] (Industrial Field of Application) The present invention relates to a dielectric substrate with a metal film for an internal matching circuit component used in a high-frequency semiconductor device, and particularly relates to a dielectric substrate with a metal film for an internal matching circuit component used in a high-frequency semiconductor device.
This field relates to adhesion between a dielectric substrate such as a ceramic substrate and a metal film bonded thereto.
（従来の技術）
高周波半導体装置に用いられる内部整合回路は、半導体
素子ベレットの持つ特性インピーダンスを５０Ωに変換
して、半導体素子ベレットの高周波特性（ＲＦ特性）、
を最大限に引き出すための回路である。この内部整合回
路は、集中定数回路と分布定数回路に分けられる場合が
多い。この集中定数回路は、インダクタンス成分である
金（Ａｕ＞ワイヤと、キャパシタンス成分である誘電体
基板等で構成され、半導体素子ベレットの特性インピー
ダンスを、インダクタンス成分とキャパシタンス成分で
５０Ωになるように大まかな調整を行なうものである。(Prior art) An internal matching circuit used in a high-frequency semiconductor device converts the characteristic impedance of the semiconductor element pellet to 50Ω, and improves the high frequency characteristics (RF characteristics) of the semiconductor element pellet.
This is a circuit that brings out the maximum potential. This internal matching circuit is often divided into lumped constant circuits and distributed constant circuits. This lumped constant circuit is composed of a gold (Au> wire as an inductance component) and a dielectric substrate as a capacitance component. It is for making adjustments.
次に分布定数回路には、５０Ωストリツプラインに加え
てトリミングパターンを有する場合が多い。５０Ωスト
リツプライン幅は、整合回路用誘電体幕板の厚さ及び誘
電率と使用周波数で決まる。トリミングパターンは、前
記集中定数回路で大まかに調整した特性インピーダンス
を、さらに５０Ωに近づけるように微調整するものであ
る。Next, distributed constant circuits often have a trimming pattern in addition to the 50Ω stripline. The width of the 50Ω stripline is determined by the thickness and dielectric constant of the dielectric curtain plate for the matching circuit, and the frequency used. The trimming pattern is used to finely adjust the characteristic impedance roughly adjusted by the lumped constant circuit so that it approaches 50Ω.
（発明が解決しようとする課題）
近年、高周波半導体素子の超高周波化の進歩は目覚まし
く、これに対応する整合回路の開発も盛んに行われてい
る。使用周波数が２０ＧＨｚを越える超高周波半導体装
置の分布定数回路の整合回路用基板に、アルミナ基板を
用いた場合には、５０Ωストリップライン幅が細くなり
、ライン抵抗が大きくなる。このため、内部整合回路の
電力損失は増大し、半導体装置のＲＦ特性の低下を起こ
し易い。(Problems to be Solved by the Invention) In recent years, there has been remarkable progress in increasing the frequency of high-frequency semiconductor elements to ultra-high frequencies, and matching circuits corresponding to this have been actively developed. When an alumina substrate is used as a matching circuit substrate for a distributed constant circuit of an ultra-high frequency semiconductor device whose operating frequency exceeds 20 GHz, the width of the 50Ω strip line becomes narrower and the line resistance increases. Therefore, the power loss of the internal matching circuit increases, and the RF characteristics of the semiconductor device tend to deteriorate.
しかし、石英ガラス基板を分布定数回路の整合回路用基
板に用いた場合には、ストリップライン幅を広くできる
ので、ライン抵抗は小さくできる。However, when a quartz glass substrate is used as a matching circuit substrate for a distributed constant circuit, the strip line width can be increased, and the line resistance can be reduced.
つまり、内部整合回路の電力損失を最少限に押さえるこ
とができる。この理由は、次の第１表に示すように、石
英ガラス基板はアルミナ基板に比べ比誘電率が１７２で
あることによる。In other words, power loss in the internal matching circuit can be minimized. The reason for this is that the quartz glass substrate has a dielectric constant of 172 compared to the alumina substrate, as shown in Table 1 below.
第１表
また、内部整合回路の集中定数回路で、長いボンディン
グワイヤの支えとしての補助部材として中継用基板にア
ルミナ基板を用いる場合、この基板の上部電極部と対向
する部分の間に発生する寄生容量が大きくなって、整合
回路の広帯域化は難しかった。奇生容量を小さくするに
は、この基板を厚くしなければならず、この場合、伯の
回路部品との段差が大きくなり、Ａｕワイヤとの接続が
難しくなるという欠点があった。しかしながら、石英ガ
ラス基板を用いる場合には、比誘電率が小さいため基板
が比較的薄くても奇生容量を小さくできるので、整合回
路の広帯域化が可能になると共に、他の回路部品との段
差を小さくできるためにＡｕワイヤとの接続が容易にな
った。Table 1 also shows that when an alumina substrate is used as a relay substrate as an auxiliary member to support a long bonding wire in a lumped constant circuit of an internal matching circuit, parasitics occur between the upper electrode part and the opposing part of this substrate. As the capacitance increased, it was difficult to widen the bandwidth of the matching circuit. In order to reduce the stray capacitance, this substrate must be made thicker, and in this case, there was a drawback that the height difference between the substrate and the other circuit components became large, making it difficult to connect with the Au wire. However, when using a silica glass substrate, the dielectric constant is small, so even if the substrate is relatively thin, the stray capacitance can be reduced, making it possible to widen the band of the matching circuit and to reduce the level difference between other circuit components. Since it can be made smaller, connection with Au wire becomes easier.
一般に、電子部品用材料の中で広範囲に用いられている
石英ガラスやセラミックスからなる誘電体基板は、それ
が化学的に非常に安定であるために、金属との接着が極
めて封しい。この接着法に関して）Ｉｏ−Ｍｎ法、蒸着
法などの種々の技術が既に開発されている。しかし、こ
れらはその簡易さ、製品コスト、システムの信頼性など
、実装面で一長一短がある。）ｌｏ−）Ｉｎ法は、最も
安定した誘電体基板への金属の接着方法である。しかし
、この場合、周波数が高くなるに従ってパターンも微細
になるので、この微細加工の点に限界があり、近年の高
周波化には対応が難しくなるという欠点があった。In general, dielectric substrates made of quartz glass or ceramics, which are widely used as materials for electronic components, are chemically very stable and therefore bond extremely tightly to metals. Regarding this bonding method, various techniques such as the Io-Mn method and the vapor deposition method have already been developed. However, these have advantages and disadvantages in terms of implementation, such as simplicity, product cost, and system reliability. )lo-)In method is the most stable method for bonding metal to dielectric substrates. However, in this case, as the frequency becomes higher, the pattern becomes finer, so there is a limit to this fine processing, and there is a drawback that it becomes difficult to cope with the recent trend toward higher frequencies.
他方、蒸着法は微細加工の点で優れており、高周波化対
応に最適である。しかし、この方法には、以下に述べる
様なプロセス上の問題がある。まず、前処理工程におい
ては、弗酸処理による誘電体基板表面の腐蝕が必要であ
ること、及び誘電体基板表面の水気を除去するために、
７Ｓ温に加熱したまま金属を蒸着する必要があることで
ある。このため、特殊な装置が必要となった。ざらに悪
いことには、この様な特殊プロセスを用いても、金属膜
と誘電体基板との接着力に再現性がなく、温度サイクル
試験、ボンディング強度試験で、金属膜が剥れる不良が
多発するという致命的な技術的課題があった。On the other hand, the vapor deposition method is superior in terms of microfabrication and is optimal for high frequency applications. However, this method has process problems as described below. First, in the pretreatment process, it is necessary to corrode the surface of the dielectric substrate by hydrofluoric acid treatment, and in order to remove moisture from the surface of the dielectric substrate,
It is necessary to vapor-deposit metal while heating to 7S temperature. This required special equipment. To make matters worse, even with this special process, the adhesion between the metal film and the dielectric substrate is not reproducible, resulting in frequent failures in which the metal film peels off during temperature cycle tests and bonding strength tests. There was a fatal technical problem.
以上述べたように、従来の高周波用の金属膜付き誘電体
基板の構造では、金属膜と誘電体基板との接着力が弱く
、金属膜の剥れ不良が発生していた。As described above, in the conventional structure of a dielectric substrate with a metal film for high frequency use, the adhesion between the metal film and the dielectric substrate is weak, resulting in failure of the metal film to peel off.
この発明は上記の欠点を除去するもので、誘電体基板と
金属膜との剥れ不良を排除した金属膜付き誘電体基板の
構造を提供することを目的とする。The present invention eliminates the above-mentioned drawbacks, and aims to provide a structure of a dielectric substrate with a metal film that eliminates peeling defects between the dielectric substrate and the metal film.
（課題を解決するだめの手段）
本発明にかかる金属膜付き誘電体基板は、誘電体基板と
、該誘電体基板の主面に被着された窒化シリコン膜と、
該窒化シリコン膜に積層して形成された金属膜とを具備
したことを特徴とするものである。(Means for Solving the Problems) A dielectric substrate with a metal film according to the present invention includes a dielectric substrate, a silicon nitride film deposited on the main surface of the dielectric substrate,
It is characterized by comprising a metal film formed in a laminated manner on the silicon nitride film.
（作 用）
本発明の金属膜付き誘電体基板は、誘電体基板と金属膜
との両方に接着力の強い中間層として窒化シリコン膜が
構成されているので、誘電体基板と金属膜の剥れ不良が
なくなる。(Function) The dielectric substrate with a metal film of the present invention has a silicon nitride film as an intermediate layer with strong adhesion between both the dielectric substrate and the metal film, so it is easy to separate the dielectric substrate and the metal film. This eliminates defects.
（実施例）
以下、本発明にかかる金属膜付き誘電体基板の一実施例
につき第１図を参照して説明する。(Example) Hereinafter, an example of a dielectric substrate with a metal film according to the present invention will be described with reference to FIG.
第１図に示す金属膜付き誘電体基板は、石英ガラス基板
１の一重部に窒化シリコン膜（Ｓｔ３Ｎ４膜）２を介し
て、チタニウム層（Ｔｉ層）３と白金層（Ｐｔ層）４と
金属（Ａｕ層）５よりなる（積層）金属膜旦が形成され
たものである。上記Ｓ’１ｓＮ４膜２は減圧ＣＶＤ法に
より一例の膜厚が１０００人に、Ｔｉ層３．Ｐｔ層４は
いずれもスパッタ蒸着法により層厚１５００人に、Ａｕ
層の一部下地層５ａはスパッタ蒸着法により層厚５００
０人に夫々が順次積層して形成され、ざらにこのＡｕ層
５ａ上には電解めっき法によってＡＵ層５ｂが４μｍ厚
に被着されてＡｕ層５が構成されている。The dielectric substrate with a metal film shown in FIG. (Au layer) A (laminated) metal film layer consisting of 5 is formed. The S'1sN4 film 2 was formed by low pressure CVD to a film thickness of 1000 mm, for example, and a Ti layer 3. The Pt layer 4 was formed to a thickness of 1500 mm by sputter deposition, and then Au
A part of the base layer 5a is formed to a thickness of 500 mm by sputter deposition.
The Au layer 5 is formed by sequentially laminating each of the two layers, and an AU layer 5b having a thickness of 4 μm is roughly deposited on the Au layer 5a by electrolytic plating.
以上の構造により、金属膜の剥れ不良は排除された。こ
の理由は、石英ガラスと窒化シリコン膜の接着力及び窒
化シリコン膜と金属膜の接着力が共に強いためと考えら
れる。The above structure eliminates the problem of peeling of the metal film. The reason for this is thought to be that both the adhesive strength between the quartz glass and the silicon nitride film and the adhesive strength between the silicon nitride film and the metal film are strong.
さらに、この構造では、前工程の弗酸処理と蒸着時の加
熱が省略できるという利点も生まれた。Furthermore, this structure has the advantage that the pre-process hydrofluoric acid treatment and heating during vapor deposition can be omitted.
なお、石英ガラス表面と金属膜との間に、中間層として
二酸化シリコン膜を有する構造が考えられる。この構造
においては、石英ガラス基板と二酸化シリコン膜との接
着力は充分改善されたが、しかし、金属膜と二酸化シリ
コン膜（Ｓ ！ ０２膜）との接着力は改善されず、金
属膜の剥れ不良は相変わらず生じた。これににす、窒化
シリコン膜を中間層として用いることに意味があると判
断できる。Note that a structure having a silicon dioxide film as an intermediate layer between the quartz glass surface and the metal film can be considered. In this structure, the adhesion between the quartz glass substrate and the silicon dioxide film was sufficiently improved, but the adhesion between the metal film and the silicon dioxide film (S!02 film) was not improved, and the metal film was easily peeled off. Failures continued to occur. Based on this, it can be concluded that it is meaningful to use a silicon nitride film as an intermediate layer.
なお、石英ガラスを用いた場合には、従来のアルミナ基
板を用いた場合に比べ比誘電率が半減するため中継用基
板の容量を半分にすることができ、例えば、３ＧＨｚ帯
用高周波トランジスタの帯域特性は、従来のものに比べ
て、１．２倍に広帯域化ができるなど、大いに半導体素
子の性能を向上させることができた。Furthermore, when quartz glass is used, the relative dielectric constant is halved compared to when a conventional alumina substrate is used, so the capacity of the relay substrate can be halved. In terms of characteristics, it was possible to greatly improve the performance of semiconductor devices, such as making the band 1.2 times wider than that of conventional devices.
以上、本発明の実施例として、ボンディングワイヤの石
英ガラスから成る中継用基板について説明したが、これ
に限定されるものではなく、超高周波半導体装置の内部
整合回路部品用の金属膜付き誘電体基板にも同様の効果
が１ｑられること、及び他の用途についても本発明の構
造は適用でき同様の効果が期待できることは明らかであ
る。As an example of the present invention, a relay substrate made of quartz glass for bonding wires has been described above, but the present invention is not limited to this, and the dielectric substrate with a metal film for internal matching circuit components of ultra-high frequency semiconductor devices is described above. It is clear that the same effect can be obtained for 1q, and that the structure of the present invention can be applied to other uses and similar effects can be expected.
次に、上記実施例では金属膜として誘電体基板側からＴ
ｉ／Ｐｔ／Ａｕをこの順に積層した膜を用いた場合を例
示したが、これに限らず、他の金属膜、例えばＣｒ／Ａ
ＬＩの積層膜を用いても同様の効果が得られた。Next, in the above embodiment, T is applied as a metal film from the dielectric substrate side.
Although a case in which a film in which i/Pt/Au is laminated in this order is used, the case is not limited to this, and other metal films such as Cr/A
A similar effect was obtained using a laminated film of LI.
（発明の効果）
上述の如く本発明によれば、石英ガラスなどの誘電体基
板と金属膜との間に窒化シリコン膜を介在させることに
より、特別な表面処理を施すことなく金属の接着の信頼
性を高められる金属膜付き誘電体基板が得られる顕著な
効果がある。(Effects of the Invention) As described above, according to the present invention, by interposing a silicon nitride film between a dielectric substrate such as quartz glass and a metal film, reliable metal adhesion can be achieved without any special surface treatment. This has the remarkable effect of providing a dielectric substrate with a metal film that has improved properties.
なお、この発明は誘電体基板の表面に、例えば酸化シリ
コン膜が形成された塁仮に対しても適用でき、有効であ
る。Note that the present invention is also applicable and effective to a base plate in which, for example, a silicon oxide film is formed on the surface of a dielectric substrate.
第１図は本発明にかかる金属膜付き誘電体基板の断面図
である。
１・・・石英ガラス基板 ２・・・ＳＩ３Ｎ４膜１
１・・・（積層）金属膜
代理人 弁理士 大 胡 典 夫
、ＳＤ ： ｃ め、：：（＝） ＡＬ１ノ１ｊ：；旦
：Ｊｌ）錫膜
＠ １ 図FIG. 1 is a sectional view of a dielectric substrate with a metal film according to the present invention. 1... Quartz glass substrate 2... SI3N4 film 1
1... (Laminated) metal film agent Patent attorney Norio Ogo, SD: c め、:: (=) AL1ノ1j:;dan:Jl) Tin film @ 1 Figure
Claims (1)
リコン膜と、該窒化シリコン膜に積層して形成された金
属膜とを具備した金属膜付き誘電体基板。A dielectric substrate with a metal film, comprising a dielectric substrate, a silicon nitride film deposited on a main surface of the dielectric substrate, and a metal film laminated on the silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1010903A JP2839523B2 (en) | 1989-01-19 | 1989-01-19 | Dielectric substrate with metal film for matching circuit formation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1010903A JP2839523B2 (en) | 1989-01-19 | 1989-01-19 | Dielectric substrate with metal film for matching circuit formation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02191349A true JPH02191349A (en) | 1990-07-27 |
| JP2839523B2 JP2839523B2 (en) | 1998-12-16 |
Family
ID=11763256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1010903A Expired - Lifetime JP2839523B2 (en) | 1989-01-19 | 1989-01-19 | Dielectric substrate with metal film for matching circuit formation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2839523B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6350397B1 (en) | 1999-03-10 | 2002-02-26 | Aspen Research Corporation | Optical member with layer having a coating geometry and composition that enhance cleaning properties |
| JP2010154525A (en) * | 2008-12-23 | 2010-07-08 | Internatl Business Mach Corp <Ibm> | Structure, method, and design structure for slow phase velocity (millimeter wave transmission line for slow phase velocity) |
| JP2019070672A (en) * | 2011-02-11 | 2019-05-09 | テラビュー リミテッド | Test system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60133758A (en) * | 1983-12-21 | 1985-07-16 | Seiko Epson Corp | Manufacture of mos type semiconductor device |
-
1989
- 1989-01-19 JP JP1010903A patent/JP2839523B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60133758A (en) * | 1983-12-21 | 1985-07-16 | Seiko Epson Corp | Manufacture of mos type semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6350397B1 (en) | 1999-03-10 | 2002-02-26 | Aspen Research Corporation | Optical member with layer having a coating geometry and composition that enhance cleaning properties |
| JP2010154525A (en) * | 2008-12-23 | 2010-07-08 | Internatl Business Mach Corp <Ibm> | Structure, method, and design structure for slow phase velocity (millimeter wave transmission line for slow phase velocity) |
| JP2019070672A (en) * | 2011-02-11 | 2019-05-09 | テラビュー リミテッド | Test system |
| US11169202B2 (en) | 2011-02-11 | 2021-11-09 | Teraview Limited | Test system |
| US11726136B2 (en) | 2011-02-11 | 2023-08-15 | Teraview Limited | Test system |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2839523B2 (en) | 1998-12-16 |
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