JPH09312457A - Circuit board with capacitor element - Google Patents

Circuit board with capacitor element

Info

Publication number
JPH09312457A
JPH09312457A JP12820096A JP12820096A JPH09312457A JP H09312457 A JPH09312457 A JP H09312457A JP 12820096 A JP12820096 A JP 12820096A JP 12820096 A JP12820096 A JP 12820096A JP H09312457 A JPH09312457 A JP H09312457A
Authority
JP
Japan
Prior art keywords
electrode layer
thin film
layer
lower electrode
capacitive element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12820096A
Other languages
Japanese (ja)
Inventor
Takeshi Oyamada
毅 小山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP12820096A priority Critical patent/JPH09312457A/en
Publication of JPH09312457A publication Critical patent/JPH09312457A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To enable a capacitor element in specific electrostatic capacitance to be formed by a method wherein, within this circuit board made of the surface of a lower part electrode layer and an upper electrode coating at least one side, a resin insulating layer is interposed in the region opposite to the angle part of surface and side of the lower part electrode layer between a dielectric layer and the upper part electrode layer. SOLUTION: Two thin film capacitor elements 3a, 3b are coat-formed on the surface of an insulating substrate 1 while the two thin film capacitor elements 3a, 3b are made of lower electrodes 5 and dielectric layers 6 coat- formed on the surface of the electrodes 5 and at least one side as well as upper part electrodes 7 coating the surface while a resin insulating matter is interposed in the region opposite to the angle part of the upper part and side of the lower part electrode layers 5. In such a constitution, a specific electrostatic capacitance decided by the permittivity of the dielectric layers 6 are formed between the lower electrodes 5 and the upper electrodes 7 so that the capacitor element in a specific electrostatic capacitance may be formed by deciding the permittivity of the dielectric layers 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は携帯電話や衛星通信
等の通信機器に搭載される容量素子付き回路基板に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board with a capacitor mounted on a communication device such as a mobile phone or satellite communication.

【0002】[0002]

【従来の技術】従来、携帯電話や衛星通信等の通信機器
には電気信号の送受信回路を構成する部品の一部に容量
素子付き回路基板が使用されている。
2. Description of the Related Art Conventionally, in a communication device such as a mobile phone or satellite communication, a circuit board with a capacitive element is used as a part of components constituting an electric signal transmitting / receiving circuit.

【0003】かかる容量素子付き回路基板は一般に上面
に所定パターンの回路配線を有する絶縁基板を準備し、
該絶縁基板上にチップ容量素子を載置するとともにその
端子を回路配線に半田等を介し電気的に接続させること
によって形成されている。
For such a circuit board with a capacitive element, an insulating board having a circuit wiring of a predetermined pattern on its upper surface is generally prepared.
It is formed by mounting a chip capacitor on the insulating substrate and electrically connecting its terminals to circuit wiring via solder or the like.

【0004】しかしながら、近時、携帯電話や衛星通信
等の通信機器は小型、軽量化が急激に進み、従来の容量
素子付き回路基板では回路配線がMoーMn法等の厚膜
形成技術により形成されており、各回路配線の幅及び隣
接する回路配線間の間隙が広いこと、チップ容量素子の
形状が大きく全体が大型となっていること等から使用す
ることができず、小型で軽量な新規の容量素子付き回路
基板が要求されるようになってきた。
However, in recent years, communication devices such as mobile phones and satellite communications have been rapidly reduced in size and weight, and in conventional circuit boards with capacitive elements, circuit wiring is formed by a thick film forming technique such as Mo-Mn method. However, it cannot be used because the width of each circuit wiring and the gap between adjacent circuit wiring are wide, and the shape of the chip capacitor is large and the whole is large. The circuit board with the capacitive element has been required.

【0005】そこで新たに絶縁基板上に薄膜形成技術に
より回路配線と容量素子を被着し、該容量素子を回路配
線に電気的に接続することによって容量素子付き回路基
板を形成することが提案されている。
Therefore, it has been proposed to newly form a circuit board with a capacitive element by depositing a circuit wiring and a capacitive element on an insulating substrate by a thin film forming technique and electrically connecting the capacitive element to the circuit wiring. ing.

【0006】かかる容量素子付き回路基板は回路配線及
び容量素子を薄膜形成技術により形成することから回路
配線の線幅及び隣接間隔を狭くし、かつ容量素子の形状
を小さく、全体を小型として小型、軽量化が急激に進む
携帯電話や衛星通信等の通信機器に使用が可能となる。
In such a circuit board with a capacitive element, since the circuit wiring and the capacitive element are formed by a thin film forming technique, the line width of the circuit wiring and the adjacent space are narrowed, and the shape of the capacitive element is small. It can be used for communication devices such as mobile phones and satellite communications, which are rapidly becoming lighter.

【0007】尚、前記容量素子付き回路基板は、その回
路配線が酸化アルミニウム質焼結体等の電気絶縁材料か
ら成る基板上にスパッタリング法や蒸着法等の薄膜形成
技術を採用することによってアルミニウム、タンタル、
タングステン、チタン、クロム等の金属材料を所定厚み
に被着し、次にこれをフォトリソグラフィー技術により
所定パターンに加工することによって形成され、また薄
膜容量素子はまず電気絶縁材料から成る基板上にスパッ
タリング法等の薄膜形成技術によりαータンタル(窒化
タンタル)を所定厚みに被着させて下部電極層を形成
し、次に前記下部電極層の上面及び少なくとも一つの側
面に酸窒化タンタル等から成る誘電物と、チタンー金や
ニクロムー金等の金属材料をスパッタリング法や蒸着法
等の薄膜形成技術により被着させ、最後にこれをエッチ
ング法により所定パターンに加工し、誘電体層及び上部
電極層とすることによって形成されている。
In the circuit board with the capacitive element, the circuit wiring of the circuit board is made of an electrically insulating material such as an aluminum oxide sintered body, and a thin film forming technique such as a sputtering method or a vapor deposition method is applied to the circuit board. tantalum,
It is formed by depositing a metal material such as tungsten, titanium, or chromium to a predetermined thickness, and then processing this into a predetermined pattern by photolithography technology.The thin film capacitive element is first formed by sputtering on a substrate made of an electrically insulating material. A lower electrode layer is formed by depositing α-tantalum (tantalum nitride) to a predetermined thickness by a thin film forming technique such as a method, and then a dielectric material made of tantalum oxynitride or the like is formed on the upper surface and at least one side surface of the lower electrode layer. And a metal material such as titanium-gold or nichrome-gold by a thin film forming technique such as a sputtering method or a vapor deposition method, and finally, this is processed into a predetermined pattern by an etching method to form a dielectric layer and an upper electrode layer. Is formed by.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、この従
来の容量素子付き回路基板においては、下部電極層の上
面及び少なくとも一つの側面に誘電物をスパッタリング
法等の薄膜形成技術により被着させる際、下部電極層の
上面と側面との角部に誘電物を所定厚みに被着させるこ
とができず、その結果、上部電極層と下部電極層とが電
気的に短絡し、容量素子としての機能の発揮させること
ができないという欠点を誘発した。
However, in this conventional circuit board with a capacitive element, when the dielectric is deposited on the upper surface and at least one side surface of the lower electrode layer by a thin film forming technique such as sputtering, Dielectrics cannot be applied to the corners of the upper and side surfaces of the electrode layer to a predetermined thickness, and as a result, the upper electrode layer and the lower electrode layer are electrically short-circuited, and the function as a capacitive element is exerted. Induced the drawback of not being able to.

【0009】[0009]

【課題を解決するための手段】本発明は上記欠点に鑑み
案出されたもので、その目的は所定の静電容量値の容量
素子が形成されて成る小型、軽量の容量素子付き回路基
板を提供することにある。
The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to provide a small-sized and lightweight circuit board with a capacitive element formed by a capacitive element having a predetermined capacitance value. To provide.

【0010】本発明は、絶縁基板上に薄膜回路配線と薄
膜容量素子を形成して成る容量素子付き回路基板であっ
て、前記薄膜容量素子は下部電極層と、該下部電極層の
上面及び少なくとも一つの側面に被着された誘電体層
と、該誘電体層の表面に被着された上部電極層とから成
り、且つ誘電体層と上部電極層との間で、下部電極層の
上面と側面との角部に対向する領域に樹脂絶縁物が介在
されていることを特徴とするものである。
The present invention is a circuit board with a capacitive element formed by forming a thin film circuit wiring and a thin film capacitive element on an insulating substrate, wherein the thin film capacitive element has a lower electrode layer, an upper surface of the lower electrode layer, and at least a lower electrode layer. A dielectric layer deposited on one side surface and an upper electrode layer deposited on the surface of the dielectric layer, and between the dielectric layer and the upper electrode layer, an upper surface of the lower electrode layer; It is characterized in that a resin insulator is interposed in a region facing a corner with a side face.

【0011】本発明の容量素子付き回路基板によれば、
絶縁基板上に薄膜形成技術を採用することによって回路
配線及び容量素子を形成したことから回路配線の線幅及
び隣接間隔を狭くし、かつ容量素子の形状を小さく、全
体を小型として小型、軽量化が急激に進む携帯電話等の
通信機器に搭載が可能となる。
According to the circuit board with a capacitive element of the present invention,
Since the circuit wiring and the capacitive element are formed by adopting the thin film forming technology on the insulating substrate, the line width of the circuit wiring and the adjacent space are narrowed, and the shape of the capacitive element is small. It can be installed in communication devices such as mobile phones, which are rapidly advancing.

【0012】また本発明の容量素子付き回路基板によれ
ば、絶縁基板上に形成される薄膜容量素子の誘電体層と
上部電極層との間で、下部電極層の上面と側面との角部
に対向する領域に樹脂絶縁物を介在させたことから下部
電極層の上面及び少なくとも一つの側面に誘電物をスパ
ッタリング法等の薄膜形成技術により被着させる際、下
部電極層の上面と側面との角部に誘電物が所定厚みに被
着さず、上部電極層と下部電極層とが電気的に短絡しよ
うとしてもその短絡は樹脂絶縁物によって有効に阻止さ
れ、その結果、薄膜容量素子に容量素子としての所定の
機能を発揮させることが可能となる。
Further, according to the circuit board with a capacitive element of the present invention, the corner portion between the upper surface and the side surface of the lower electrode layer is formed between the dielectric layer and the upper electrode layer of the thin film capacitive element formed on the insulating substrate. Since the resin insulating material is interposed in the region facing the upper surface of the lower electrode layer, when the dielectric material is deposited on the upper surface and at least one side surface of the lower electrode layer by a thin film forming technique such as sputtering, Even if the upper electrode layer and the lower electrode layer are electrically short-circuited because the dielectric material does not adhere to the corners to a predetermined thickness, the short circuit is effectively prevented by the resin insulator, and as a result, the capacitance of the thin film capacitive element is reduced. It becomes possible to exhibit a predetermined function as an element.

【0013】更に前記薄膜容量素子の誘電体層と上部電
極層との間に介在される樹脂絶縁物は低誘電率であるこ
とから、樹脂絶縁物によって薄膜容量素子の静電容量値
が大きくばらつくことはなく、薄膜容量素子の静電容量
値を所定の値となすことができる。
Furthermore, since the resin insulating material interposed between the dielectric layer and the upper electrode layer of the thin film capacitive element has a low dielectric constant, the capacitance value of the thin film capacitive element greatly varies due to the resin insulating material. Therefore, the capacitance value of the thin film capacitive element can be set to a predetermined value.

【0014】[0014]

【発明の実施の形態】次に、本発明を添付図面に基づき
詳細に説明する。図1及び図2は本発明の容量素子付き
回路基板の一実施例を示し、1は絶縁基板、2は薄膜回
路配線、3a、3bは薄膜容量素子である。
Next, the present invention will be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a circuit board with a capacitance element of the present invention, 1 is an insulating substrate, 2 is thin film circuit wiring, and 3a and 3b are thin film capacitance elements.

【0015】前記絶縁基板1は酸化アルミニウム質焼結
体、ムライト質焼結体、炭化珪素質焼結体、窒化アルミ
ニウム質焼結体、ガラスセラミックス焼結体等の電気絶
縁材料から成り、例えば、酸化アルミニウム質焼結体か
ら成る場合には、酸化アルミニウム、酸化珪素、酸化マ
グネシウム、酸化カルシウム等の原料粉末に適当な有機
溶剤、溶媒を添加混合して泥漿状となすとともにこれを
従来周知のドクターブレード法やカレンダーロール法等
によりシート状に成形してセラミックグリーンシート
(セラミック生シート)を得、しかる後、前記セラミッ
クグリーンシートに適当な打ち抜き加工を施し所定形状
となすとともに約1600℃の温度で焼成することによ
って製作される。
The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, and a glass ceramic sintered body. In the case of using an aluminum oxide sintered body, an appropriate organic solvent or solvent is added to and mixed with a raw material powder of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide or the like to form a sludge, and this is well-known to doctors. A ceramic green sheet (ceramic green sheet) is obtained by forming into a sheet shape by a blade method or a calendar roll method, and then the ceramic green sheet is subjected to an appropriate punching process to obtain a predetermined shape and at a temperature of about 1600 ° C. It is manufactured by firing.

【0016】前記絶縁基板1は薄膜回路配線2及び薄膜
容量素子3a、3b等を支持する支持部材として作用
し、その上面に所定パターンの薄膜回路配線2と所定静
電容量値の2つの薄膜容量素子3a、3bが被着形成さ
れている。
The insulating substrate 1 acts as a supporting member for supporting the thin film circuit wiring 2, the thin film capacitive elements 3a and 3b, and the like, and the thin film circuit wiring 2 having a predetermined pattern and two thin film capacitors having a predetermined electrostatic capacitance value on the upper surface thereof. The elements 3a and 3b are adhered and formed.

【0017】前記絶縁基板1の上面に被着形成されてい
る薄膜回路配線2は薄膜容量素子3a、3bを絶縁基板
1の上面に実装されている他の電子部品、例えば、半導
体素子4等に接続する、或いは薄膜容量素子3a、3b
や半導体素子4を外部の電気回路に電気的に接続する作
用を為す。
The thin film circuit wiring 2 adhered and formed on the upper surface of the insulating substrate 1 is attached to the other electronic parts such as the semiconductor element 4 on which the thin film capacitor elements 3a and 3b are mounted on the upper surface of the insulating substrate 1. Connect, or thin film capacitive elements 3a, 3b
Also, it serves to electrically connect the semiconductor element 4 to an external electric circuit.

【0018】尚、前記薄膜回路配線2は、例えばチタ
ン、クロム、ニッケル・クロム合金等から成る密着層
と、ニッケル、パラジウム、白金等から成るバリア層
と、金、銅等から成る主導体層の3層構造を有してお
り、絶縁基体1の上面に上記各金属を順次、イオンプレ
ーティング法やスパッタリング法、メッキ法、蒸着法等
の薄膜形成技術により層着し、しかる後、これら層着し
た各層をフォトリソグラフィ技術により所定パターンに
加工することによって絶縁基板1上に所定パターンに被
着形成される。
The thin film circuit wiring 2 is composed of, for example, an adhesion layer made of titanium, chromium, nickel-chromium alloy, etc., a barrier layer made of nickel, palladium, platinum, etc., and a main conductor layer made of gold, copper, etc. It has a three-layer structure, and each of the above metals is sequentially layered on the upper surface of the insulating substrate 1 by a thin film forming technique such as an ion plating method, a sputtering method, a plating method, or a vapor deposition method. The respective layers are processed into a predetermined pattern by a photolithography technique to be formed in a predetermined pattern on the insulating substrate 1.

【0019】また前記薄膜回路配線2は絶縁基板1上に
薄膜形成技術を採用することによって形成されることか
ら薄膜回路配線2の線幅及び隣接間隔を極めて狭いもの
として絶縁基板1に高密度に被着形成することが可能と
なり、その結果、薄膜回路配線2が被着形成される絶縁
基板1を小型化させることができる。
Further, since the thin film circuit wiring 2 is formed on the insulating substrate 1 by adopting a thin film forming technique, the thin film circuit wiring 2 can be formed on the insulating substrate 1 with a high density by setting the line width and the adjacent space to be extremely narrow. The insulating substrate 1 on which the thin film circuit wiring 2 is adhered and formed can be miniaturized.

【0020】更に前記絶縁基板1の上面には2つの薄膜
容量素子3a、3bが被着形成されており、該2つの薄
膜容量素子3a、3bは図2に示すように例えば、αー
タンタル(窒化タンタル)から成る下部電極層5と、該
下部電極層5の上面及び少なくとも一つの側面との被着
形成された酸窒化タンタル等から成る誘電体層6と、該
誘電体層6の表面に被着される上部電極層7とから成
り、下部電極層5と上部電極層7との間に誘電体層6の
比誘電率によって決定される一定の静電容量が形成され
るようになっている。
Further, two thin film capacitive elements 3a and 3b are adhered and formed on the upper surface of the insulating substrate 1, and the two thin film capacitive elements 3a and 3b are, for example, as shown in FIG. A lower electrode layer 5 made of tantalum), a dielectric layer 6 made of tantalum oxynitride or the like deposited on the upper surface and at least one side surface of the lower electrode layer 5, and a surface of the dielectric layer 6 covered. The upper electrode layer 7 and the upper electrode layer 7 are attached to each other, and a constant capacitance determined by the relative dielectric constant of the dielectric layer 6 is formed between the lower electrode layer 5 and the upper electrode layer 7. .

【0021】前記2つの薄膜容量素子3a、3bはその
下部電極層5が例えば、薄膜回路配線2に接続され、上
部電極層7が半導体素子4の電極や他の薄膜回路配線2
にボンディングワイヤ8を介して接続され、これによっ
て所定の電気回路に接続されるようになっている。
The lower electrode layers 5 of the two thin film capacitive elements 3a and 3b are connected to, for example, the thin film circuit wiring 2, and the upper electrode layer 7 is an electrode of the semiconductor element 4 or another thin film circuit wiring 2.
To a predetermined electric circuit.

【0022】前記2つの薄膜容量素子3a、3bの絶縁
基板1上面への被着形成は、まず絶縁基板1上に下部電
極層5を被着形成する。この下部電極層5は例えば、α
ータンタル(窒化タンタル)から成り、該αータンタル
を絶縁基板1上にスパッタリング法やイオンプレーティ
ング法等の薄膜形成技術を採用することによって所定厚
み(250オングストローム〜10000オングストロ
ーム)に被着させ、しかる後、これをフォトリソグラフ
ィ技術により所定パターンに加工することによって絶縁
基板1上に形成される。
To deposit the two thin film capacitive elements 3a and 3b on the upper surface of the insulating substrate 1, first, the lower electrode layer 5 is deposited on the insulating substrate 1. This lower electrode layer 5 is formed of, for example, α
-Tantalum (tantalum nitride), the α-tantalum is deposited on the insulating substrate 1 to a predetermined thickness (250 angstroms to 10000 angstroms) by adopting a thin film forming technique such as a sputtering method or an ion plating method. This is formed on the insulating substrate 1 by processing it into a predetermined pattern by a photolithography technique.

【0023】尚、前記αータンタルから成る下部電極層
5はその厚みが250オングストローム未満であると下
部電極層5を絶縁基板1に強固に接合させることが困難
となり、また10000オングストロームを越えると下
部電極層5を絶縁基板1上に被着させる際に下部電極層
5内部に大きな応力が内在し、該内在応力によって下部
電極層5が絶縁基板1より剥離し易くなる傾向にある。
従って、前記αータンタルから成る下部電極層5はその
厚みを250オングストローム〜10000オングスト
ロームの範囲としておくことが好ましい。
If the thickness of the lower electrode layer 5 made of α-tantalum is less than 250 Å, it will be difficult to firmly bond the lower electrode layer 5 to the insulating substrate 1, and if it exceeds 10,000 Å, the lower electrode layer 5 will be difficult to bond. When the layer 5 is deposited on the insulating substrate 1, a large stress is internally present inside the lower electrode layer 5, and the internal stress tends to cause the lower electrode layer 5 to peel off from the insulating substrate 1.
Therefore, the lower electrode layer 5 made of α-tantalum preferably has a thickness in the range of 250 Å to 10000 Å.

【0024】次に、前記下部電極層5の上面及び少なく
とも一つの側面に例えば、酸窒化タンタル等から成る誘
電物をスパッタリング等の薄膜形成技術により所定厚み
に被着させるとともにフォトリソグラフィー技術により
所定パターンに加工して誘電体層6を形成する。この誘
電体層6は下部電極層5と上部電極層7との間に所定の
静電容量を形成する作用を為し、下部電極層5の上面及
び少なくとも一つの側面に2000オングストローム〜
10000オングストロームの厚みに被着される。
Next, a dielectric made of, for example, tantalum oxynitride is deposited to a predetermined thickness on the upper surface and at least one side surface of the lower electrode layer 5 by a thin film forming technique such as sputtering, and a predetermined pattern is formed by a photolithography technique. Then, the dielectric layer 6 is formed. The dielectric layer 6 has a function of forming a predetermined capacitance between the lower electrode layer 5 and the upper electrode layer 7, and has a thickness of 2000 angstroms or more on the upper surface and at least one side surface of the lower electrode layer 5.
It is deposited to a thickness of 10,000 Angstroms.

【0025】そして最後に、前記誘電体層6の表面に上
部電極層7を被着し、上部電極層7と前述の下部電極層
5との間に誘電体層6を位置させることによって所定の
静電容量値を有する薄膜容量素子3a、3bが絶縁基板
1上の所定位置に被着形成されることとなる。
Finally, by depositing an upper electrode layer 7 on the surface of the dielectric layer 6 and arranging the dielectric layer 6 between the upper electrode layer 7 and the lower electrode layer 5 described above, The thin film capacitive elements 3a and 3b having a capacitance value are deposited and formed on the insulating substrate 1 at predetermined positions.

【0026】前記上部電極層7は例えば、チタン層と金
層、ニクロム層と金層等の金属材料を2層に積層したも
ので形成され、従来周知の蒸着法やスパッタリング法等
の薄膜形成技術及びフォトリソグラフィー技術を採用す
ることによって誘電体層6の表面に被着される。
The upper electrode layer 7 is formed, for example, by laminating two layers of metal materials such as a titanium layer and a gold layer, a nichrome layer and a gold layer, and a thin film forming technique such as a conventionally known vapor deposition method or sputtering method. And on the surface of the dielectric layer 6 by applying photolithography technique.

【0027】尚、前記上部電極層7は例えば、チタン層
と金層の2層で形成する場合、チタン層は上部電極層7
を誘電体層6上に強固に被着させる作用を為し、その厚
みが250オングストローム未満であると上部電極層7
を誘電体層6上に強固に被着させるのが困難となり、ま
た10000オングストロームを越えると誘電体層6上
に上部電極層7を被着させる際、上部電極層7の内部に
大きな応力が内在し、該内在応力によって薄膜容量素子
3a、3bの絶縁特性、耐電圧特性が劣化する傾向にあ
る。従って、前記上部電極層7はその厚みを250オン
グストローム乃至10000オングストロームの範囲と
しておくことが好ましい。
When the upper electrode layer 7 is formed of, for example, a titanium layer and a gold layer, the titanium layer is the upper electrode layer 7.
Is firmly adhered onto the dielectric layer 6, and if the thickness is less than 250 Å, the upper electrode layer 7
Is difficult to adhere firmly onto the dielectric layer 6, and if it exceeds 10,000 angstroms, when the upper electrode layer 7 is adhered onto the dielectric layer 6, a large stress is internally generated in the upper electrode layer 7. However, the insulation stress and the withstand voltage characteristics of the thin film capacitive elements 3a and 3b tend to deteriorate due to the internal stress. Therefore, the thickness of the upper electrode layer 7 is preferably set in the range of 250 Å to 10000 Å.

【0028】また前記上部電極層7の金層は、上部電極
層7の主導体層として作用し、その厚みが0.3μm未
満であると後述する上部電極層7と薄膜回路配線2とを
ボンディングワイヤ8を介して接続する際、上部電極層
7とボンディングワイヤ8との電気的接続の信頼性が低
くなる傾向にあり、また5μmを越えると金層を形成す
る際に内部に大きな応力が内在し、該内在応力によって
薄膜容量素子3a、3bの絶縁特性、耐電圧特性が劣化
する傾向にある。従って、前記金層はその厚みを0.3
μm乃至5μmの範囲としておくことが好ましい。
The gold layer of the upper electrode layer 7 acts as a main conductor layer of the upper electrode layer 7, and if the thickness is less than 0.3 μm, the upper electrode layer 7 and the thin film circuit wiring 2 which will be described later are bonded. When connecting via the wire 8, the reliability of the electrical connection between the upper electrode layer 7 and the bonding wire 8 tends to be low, and when the thickness exceeds 5 μm, a large stress is internally generated when the gold layer is formed. However, the insulation stress and the withstand voltage characteristics of the thin film capacitive elements 3a and 3b tend to deteriorate due to the internal stress. Therefore, the gold layer has a thickness of 0.3.
It is preferably set in the range of μm to 5 μm.

【0029】前記薄膜容量素子3a、3bはそれを構成
する下部電極層5、誘電体層6及び上部電極層7のいず
れもが薄膜形成技術より形成されていることから全体の
形状が小さく、小型、軽量化が急激に進む携帯電話等の
通信機器に搭載が可能となる。
Since the lower electrode layer 5, the dielectric layer 6 and the upper electrode layer 7 constituting the thin film capacitive elements 3a and 3b are all formed by the thin film forming technique, the overall shape is small and small. It can be installed in communication devices such as mobile phones, which are rapidly becoming lighter.

【0030】上述した薄膜容量素子3a、3bはまた図
2に示す如く、その各々の誘電体層6と上部電極層7と
の間で、下部電極層5の上面と側面との角部に対向する
領域に低誘電率の樹脂絶縁物9が介在しており、該樹脂
絶縁物9によって下部電極層5の上面及び少なくとも一
つの側面に誘電物をスパッタリング法等の薄膜形成技術
により被着させ誘電体層6を形成する際、下部電極層5
の上面と側面との角部に誘電物が所定厚みに被着せず、
上部電極層7と下部電極層5とが電気的に短絡しようと
してもその短絡が有効に阻止され、その結果、薄膜容量
素子3a、3bの各々に容量素子としての所定の機能を
発揮させることができる。
As shown in FIG. 2, each of the above-mentioned thin film capacitive elements 3a and 3b faces the corner between the upper surface and the side surface of the lower electrode layer 5 between each dielectric layer 6 and the upper electrode layer 7. A low-dielectric-constant resin insulator 9 is interposed in the region to be covered, and the dielectric substance is applied to the upper surface and at least one side surface of the lower electrode layer 5 by a thin film forming technique such as a sputtering method. When forming the body layer 6, the lower electrode layer 5
Dielectric material does not adhere to the corners of the upper and side surfaces of the
Even if the upper electrode layer 7 and the lower electrode layer 5 are electrically short-circuited, the short circuit is effectively prevented, and as a result, each of the thin film capacitive elements 3a and 3b can exhibit a predetermined function as a capacitive element. it can.

【0031】更に前記樹脂絶縁物9はその比誘電率が低
く、そのため薄膜容量素子3a、3bの静電容量値が前
記樹脂絶縁物の比誘電率によって大きくばらつくことは
なく、薄膜容量素子3a、3bの静電容量値を所定の値
となすことが可能となる。
Further, since the resin insulator 9 has a low relative permittivity, the capacitance values of the thin film capacitive elements 3a and 3b do not greatly vary depending on the relative permittivity of the resin insulating material, and the thin film capacitive element 3a, It is possible to set the capacitance value of 3b to a predetermined value.

【0032】前記樹脂絶縁物9としては例えば、ふっ素
樹脂、ポリフェニレンエーテル樹脂等の比誘電率が3
(室温1MHz)以下の電気絶縁性の有機樹脂が好適に
使用され、ふっ素樹脂等の樹脂前駆体を下部電極層5の
上面と側面との角部に対向する領域に塗布し、しかる
後、これを所定温度で熱硬化させることによって誘電体
層6と上部電極層7との間に形成される。
As the resin insulator 9, for example, fluorine resin, polyphenylene ether resin or the like having a relative dielectric constant of 3 is used.
An electrically insulating organic resin having a room temperature (1 MHz) or less is preferably used, and a resin precursor such as a fluorine resin is applied to a region facing the corners of the upper surface and the side surface of the lower electrode layer 5, and thereafter, Is cured between the dielectric layer 6 and the upper electrode layer 7 by heat curing at a predetermined temperature.

【0033】かくして本発明の容量素子付き回路基板に
よれば、絶縁基板1上に設けた薄膜回路配線2に半導体
素子4やその他の抵抗器を搭載接続するとともに薄膜容
量素子3a、3bの下部電極層5及び上部電極層7を所
定の薄膜回路配線2や半導体素子5の電極に、直接、或
いはボンディングワイヤ8を介して接続すれば、携帯電
話や衛星通信等の通信機器に実装される電気回路基板と
なる。
Thus, according to the circuit board with a capacitive element of the present invention, the semiconductor element 4 and other resistors are mounted and connected to the thin film circuit wiring 2 provided on the insulating substrate 1, and the lower electrodes of the thin film capacitive elements 3a and 3b are connected. If the layer 5 and the upper electrode layer 7 are connected to a predetermined thin film circuit wiring 2 or an electrode of the semiconductor element 5 directly or via a bonding wire 8, an electric circuit mounted in a communication device such as a mobile phone or satellite communication. It becomes the substrate.

【0034】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば上述の実施例では絶縁基
板1の上面に2つの薄膜容量素子3a、3bを形成した
がこれを3個以上設けてもよく、また各薄膜容量素子3
a、3bの下部電極層5、誘電体層6及び上部電極層7
を他の材料で形成してもよく、更に各薄膜容量素子3
a、3bの下部電極層5を薄膜回路配線2と同じ材料で
形成してもよい。
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, in the above-mentioned embodiments, the upper surface of the insulating substrate 1 can be changed. Although two thin film capacitive elements 3a and 3b are formed in the above, three or more thin film capacitive elements 3a and 3b may be provided.
a, 3b lower electrode layer 5, dielectric layer 6 and upper electrode layer 7
May be made of another material, and each thin film capacitive element 3
The lower electrode layers 5 of a and 3b may be formed of the same material as the thin film circuit wiring 2.

【0035】[0035]

【発明の効果】本発明の容量素子付き回路基板によれ
ば、絶縁基板上に薄膜形成技術を採用することによって
回路配線及び容量素子を形成したことから回路配線の線
幅及び隣接間隔を狭くし、かつ容量素子の形状を小さ
く、全体を小型として小型、軽量化が急激に進む携帯電
話等の通信機器に搭載が可能となる。
According to the circuit board with a capacitive element of the present invention, since the circuit wiring and the capacitive element are formed by adopting the thin film forming technique on the insulating substrate, the line width and the adjacent space of the circuit wiring can be reduced. In addition, the shape of the capacitive element is small, and the entire device is small, so that it can be mounted on communication devices such as mobile phones, which are rapidly becoming smaller and lighter.

【0036】また本発明の容量素子付き回路基板によれ
ば、絶縁基板上に形成される薄膜容量素子の誘電体層と
上部電極層との間で、下部電極層の上面と側面との角部
に対向する領域に樹脂絶縁物を介在させたことから下部
電極層の上面及び少なくとも一つの側面に誘電物をスパ
ッタリング法等の薄膜形成技術により被着させる際、下
部電極層の上面と側面との角部に誘電物が所定厚みに被
着せず、上部電極層と下部電極層とが電気的に短絡しよ
うとしてもその短絡は樹脂絶縁物によって有効に阻止さ
れ、その結果、薄膜容量素子に容量素子としての所定の
機能を発揮させることが可能となる。
Further, according to the circuit board with a capacitive element of the present invention, the corner portion between the upper surface and the side surface of the lower electrode layer is formed between the dielectric layer and the upper electrode layer of the thin film capacitive element formed on the insulating substrate. Since the resin insulating material is interposed in the region facing the upper surface of the lower electrode layer, when the dielectric material is deposited on the upper surface and at least one side surface of the lower electrode layer by a thin film forming technique such as sputtering, Even if the upper electrode layer and the lower electrode layer are electrically short-circuited even if the corner portion is not covered with the dielectric substance with a predetermined thickness, the short circuit is effectively prevented by the resin insulator, and as a result, the thin-film capacitance element becomes a capacitive element. It is possible to exert a predetermined function as.

【0037】更に前記薄膜容量素子の誘電体層と上部電
極層との間に介在される樹脂絶縁物は低誘電率であるこ
とから、樹脂絶縁物によって薄膜容量素子の静電容量値
が大きくばらつくことはなく、薄膜容量素子の静電容量
値を所定の値となすことができる。
Furthermore, since the resin insulating material interposed between the dielectric layer and the upper electrode layer of the thin film capacitive element has a low dielectric constant, the capacitance value of the thin film capacitive element greatly varies due to the resin insulating material. Therefore, the capacitance value of the thin film capacitive element can be set to a predetermined value.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の容量素子付き回路基板の一実施例を示
す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a circuit board with a capacitor according to the present invention.

【図2】図1に示す薄膜容量素子を説明するための拡大
断面図である。
FIG. 2 is an enlarged cross-sectional view for explaining the thin film capacitive element shown in FIG.

【符号の説明】[Explanation of symbols]

1・・・・・・絶縁基板 2・・・・・・薄膜回路配線 3a、3b・・薄膜容量素子 5・・・・・・下部電極層 6・・・・・・酸窒化タンタル層 7・・・・・・上部電極層 9・・・・・・樹脂絶縁物 1 ... Insulating substrate 2 ... Thin film circuit wiring 3a, 3b ... Thin film capacitive element 5 ... Lower electrode layer 6 ... Tantalum oxynitride layer 7 ...・ ・ ・ ・ ・ Upper electrode layer 9 ・ ・ ・ Resin insulation

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁基板上に薄膜回路配線と薄膜容量素子
を形成して成る容量素子付き回路基板であって、前記薄
膜容量素子は下部電極層と、該下部電極層の上面及び少
なくとも一つの側面に被着された誘電体層と、該誘電体
層の表面に被着された上部電極層とから成り、且つ誘電
体層と上部電極層との間で、下部電極層の上面と側面と
の角部に対向する領域に低誘電率の樹脂絶縁物が介在さ
れていることを特徴とする容量素子付き回路基板。
1. A circuit board with a capacitive element, comprising a thin film circuit wiring and a thin film capacitive element formed on an insulating substrate, wherein the thin film capacitive element includes a lower electrode layer, an upper surface of the lower electrode layer, and at least one of the lower electrode layers. A dielectric layer deposited on the side surface and an upper electrode layer deposited on the surface of the dielectric layer, and between the dielectric layer and the upper electrode layer, the upper surface and the side surface of the lower electrode layer. A circuit board with a capacitor, wherein a resin insulator having a low dielectric constant is interposed in a region facing a corner portion of the.
JP12820096A 1996-05-23 1996-05-23 Circuit board with capacitor element Pending JPH09312457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12820096A JPH09312457A (en) 1996-05-23 1996-05-23 Circuit board with capacitor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12820096A JPH09312457A (en) 1996-05-23 1996-05-23 Circuit board with capacitor element

Publications (1)

Publication Number Publication Date
JPH09312457A true JPH09312457A (en) 1997-12-02

Family

ID=14978948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12820096A Pending JPH09312457A (en) 1996-05-23 1996-05-23 Circuit board with capacitor element

Country Status (1)

Country Link
JP (1) JPH09312457A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1170797A2 (en) * 2000-07-04 2002-01-09 Alps Electric Co., Ltd. Thin-film capacitor element and electronic circuit board on which thin-film capacitor element is formed
US7652349B2 (en) 2005-11-11 2010-01-26 Tdk Corporation Thin-film device and method of manufacturing same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1170797A2 (en) * 2000-07-04 2002-01-09 Alps Electric Co., Ltd. Thin-film capacitor element and electronic circuit board on which thin-film capacitor element is formed
EP1170797A3 (en) * 2000-07-04 2005-05-25 Alps Electric Co., Ltd. Thin-film capacitor element and electronic circuit board on which thin-film capacitor element is formed
US7652349B2 (en) 2005-11-11 2010-01-26 Tdk Corporation Thin-film device and method of manufacturing same

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