JPH07161734A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To prevent generation of recess around a gate, and easily eliminate a protective film for annealing after annealing, by performing annealing after an insulating film turning to a protective film for annealing and a high thermal conduction film are formed in order on a semiconductor layer and a gate electrode. CONSTITUTION:A semiconductor layer 8 having a specified conductivity type is formed by selectively implanting impurities in the surface of a compound semiconductor substrate 1. A gate electrode 2 composed of high melting point metal is formed on a specified region of the semiconductor layer 8. A high concentration semiconductor region 9 having the same conductivity type as the semiconductor layer 8 is formed on both side parts of the gate electrode 2 of the semiconductor substrate 1 by impurity implantation. Insulating films 3, 4 turning to protective films for annealing and a high thermal conduction film 5 composed of high melting point metal or its compound are deposited in order on the semiconductor layers 8, 9 and the gate electrode 2. By using the insulating films 3, 4 and the high thermal conduction film 5 as the protective films for annealing, an annealing process is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a method for forming a protective film for annealing in a self-aligned gate field effect transistor.

[0002]

2. Description of the Related Art In a conventional SAGFET (self-alignment gate FET) process, after forming a refractory metal gate such as WSi, ion implantation is performed using this as a mask to perform activation annealing. In the process, activation annealing after ion implantation needs to be performed at a high temperature of 800 ° C. or higher. However, in general, compound semiconductors often contain high vapor pressure constituent elements, and when such a substrate is exposed to high temperatures, some of the constituent atoms of the substrate dissociate from the substrate surface. Then, vacant points are generated. Therefore, at such a high temperature, As atoms having a high equilibrium vapor pressure dissociate from the surface and deteriorate the characteristics of the ion-implanted layer.

In order to prevent this, a capless annealing method is used to prevent the dissociation of atoms from the substrate by applying a pressure comparable to the vapor pressure of the constituent elements of the substrate to the surface of the substrate during annealing. For example, when a GaAs substrate is used, As produced by thermal decomposition of AsH3 gas
The method used as a pressure source is widely used. As a device used for these annealing, a device in which a substrate is placed in a quartz tube and is heated by an electric heater or an infrared lamp attached to the periphery of the quartz tube is widely used. Introduce gas such as AsH3,
Annealing is performed in the required atmosphere. Further, in the case where the infrared lamp is used as described above, rapid heating, which is called lamp annealing, is possible, so that diffusion of implanted atoms and atoms constituting the substrate can be suppressed, activation of the implanted atoms can be highly activated, and the like.

FIG. 10 is a diagram showing an example of a basic SAGFET process flow in a capless annealing system using a GaAs substrate. In the figure, 1 is GaAs
A substrate 2 is a refractory metal gate, 8 is an n implantation region (hereinafter also referred to as an n layer) forming a channel portion, 9 is an n ⁺ implantation region (hereinafter also referred to as an n ⁺ layer) as a drain and a source region. ), 11 is a resist, 12 is a SiO2 film, 13
Is an ohmic electrode.

Next, the manufacturing process will be described. First,
The SiO2 film 12 is formed on the GaAs semi-insulating substrate 1,
An n-type dopant is selectively implanted using the resist 11 as a mask. Si is usually used as the n-type dopant. After removing the resist 11, the SiO 2 film 12 is directly used as an annealing protection film for activation annealing, and n
The implantation region 8 is formed (FIG. 10 (a)). Next, the above Si
The O2 film 12 is removed, and the refractory metal gate 2 is formed by sputtering or the like, and by etching such as RIE using a fluorine-based gas (FIG. 10 (b)). Next, an n-type dopant is implanted using the resist 11 and the refractory metal gate 2 as a mask (FIG. 10 (c)). After removing the resist 11, activation annealing is performed to
⁺ Layer 9 is formed. By this process method, the n ⁺ layer 9 as the source and drain regions can be formed in self-alignment with the gate 2. Finally, an ohmic electrode 13 is formed on the source and drain regions (n ⁺ layer) 9,
Complete T.

As the annealing after the formation of the refractory metal gate 2 described above, capless annealing is generally used as shown in the process flow of FIG. However, in the capless annealing, since the heat treatment is performed in a state where the substrate surface is not covered with the protective film, there is an advantage that problems such as reaction and stress generation at the interface between the substrate and the protective film do not occur. On the other hand, since the substrate surface is in direct contact with the outside air, surface contamination is likely to occur and it is difficult to ensure reproducibility and uniformity of the injection layer. In addition to the problem that AsH3 is highly toxic, the problem is that the quartz tube of the annealing device becomes cloudy, and it is particularly difficult to use it for lamp annealing.

Therefore, as another annealing method, a protective film of SiN, SiO2 or the like is formed on the surface of the substrate before performing the annealing treatment, whereby dissociation of atoms having a high vapor pressure constituting the substrate can be prevented. There is a cap annealing method. It is known that when this method is used, the activation rate becomes high even in the carrier profile of the injection layer after annealing, and the diffusion of the dopant is suppressed. For the above reasons, by applying the cap annealing at the time of manufacturing the SAGFET, the ion implantation characteristics and the F
It is considered that ET characteristics can be improved.

FIG. 11 shows SAG using cap annealing.
3 shows a method of manufacturing an FET. In the figure, the same reference numerals as those in FIG. 10 indicate the same or corresponding portions, and 14 is a protective film for annealing, which is generally SiO2, SiON,
A SiN film is used.

Next, the manufacturing process will be described. First,
By the same processing as the steps shown in FIGS. 10 (a) and 10 (b), Ga
After the n-implanted region 8 and the refractory metal gate 2 are formed on the As semi-insulating substrate 1 (FIGS. 11A and 11B), the resist 11 and the refractory metal gate 2 are used as masks for n-type dopant. After implanting (FIG. 11C) and removing the resist 11, a protective film 14 is formed and activation annealing is performed to form an n ⁺ layer 9 (FIG. 11D). Finally, ohmic electrodes 13 are formed on the source and drain regions,
Complete the FET.

[0010]

However, when a SiO2, SiON, or SiN film is used as the annealing protection film, there is a problem that a depression is formed on the GaAs surface around the gate. The cause of this is not clear, but it is considered that abnormal dissociation of As due to stress concentration at the gate end occurs, and in the case of lamp annealing, local heating around WSi is the cause. 9 (a) shows that after forming a WSi gate on the surface of a GaAs substrate, SiO 2 is formed.
2 is a SEM photograph of a cross section of a substrate when lamp annealing was performed at 930 ° C. for 5 seconds with the 2 film as a protective film. It can be seen that the surface of the GaAs substrate around the WSi gate has a depression of 1000 angstroms or more. This recess cuts the channel layer along the gate, which is a fatal problem in the operation of the FET. Further, when the SiN film is used as the protective film for annealing, there is a problem that the film is likely to peel off due to the large stress and it is more difficult to remove the film than the SiO film.

By the way, Japanese Patent Laid-Open No. 4-359435 discloses a method of manufacturing a Schottky gate field effect transistor using GaAs, in which an annealing treatment is performed using a WSiN film as a protective film.
In the annealing treatment described in this publication, the WSiN film can reduce the local dissociation of As around the gate.
To remove the N film, for example, RIE using a fluorine-based gas
It is difficult to selectively remove the WSiN film from the gate electrode made of WSi, which is a problem in ensuring controllability and uniformity of the gate length. The present invention has been made to solve the above problems, and provides a compound semiconductor device capable of preventing the formation of depressions around the gate and easily removing the annealing protective film after annealing. The purpose is to obtain a manufacturing method.

[0012]

A method of manufacturing a compound semiconductor device according to the present invention comprises forming a refractory metal gate on a semiconductor layer of a predetermined conductivity type formed on the surface of a compound semiconductor substrate, After forming a high-concentration semiconductor layer having the same conductivity type as that of the semiconductor layer on both sides of the gate electrode by implanting impurities, an insulating film serving as a protective film for annealing, and Mo, Ti, Si, and A high thermal conductive film made of a material such as W or WSiN, WSi, WN, TiN is sequentially formed, and then annealing is performed using the insulating film and the high thermal conductive film as a protective film for annealing.

According to the present invention, in the method of manufacturing a compound semiconductor device, the insulating film is formed by laminating a SiN film or a SiON film on a SiO2 film. According to the present invention, in the method of manufacturing a compound semiconductor device, the SiO2 film is removed by a required etching solution after the annealing treatment.

According to the present invention, in the method of manufacturing a compound semiconductor device described above, Si is formed on both sides of the gate electrode of the semiconductor substrate.
A side wall made of O2 is formed, and then the insulating film and the high thermal conductive film are sequentially deposited. According to the present invention, in the method of manufacturing a compound semiconductor device, the sidewall is removed by a required etching solution after annealing.

According to the present invention, in the method of manufacturing a compound semiconductor device, a SiO2 film is formed on the entire surface after forming the sidewall and before forming the insulating film. In the method for manufacturing a compound semiconductor device according to the present invention, the annealing protective film has a multi-layer structure in which a thin insulating film and a thin high thermal conductive film are alternately and repeatedly laminated. Is.

According to the present invention, in the above method for manufacturing a compound semiconductor device, either or both of an insulating protective film and a conductive protective film are formed as an annealing protective film on the back side of the substrate before the annealing. . In the method of manufacturing a compound semiconductor device according to the present invention, an insulating film and a high thermal conductive film made of a refractory metal film or a compound thereof are laminated as the annealing protection film on the back surface side. In the method of manufacturing the compound semiconductor device according to the present invention, the insulating film is formed by laminating a SiN film or a SiON film on a SiO2 film.

[0017]

According to the present invention, a refractory metal gate is formed on a semiconductor layer of a predetermined conductivity type formed on the surface of a compound semiconductor substrate, and impurities are implanted into both sides of the gate electrode on the surface of the semiconductor substrate to form the same layer as the semiconductor layer. After forming a conductive type high-concentration semiconductor layer, on the semiconductor layer and the gate electrode,
Since an insulating film that serves as a protective film for annealing and a high thermal conductive film are sequentially formed and then annealing is performed, it is possible to prevent some of the constituent atoms of the substrate from dissociating from the substrate surface around the gate during the annealing process. It can be suppressed by the film and the high thermal conductivity film, and the high thermal conductivity film improves the thermal conductivity on the semiconductor surface to obtain a soaking effect, and local heating can be prevented, whereby the gate electrode It is possible to prevent the occurrence of depressions in the periphery. Further, since the insulating film is formed on the lower side of the high thermal conductive film, even when the high thermal conductive film and the gate electrode are made of the same material, the high thermal conductive film is used to etch the gate electrode. It can be removed by etching without performing.

Further, in the present invention, since the insulating film constituting the annealing protective film is made of the SiN film or the SiON film, the dissociation of a part of the substrate constituent atoms from the substrate surface around the gate is minimized. Can be reduced. Further, in the present invention, the insulating film forming the annealing protection film is a SiO2 film, and after the annealing treatment, the insulating film is removed with a required etching solution, so that the protection film after annealing can be easily removed. It can be performed without fear of etching the gate electrode.

Further, in the present invention, after the sidewalls made of SiO 2 are formed on both sides of the gate electrode of the semiconductor substrate, the insulating film and the high thermal conductive film are formed as the annealing protection film. Not only can the formation of depressions around the electrodes be prevented, but since the SiO2 sidewall is formed around the gate when the protective film for annealing is removed, the removal can be easily performed by etching.

In the present invention, the protective film for annealing has a multi-layer structure in which the thinned insulating film and the thinned high thermal conductive film are alternately and repeatedly laminated. In that case, a sufficient soaking effect can be obtained, local heating can be avoided, and dissociation of constituent atoms from the compound semiconductor substrate surface can be further reduced. Further, the multi-layer structure can reduce the stress more than the single-layer structure, and the film peeling of the annealing protective film is less likely to occur.

Further, in the present invention, before the annealing, the insulating protective film and / or the conductive protective film or both of them are formed as the protective film for annealing on the back surface side of the substrate. The stress that occurs when the film is formed can be relaxed by the back surface protective film, and dissociation of constituent atoms from the back surface of the compound semiconductor substrate can be prevented by the back surface protective film.

[0022]

EXAMPLE 1 FIG. 1 is a cross-sectional view of a protective film for annealing used in a method of manufacturing a compound semiconductor device according to Example 1 of the present invention, and FIG. 2 shows a method of manufacturing the compound semiconductor device in the order of steps. It is a figure for explaining. In the figure,
Reference numeral 10 denotes an annealing protection film formed after implanting an n-type dopant into the refractory metal gate 2 and the n ⁺ layer 9 which is a drain / source region. The annealing protection film 10 is a GaAs semi-insulating substrate 1, A 300 Å thick SiO2 film 3 deposited on the semi-insulating substrate 1, the S
It comprises a SiN film 4 having a film thickness of 500 angstroms deposited on the iO2 film 3 and a WSi film 5 having a film thickness of 400 angstroms formed on the SiO2 film 4.

Next, the manufacturing method will be described. First,
Forming a SiO2 film 12 on the GaAs semi-insulating substrate 1,
Si, which is an n-type dopant, is selectively implanted using the resist 11 as a mask. After removing the resist 11,
The SiO2 film 12 is directly used as an annealing protection film for activation annealing to form an n-implanted region 8 (FIG. 2 (a)).
). Next, the SiO2 film 12 is removed, and the refractory metal gate 2 is formed by sputtering or the like and etching thereof, for example, processing by RIE using a fluorine-based gas (FIG. 2 (b)). Next, an n-type dopant is implanted using the resist 11 and the refractory metal gate 2 as a mask (FIG. 2 (c)). After removing the resist 11, the SiO2 film 3 and the SiN film 4 are formed on the substrate 1 by plasma CVD or the like.
Are sequentially formed, and the high thermal conductive film 5 made of WSi is formed thereon by the sputtering method. Thereafter, the SiO2 film 3, SiN film 4, and WSi film 5 are annealed as a protective film 1 for annealing.
Then, activation annealing is performed with the value 0 to form an n ⁺ layer 9 which is a drain / source region (FIG. 2 (d)). Finally, after removing the protection film 10 for annealing, an ohmic electrode 13 is formed on the source and drain regions 9,
Is completed (Fig. 2 (e)).

Here, the WSi film 5 and the SiN film 4 are used.
Are partially removed by RIE or the like, and the remaining SiN film 4 and SiO2 film 3 are removed with a hydrofluoric acid aqueous solution. WS in RIE
When the i film 5 is removed, there is no problem that the WSi gate 2 is etched at the same time as the high thermal conductivity film 5 because the SiO 2 film 3 as an etching protection film is under the i film 5, and the bottom layer is the SiO 2 film 3. Therefore, it is possible to easily remove these with an aqueous solution of hydrofluoric acid.

Next, the function and effect will be described. Figure 9 (b)
Is a SEM photograph of a substrate cross section when an annealing process is performed after the gate is formed using the protective film 10 for annealing, which is seen in the conventional protective film using only the SiO2 film as shown in FIG. 9 (a). Almost no cavities due to As escape around the gate are seen. This is because the loss of As is reduced by forming the SiN film 4 having a small diffusion of As atoms on the SiO2 film 3 and further forming the WSi film 5 made of the same material as the gate on the SiN film 4. It is considered that this is because the local heating around the gate is suppressed.

As described above, in the method of manufacturing the compound semiconductor device according to the first embodiment, after the gate electrode is formed, S is formed on the entire surface.
iO2 film 3, SiN film 4 and WSi film 5 having high thermal conductivity
Since the film is formed and then annealing is performed using these films as a protective film for annealing, it is possible to suppress the dissociation of some of the substrate constituent atoms from the substrate surface around the gate by the insulating film, and The high thermal conductivity film 5 improves the thermal conductivity on the surface of the semiconductor to obtain a soaking effect, and can prevent local heating, thereby preventing the formation of depressions around the gate electrode. In addition, the protective film for annealing 10 includes the WSi film 5 and SiN.
The SiO2 film 3 can be easily removed by an RIE method on the film 4 by an aqueous solution of hydrofluoric acid, and at the time of etching the WSi film 5, the WSi gate 2 below the SiO2 film 2 is made of SiO2.
Since it is covered with the film 3, there is no risk of etching the gate electrode 2. Although WSi is used as the high thermal conductivity film in the above-mentioned embodiment, it may be formed of a high melting point metal film such as Mo, Ti, Si, W, or its compound WSiN, WN, TiN, or the like. Good.

Although the SiO2 film 3 is formed after the ion implantation in the above embodiment, it may be formed before the ion implantation.
Ion implantation is performed through the membrane 3. Further, although the SiN film 4 is used in the above-mentioned embodiment, this is SiO containing oxygen.
An N film may be used, and by doing so, stress can be reduced by containing oxygen and film peeling can be made less likely to occur. However, in this case, as the oxygen content increases, As atoms easily diffuse in the film and As is dissociated from the GaAs surface, so it is necessary to select an optimum content.

Embodiment 2 FIG. 3 is a cross-sectional view of a protective film for annealing used in a method of manufacturing a compound semiconductor device according to Embodiment 2 of the present invention, in which the same as FIG. 1 and FIG. 2 of Embodiment 1 above. Reference numeral indicates the same or a corresponding portion, and reference numeral 40 denotes a multilayer annealing protective film including a lower-layer annealing protective film 20 and an upper-layer annealing protective film 30. The lower-layer annealing protective film 20 is sequentially laminated on the substrate 1. , Thinned Si
The O2 film 3a, the SiN film 4a, and the WSi film 5a are formed, and the upper annealing protective film 30 is the WSi film 5a.
a thin SiO2 film 3b, Si sequentially laminated on a
It is composed of an N film 4b and a WSi film 5b.

Further, FIG. 4 (a) is a view conceptually showing an apparatus used to form the above-mentioned protective film for annealing.
0 is a P (plasma) -CVD apparatus, and its chamber 50
In a, a SiO2 target 51 and a SiN target 52 are arranged above the portion where the substrate 1 is arranged. Further, reference numeral 60 is a sputtering apparatus, which is a chamber 6
A WSi target 61 is arranged above the portion of the substrate 0a where the substrate 1 is arranged.

Next, the manufacturing method will be described. In the manufacturing method of this embodiment, in the process shown in FIG. 2D of the first embodiment, the process of sequentially forming the SiO2 film, the SiN film and the WSi film on the substrate The protective film 40 for multilayer annealing is formed by thinning and repeating twice.
Are formed.

That is, in the manufacturing method of this embodiment, first, in the process shown in FIG.
It is placed in the chamber 50a of the CVD apparatus 50, and the SiO2 film 3a and the SiN film 4a are successively formed on the substrate to be thinner than the SiO2 film 3 and the SiN film 4 of the first embodiment.

Thereafter, the substrate 1 is placed on the P-CVD apparatus 50.
Of the sputtering apparatus 60, the WSi film 5a having a high thermal conductivity is formed on the SiN film 4a to be thinner than the WSi film 5 of the first embodiment, and the lower layer annealing is performed. Forming a protective film 20 for use.

After that, the same processing as described above is repeated to form the SiO2 film 3b and the SiN film 4 on the WSi film 5a.
b and the WSi film 5b are sequentially formed to form the upper-layer annealing protective film 30, and the annealing protective film 40 having a multilayer structure is formed.
To form. After that, the same processing as in the first embodiment is performed to complete the FET.

As described above, according to the second embodiment, SA
An annealing protective film used in the process flow of the GFET is formed on the substrate 1 in this order, and the lower annealing protective film 20 is composed of the thinned SiO2 film 3a, SiN film 4a, and WSi film 5a, and the WSi film. Since the upper layer annealing protection film 30 is formed of the SiO2 film 3b, the SiN film 4b, and the WSi film 5b, which are sequentially laminated on the gate electrode 5a, as in the first embodiment, the area around the gate electrode is reduced. In addition to the effect of preventing the formation of depressions in the film and easy removal of the annealing protection film, the annealing protection film 40 is made of a thin SiO 2 film, a SiN film, and a WSi film. Since it is composed of the film 20 and the protective film 30 for the upper layer annealing, it is possible to prevent the film peeling due to the stress between the adjacent films which occurs when the respective films are thick. .

Example 3. FIG. 4 (b) is a diagram for explaining a method for manufacturing the compound semiconductor device according to the third embodiment of the present invention, which is a conceptual diagram showing a film forming apparatus used for forming an annealing protective film in this manufacturing method. is there. In the figure, reference numeral 70 denotes a film forming apparatus, which has a chamber 70a in which a SiO2 target 7 is provided above a portion where the substrate 1 is arranged.
1, a target 72 of SiN and a target 73 of WSi are arranged.

This embodiment differs from the second embodiment only in that the multilayer annealing protective film 40 is formed by using the film forming apparatus 70 having the above-mentioned structure. FIG. 4B is a diagram showing an apparatus used for manufacturing the protective film for annealing. Since this apparatus has three different targets in one chamber, unlike the second embodiment, the protective film for annealing is different. The semiconductor substrate 1 does not have to be taken out of the device during the formation of the film.

That is, in the manufacturing method of the third embodiment, in the step shown in FIG. 2D of the first embodiment, first, the substrate 1 is placed in the chamber 70a of the film forming apparatus 70, and SiO2 is deposited on the substrate. The film 3a, the SiN film 4a, and the WSi 5a are sequentially formed to be thinner than those in Example 1 to form the lower-layer annealing protective film 20, and subsequently, the same treatment as described above is repeated to form a film on the WSi film 5a. SiO2 film 3b,
The SiN film 4b and the WSi film 5b are sequentially formed to form the upper-layer annealing protective film 30 and the annealing protective film 40 having a multilayer structure.

As described above, according to the third embodiment, when manufacturing the annealing protection film having the multilayer structure including the lower-layer annealing protection film and the upper-layer annealing protection film, a plurality of layers are formed in one chamber. Since the film forming apparatus 70 having the target of No. 2 is used, in addition to the effect of the second embodiment, it is not necessary to take the substrate out of the film forming apparatus during the formation of the protective film for annealing.
The effect of preventing surface contamination and improving work efficiency can be obtained.

Embodiment 4 FIG. 5 is a cross-sectional view of an annealing protective film used in a method of manufacturing a compound semiconductor device according to a fourth embodiment of the present invention, and FIG. 6 is a view for explaining the method of manufacturing the compound semiconductor device. It is a figure. In the figure, the same reference numerals as those in FIGS. 1 and 2 of the first embodiment indicate the same or corresponding portions. In the fourth embodiment, the point that the protective film for annealing is formed not only on the front surface of the substrate but also on the back surface of the substrate, is the same as the first embodiment.
Is different from

Next, the manufacturing method will be described. The gate electrodes 2 and S are formed on the front surface side of the substrate 1 in the same manner as in the first embodiment.
After forming the iO2 film 3, the SiN film 4, and the WSi film 5 (FIGS. 6 (a) to 6 (d)) and further forming the source / drain layers 9 (FIG. 6 (d)), the semiconductor substrate 1 is turned over. And GaA
s A film is formed on the back surface of the semi-insulating substrate 1 in the same manner as the front surface side to form a back surface protection film 7 (FIG. 6 (e)). Finally, the ohmic electrode 13 is formed on the source and drain regions,
The FET is completed (Fig. 6 (f)).

In Embodiment 4, since the protective film is formed not only on the front surface of the semiconductor substrate but also on the back surface thereof, in addition to the effect of Embodiment 1 described above, the stress due to film formation is the same on the front surface and the back surface of the substrate. Therefore, it is possible to reduce the distortion of the wafer and the occurrence of slip lines, and it is possible to prevent the dissociation of constituent atoms from the back surface of the compound semiconductor substrate.

The back surface protection film 7 has the same structure as the film formed on the front surface and has the same structure as the SiO2 film 3, the SiN film 4, and the WSi film 5.
Or a direction of stress,
The film may be made of only WSi, the size of which can be adjusted. Further, the step of forming the back surface protective film may be performed before forming the front surface protective film.

Embodiment 5 FIG. 7 is a sectional view of an annealing protective film used in a method of manufacturing a compound semiconductor device according to Embodiment 5 of the present invention, and FIG. 8 is a diagram showing a method of manufacturing the annealing protective film. is there. In the fifth embodiment, an intermediate concentration n'layer 9a is provided between the channel layer 8 and the source / drain n ⁺ layer 9.
The method of manufacturing an FET having the above-described method has the step of forming the annealing protective film of Example 1 described above added. In the figure, the same reference numerals as those in FIGS. 1 and 2 indicate the same or corresponding portions, and 6 is a sidewall made of a SiO2 film formed on both sides of the gate electrode of the semiconductor substrate which constitutes the protection film for annealing in this embodiment. is there.

Next, the manufacturing method will be described. Figure 8
(a)-(e) is a figure for demonstrating the manufacturing method of FET which uses a present Example in order of process. The n layer 8 and the high melting point gate 2 are formed in the same manner as in the manufacturing method of the first embodiment (see FIG.
(a)), n-type dopant is implanted. After that, a SiO2 film 3 is deposited on the entire wafer by plasma CVD or the like (FIG. 8 (b)), and anisotropic etching such as RIE is performed.
Sidewalls 6 are formed by leaving the insulating film 3 only on the side surfaces of the gate (FIG. 8C). Then, after ion implantation is performed again (FIG. 8 (d)), the sidewall 6 is removed.
Is not removed, and the SiN film 4 is formed on top of it.
The film 5 is formed to serve as a protective film for annealing. Then, an annealing treatment is performed to form a high-concentration n ⁺ layer 9 and an intermediate-concentration n ′ layer 9a under the sidewall 6 (FIG. 8 (e)). Finally, ohmic electrodes are formed on the source and drain regions to complete the FET.

As described above, according to the fifth embodiment, SA
In the process flow of the GFET, the n-type dopant is injected leaving the sidewall 6 only on the side surface of the gate, then the SiN film 4 is formed on the sidewall, and the high thermal conductive film 5 is further formed for annealing. Since the protective film is formed, it is possible to suppress the dissociation of some of the constituent atoms of the substrate from the surface of the substrate around the gate, and the high thermal conductivity film 5 improves the thermal conductivity on the surface of the semiconductor, soaking the heat. It is possible to obtain the effect, and it is possible to prevent local heating, and thus it is possible to prevent the occurrence of depressions around the gate electrode. Further, the SiN film 4 is difficult to be removed in the peripheral portion of the gate, but in this structure, SiO2 is formed in the peripheral portion of the gate.
Since the side wall 6 is formed, this problem does not occur. Although the SiN film 4 is directly formed on the sidewall 6 in the fifth embodiment, the SiN film 4 may be formed after the SiO2 film is formed on the sidewall 6.

[0046]

As described above, according to the compound semiconductor manufacturing method of the present invention, the refractory metal gate is formed on the semiconductor layer of the predetermined conductivity type formed on the surface of the compound semiconductor substrate, and After forming a high-concentration semiconductor layer having the same conductivity type as the semiconductor layer by implanting impurities on both sides of the gate electrode, an insulating film is formed on the semiconductor layer and the gate electrode.
And the high thermal conductive film are sequentially formed, and then annealing is performed using the insulating film and the high thermal conductive film as the annealing protective film. Therefore, the annealing protective film suppresses dissociation of substrate constituent atoms, and The entire upper surface is heated uniformly, which has the effect of reducing the occurrence of depressions around the gate.

Further, since the insulating film is formed below the high thermal conductive film, even if the high thermal conductive film and the gate electrode are made of the same material, the high thermal conductive film is used as the gate. The electrode can be removed by etching without etching, which makes it possible to perform good annealing after forming the gate by applying a cap anneal, with excellent uniformity and reproducibility, and at high concentration and diffusion. There is an effect that it is possible to form a semiconductor device having a high-quality impurity-implanted active layer in which the generation is suppressed with high yield.

Further, according to the present invention, in the above manufacturing method, the thinned high thermal conductivity film and the thinned insulating film are alternately and repeatedly laminated to form the protective film for multilayer annealing. In addition, stress in the annealing protection film is reduced, and peeling of the annealing protection film is less likely to occur.

Further, according to the present invention, in the above-mentioned manufacturing method, since the insulating film forming the annealing protection film is the SiN film or the SiON film, some of the substrate constituent atoms are dissociated from the substrate surface around the gate. Can be effectively reduced, and further, when the SiON film is used for the insulating film, there is an effect that the film peeling of the annealing protection film is further difficult to occur. Further, according to the present invention, in the above manufacturing method, since the insulating film forming the protective film for annealing is a SiO2 film, there is an effect that the protective film can be easily removed after annealing.

Further, according to the present invention, in the above manufacturing method, as the annealing protection film, sidewalls made of SiO 2 are formed on both sides of the gate electrode of the semiconductor substrate, and then a SiN film or a SiON film is formed on the entire surface.
Since a high thermal conductivity film made of a refractory metal or its compound is sequentially deposited, not only can the formation of depressions around the gate electrode be prevented, but when the protective film for annealing is removed, a SiO2 sidewall is formed around the gate. Since it is formed, there is an effect that it can be easily removed by etching.

According to the invention, in the above manufacturing method, before the annealing, not only on the semiconductor layer and the gate electrode on the front surface side of the semiconductor substrate but also on the back surface of the semiconductor substrate, the insulating film and the high thermal conductive film are formed. Is sequentially deposited as a protective film for annealing, the stress generated when the protective film for annealing is formed only on the front surface can be relaxed by the protective film on the back surface side, and dissociation of constituent atoms from the rear surface of the compound semiconductor substrate is also on the back surface side. There is an effect that can be prevented by the protective film.

[Brief description of drawings]

FIG. 1 is a SAGFET used in a first embodiment of the present invention.
Schematic cross-sectional view showing the structure of an annealing protective film used in the manufacturing method of FIG.

FIG. 2 is a SAGFET according to the first embodiment of the present invention.
Schematic cross-sectional view showing the manufacturing method of.

FIG. 3 is a schematic cross-sectional view showing the structure of an annealing protective film used in the second and third embodiments of the present invention.

FIG. 4 is a SAGFET according to the second and third embodiments.
FIG. 3 is a diagram conceptually showing the structure of a film forming apparatus used in the manufacturing method of FIG.

FIG. 5 is a schematic cross-sectional view showing the structure of an annealing protective film used in the method for manufacturing a SAGFET according to the fourth embodiment of the present invention.

FIG. 6 is a schematic sectional view showing a method of manufacturing a SAGFET according to the fourth embodiment of the invention.

FIG. 7 is a schematic sectional view showing the structure of an annealing protective film used in the method for manufacturing a SAGFET according to the fifth embodiment of the present invention.

FIG. 8 is a schematic sectional view showing a method of manufacturing a SAGFET according to the fifth embodiment of the invention.

FIG. 9: SAG of the conventional method and the first embodiment of the present invention
The figure which shows the SEM photograph of the GaAs substrate cross section after annealing process in the manufacturing method of FET.

FIG. 10 is a schematic sectional view showing an example of a conventional method for manufacturing a SAGFET.

FIG. 11 is a schematic sectional view showing another example of the conventional method for manufacturing a SAGFET.

[Explanation of symbols]

1 GaAs semi-insulating substrate 2 refractory metal gate 3 SiO2 film 3a thinned SiO2 film 3b thinned SiO2 film 4 SiN film 4a thinned SiN film 4b thinned SiN film 5 WSiN film 6 side Wall 7 Protective film 8 n Implanted region (n layer) 9 n ⁺ Implanted region (n ⁺ layer) 9a n'Injected region (n 'layer) 10 Protective film for annealing 11 Resist 12 SiO2 film 13 Ohmic electrode 14 Protective film 20 Lower layer Protective film for annealing 30 Protective film for upper layer annealing 40 Protective film for multilayer annealing 50 P-CVD device 60 Sputtering device 70 Film forming device

[Procedure amendment]

[Submission date] February 28, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

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[0002]

2. Description of the Related Art In a conventional SAGFET (self-alignment gate FET) process, after forming a refractory metal gate such as WSi, ion implantation is performed using this as a mask to perform activation annealing. In the process, activation annealing after ion implantation needs to be performed at a high temperature of 800 ° C. or higher. However, in general, compound semiconductors often contain high vapor pressure constituent elements, and when such a substrate is exposed to high temperatures, some of the constituent atoms of the substrate dissociate from the substrate surface. Then, vacant points are generated. Therefore, at such a high temperature, constituent atoms having a high equilibrium vapor pressure are dissociated from the surface and deteriorate the characteristics of the ion-implanted layer.

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[Name of item to be corrected] 0029

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Further, FIG. 4 (a) is a view conceptually showing an apparatus used to form the above-mentioned protective film for annealing.
0 is a P (plasma) -CVD apparatus, and its chamber 50
Gas as a raw material is introduced into a . A sputtering apparatus 60 has a WSi target 61 arranged above the portion of the chamber 60a where the substrate 1 is arranged.

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

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[Figure 4]

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/324 C

Claims (11)

[Claims] 1. A step of selectively implanting an impurity into a surface of a compound semiconductor substrate to form a semiconductor layer of a predetermined conductivity type, and a step of forming a gate electrode made of a refractory metal on a predetermined region of the semiconductor layer. And a step of forming a high-concentration semiconductor region of the same conductivity type as the semiconductor layer by implanting impurities on both sides of the gate electrode of the semiconductor substrate, and an insulating film serving as a protective film for annealing on the semiconductor layer and the gate electrode. , And a step of sequentially depositing a high thermal conductive film made of a refractory metal or a compound thereof, and then performing an annealing process using the insulating film and the high thermal conductive film as a protective film for annealing. Method for manufacturing compound semiconductor device. 2. The method for manufacturing a compound semiconductor device according to claim 1, wherein the insulating film is a SiN film or a SiO 2 film on a SiO 2 film.
A method for manufacturing a compound semiconductor device, which comprises laminating N films. 3. The method of manufacturing a compound semiconductor device according to claim 2, wherein the SiO 2 film is removed by a required etching solution after the annealing treatment. 4. The method for manufacturing a compound semiconductor device according to claim 1, wherein the high thermal conductivity film is Mo, Ti, Si, W, or
A method of manufacturing a compound semiconductor device, which comprises WSiN, WSi, WN, and TiN. 5. The method of manufacturing a compound semiconductor device according to claim 2, wherein the annealing protection film has sidewalls made of SiO 2 formed on both sides of the gate electrode of the semiconductor substrate, and then has a SiN film or SiON film on the entire surface. A method of manufacturing a compound semiconductor device, which comprises sequentially depositing a film and a film having a high thermal conductivity made of a refractory metal or its compound. 6. The method of manufacturing a compound semiconductor device according to claim 5, wherein the sidewalls are removed by a required etching solution after the annealing treatment. 7. The method of manufacturing a compound semiconductor device according to claim 5, wherein after forming the side wall, a SiO2 film is formed on the entire surface before forming the SiN film or the SiON film. And a method for manufacturing a compound semiconductor device. 8. The method of manufacturing a compound semiconductor device according to claim 1, wherein the annealing protective film is formed by alternating a thin insulating film and a thin high thermal conductivity film. A method of manufacturing a compound semiconductor device, wherein the compound semiconductor device has a multi-layered structure formed by repeatedly stacking layers. 9. The method of manufacturing a compound semiconductor device according to claim 1, wherein both the insulating protective film and the conductive protective film are formed on the back surface side of the semiconductor substrate before the annealing. Alternatively, a method of manufacturing a compound semiconductor device, characterized in that one of them is formed as a protective film for annealing. 10. The method of manufacturing a compound semiconductor device according to claim 9, wherein the backside annealing protective film is made of an insulating film and a refractory metal film or a compound thereof on the backside of the semiconductor substrate. A method for manufacturing a compound semiconductor device, which comprises sequentially stacking high thermal conductive films. 11. The method of manufacturing a compound semiconductor device according to claim 10, wherein the insulating film is a SiN film or a SiO film on a SiO 2 film.
The high thermal conductivity film is made of Mo, Ti, Si, W, or
A method of manufacturing a compound semiconductor device, which comprises WSiN, WSi, WN, and TiN.