JPH07160862A - Frame memory reading circuit - Google Patents

Abstract

PURPOSE:To deform and display a picture in real time by making it possible to the picture of a frame memory so as to display it without rewritting the frame memory. CONSTITUTION:Register parts (50 and 53) respectively store a reading start position and an increase portion in the horizontal direction, which are supplied at every horizontal scanning cycle and the reading start position and the increase portion in the vertical direction. Arithmetic parts 55, 56 and 58 vary the respective reading positions in the horizontal and vertical directions for the increase portion from the respective reading start positions in the horizontal and vertical directions whenever clock expressing a display period of one picture element portion comes so as to output them. The frame memory is accessed with the reading positions in the horizontal and vertical directions, which are outputted from the arithmetic parts 55, 56 and 58, as a reading address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory reading circuit, and more particularly to a frame memory reading circuit for controlling reading of image data from a frame memory.

[0002]

2. Description of the Related Art Conventionally, in an image processing apparatus used as a game machine, a foreground image in which a character appearing in a game is written into a frame memory, developed, and sequentially read from the frame memory in synchronization with horizontal and vertical sync signals. It is performed to combine and display with a background image prepared separately.

[0003]

In the conventional apparatus, the foreground picture is read from the frame memory according to the horizontal and vertical synchronizing signals of the display, and if the whole foreground picture is deformed by enlargement, reduction, rotation, etc. Must be modified to rewrite the frame memory. For example, a modification that continuously changes the enlargement / reduction ratio or the rotation angle requires time to rewrite the frame memory, and it is difficult to display the modified foreground in real time. There was a problem.

The present invention has been made in view of the above points,
An object of the present invention is to provide a frame memory read circuit that can deform and display an image in the frame memory without rewriting the frame memory and can deform and display the image in real time.

[0005]

A frame memory read circuit according to the present invention includes a register section for storing a horizontal read start position and an increment, and a vertical read start position and an increment, which are supplied every horizontal scanning period. And a calculation unit that outputs the read position in the horizontal direction and the read position in the vertical direction by incrementing from the read start position in the horizontal direction and the read position each time the clock indicating the display period for one pixel comes in. Then, the frame memory is accessed using the horizontal and vertical read positions output from the arithmetic unit as read addresses.

[0006]

The frame memory read circuit of the present invention sets the read start position and the increment in the horizontal direction and the vertical direction for each horizontal scanning period, and changes the read position by the increment in dot units, so that the frame memory is rewritten. Instead, the image in the frame memory can be transformed and displayed, and the image can be transformed and displayed in real time.

[0007]

2 is a block diagram of an embodiment of an image processing apparatus to which the apparatus of the present invention is applied. In the figure, a bus 15 is connected to a CPU 15 for executing a game program, a RAM 16 for storing the program, a bus controller 17, a sprite engine 20 for performing foreground image processing, and a scroll engine 21 for performing background image processing. Further, the sprite engine 20 is connected to a RAM 22 for storing foreground patterns and window patterns of characters and the like and a frame buffer 23 for developing the foreground patterns, and the scroll engine 21 is provided with a video RAM (VRAM) 24 for storing background patterns and a color. RAM2
5 is connected.

The CPU 15 executes a program and issues a command to the sprite engine 20 and the scroll engine 21 to draw a composite image. The bus controller 17 controls the right to use the bus 14 by the CPU 15, the sprite engine 20, and the scroll engine 21.

The sprite engine 20 selects and reads image data of a foreground pattern such as a character from the RAM 22, performs processing such as rotation, enlargement, reduction, color calculation, and the like, and then writes it to a predetermined address of the frame memory 23 to write it in the foreground. Expand the pattern. Also, Sprite Engine 2
A frame memory read circuit 40 is provided in 0, and the frame memory 23 is accessed by an address generated by the frame memory read circuit 40, and the image data of the foreground image read by this is not passed through the bus 14. Directly from the sprite engine 20, scroll engine 21
Is supplied to.

The scroll engine 21 again performs VRA based on the pattern name data read from the VRAM 24.
The pattern data (the image data of the cell composed of a predetermined number of pixels) is read from M24 and the image data of the background image synchronized with the foreground image is generated. Further, the priority code at the predetermined bit position of the image data of each of the foreground image and the background image is compared, and the image data of the foreground image or the background image having a high priority is selected to combine them. After that, the color RAM 25 is accessed with the color code at the predetermined bit position of the selected image data.
RGB data representing the respective levels of GB are obtained. This R
The GB data is supplied from the scroll engine 21 to the D / A converter 31, converted into an analog signal, output as an RGB video signal from the terminal 32, and displayed on a monitor (not shown).

FIG. 1 shows a block diagram of a frame memory read circuit of the present invention. In the figure, a start signal D synchronized with a horizontal synchronizing signal from the scroll engine 21 is provided at a terminal 41.
The ISPST comes in and is provided to the timing generator 42. The terminal 43 receives data DATA of the initial value X _DISP , the increment ΔX, the initial value Y _DISP , and the increment ΔY from the scroll engine 21 in time series, and the terminal clock 44 receives the dot clock CLK from the scroll engine 21. Come and
These data and clock are supplied to the X counter 45 and the Y counter 46, respectively.

The timing generator 42 uses a start signal DI
X _DISP , Δ in the horizontal blanking period in synchronization with SPST
Latch signal XDC when X, Y _DISP and ΔY come in
K, ΔXCK, YDCK, and ΔYCK are generated, and a start signal START is generated, and these are supplied to the X counter 45 and the Y counter 46, respectively.

Each of the X counter 45 and the Y counter 46 has the structure shown in FIG. As an X counter 45, the register 50 receives data DATA from the terminal 52 when the latch signal XDCK is received from the terminal 51.
The initial value X _DISP that comes in is latched and supplied to the multiplexer (MPX) 55. Further, the register 53 is provided with the terminal 52 when the latching signal ΔXCK is received from the terminal 51.
The increment ΔX that comes in as more data DATA is latched and supplied to the adder (FA) 56.

When the start signal START comes in from the terminal 57 after the signals XDCK and ΔXCK come in, the multiplexer 55 selects the initial value supplied from the register 50 and supplies it to the latch circuit 58, and then the latch circuit 58. Within one clock cycle of the clock CLK supplied to 58, the adder ADDS from the adder 56 is selected and supplied to the latch circuit 58.

The latch circuit 58 receives the clock C from the terminal 59.
Each time LK comes in, the output of the multiplexer 55 is latched, output from the terminal 60, and supplied to the adder 56.
The adder 56 adds the increment ΔX supplied from the register 53 to the output of the latch circuit 58 and supplies it to the multiplexer 55. Due to the delay of the adder 56 and the multiplexer 55, the initial value X _DISP is immediately after the start signal comes in, and ΔX is added every time the clock comes in to generate an X address, which is output from the terminal 60.

The X address and Y address generated by the X counter 45 and the Y counter 46 are supplied to the frame memory 23 shown in FIG. 1 by using the X address as a lower address and a Y address higher address. The read image data is supplied to the sprite engine 20 from the terminal 47.

Since the frame memory 23 is addressed so as to match the scanning order of the display, the X address and the Y address can be regarded as the coordinates of each pixel on the display screen.

In the frame memory read circuit 40, by designating parameters, that is, initial values X _DISP , Y _DISP and increments ΔX, ΔY, the position represented by the following equation on the frame memory 23 at the nth clock after the start signal START comes in. The pixels of Xn and Yn are accessed.

(Xn, Yn) = (X _DISP + ΔX · n, Y _DISP + ΔY · n) However, the upper left corner of the screen is set to (0, 0). Increment ΔX, ΔY
If is positive, the pixels can be read out in an oblique direction for rotation display as shown in FIG. Further, if the increment ΔX is negative and the increment ΔY is positive, the pixels can be read from the right to the left as opposed to the normal one, as shown in FIG. Further, by setting 0 <ΔX <1 and 0 <ΔY <1, enlarged display can be performed in the horizontal direction and the vertical direction, and ΔX> 1 and ΔY> 1 are set (minus portions of Xn and Yn are discarded). ) A reduced display can be performed. In addition,
When the address is supplied to the frame memory 23, the parameter can be changed every horizontal scanning period (1 line), and thus the modified reading as shown in FIG. 4C can be performed.
In the frame memory 23, as shown in FIG.
When image data for displaying is stored, the image can be rotated and displayed as shown in FIG. 5 (A) by reading in an oblique direction, and the increments ΔX and ΔY are set to less than 1 in FIG. 5 (B). The enlarged display as shown is possible, and the reduced display as shown in FIG. 5C is possible with the increments ΔX and ΔY being 1 or more. Further, in the upper half of the screen of the frame memory 23 shown in FIG. 4C, the horizontal enlargement ratio is sequentially increased from the upper end line to the central line to read from the left end to the right end. As shown in FIG. 5D, the enlargement ratio is sequentially reduced from the line to the bottom line, and reading is performed from the right end toward the left end.
A modified display as shown in is possible.

[0020]

As described above, according to the frame memory reading circuit of the present invention, the image in the frame memory can be transformed and displayed without rewriting the frame memory, and the image can be transformed and displayed in real time, which is extremely useful in practice. Is.

[Brief description of drawings]

FIG. 1 is a block diagram of a circuit of the present invention.

FIG. 2 is a block diagram of an image processing apparatus to which the circuit of the present invention is applied.

FIG. 3 is a circuit configuration diagram of a counter.

FIG. 4 is a diagram for explaining the present invention.

FIG. 5 is a diagram for explaining the present invention.

[Explanation of symbols]

 20 sprite engine 21 scroll engine 23 frame memory 40 frame memory read circuit 42 timing generator 45 X counter 46 Y counter 50, 53 register 55 multiplexer 56 adder 58 latch circuit

Claims (1)

[Claims] 1. A clock for inputting a horizontal read start position and an increment, a register for storing the vertical read start position and an increment, and a clock for indicating a display period for one pixel, which are supplied every horizontal scanning period. Each time the reading position in the horizontal direction and the vertical direction is changed by an increment from the reading start position in the horizontal direction and the vertical direction, respectively, and output. The frame memory read circuit is characterized in that the frame memory is accessed using the read position of the read address.