JPH07159499A - Judging method for fundamental undetected failure of logic circuit, and test pattern production method - Google Patents

Abstract

PURPOSE:To efficiently judge fundamental undetected failure of a logic circuit of an operator system and producing test patterns. CONSTITUTION:In failure diagnosis of a logic circuit of an operator system, whether the failure is an fundamental undetected failure or not is judged in the following procedure. First, the objective logic circuit is separated into some combined circuits and each separated circuit is converted into equivalent circuit consisting of a single kind of basic gates. Then, this equivalent circuit is converted into a single output circuits outputting true value only to an input pattern for detecting a failure. EOR, ENOR logics are recognized, EOR, ENOR logics are simplified and the single output circuit is simplified. Furthermore, in this simplified circuit, whether an input pattern making the circuit output 1 exists or not is judged. Based on the judgement result from each separation circuit, whether or not the objective failure is a fundamental undetected failure in the whole circuits is judged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of diagnosing a failure in a logic circuit, and more particularly to a method for determining a principle undetected failure of a logic circuit composed of combinational circuits and a test pattern generating method.

[0002]

2. Description of the Related Art In recent years, as the scale of logic circuits has increased, the mainstream of fault diagnosis methods for logic circuits is to directly generate fault diagnosis data for the entire logic circuit. The scan design method is being shifted to one in which partial fault diagnosis data is generated for each combinational circuit and is edited to generate fault diagnosis data for the entire logic circuit. With this transition, the circuit to be subjected to the fault diagnosis is also changed from the sequential circuit to the combinational circuit, and the fault diagnosis data generation method for the combinational circuit, particularly the test pattern generation method and the fault simulation method, which are the core of the method, becomes an important issue. ing. To date, test pattern generation methods for combinational circuits have included Boolean differentiation, D algorithm, and PODEM (Path Oriented DE).
cision making), FAN (FAN out-oriented test gene
ration algorithm) has been proposed so that a test pattern with high detection rate can be generated. Fan
The test pattern generation method based on the algorithm is
"I-E-E-Transaction On
Computer, December 1983, NO.12, VOL.C-32,
Pp. 1137-1144 (IEEE TRANSACTIONS ON COMPU
TERS, VOL.C-32, NO.12, DECEMBER 1983, pp.1137-1144) "
It is described in. However, regarding an undetected failure, it is often unclear whether the test pattern, even if it exists, could not be generated or is undetected because the test pattern does not exist in principle. this is,
This is because the test pattern generation problem is the NP perfection problem, and in the worst case, it takes a processing time of the order of the exponent of the circuit scale, so that the test pattern generation is given up midway. In such a case, there is a method of efficiently generating a test pattern for a fault in which a test pattern exists, and determining a fault not having a test pattern in principle as a principle undetected fault. . Regarding this method, up to now, MH Schulz et al.'S method has been described as “IEE transaction on computer-aid design, July 1989, NO.7, VO.
L.8, pp. 811-816 (IEEE TRANSACTIONS ON COMP
UTER-AIDED DESIGN, VOL.8, NO.7, JULY 1989, pp.811-81
6) ”, a principle undetected failure determination method using a circuit simplification method is described in JP-A-5-5774.
The method proposed by MH Schulz et al. Defines the logical value uniquely by the conventional implication operation, etc. by adding the function of extended implication operation and unique activation to the test pattern generation system called SOCRATES. The logic value is set to the signal line that could not be set. As a result, the need for backtracking can be grasped at an early stage, and the range of searching for a solution (test pattern) in the space of all input patterns can be narrowed, resulting in more efficient test pattern generation and theoretical undetected failure than in the past. Can be extracted. When the logical value of the output signal line of the gate is uniquely determined by the logical value of the input signal line of the gate, the logical value is assigned to the output signal line, or the input of the gate is input by the logical value of the output signal line of the gate A conventional implication operation is to assign a logical value to an input signal line when the logical value of the signal line is uniquely determined. On the other hand, the extended implication operation is performed on two sets of signal lines that are not necessarily in the relationship of the input signal line and the output signal line of a certain gate,
When the logical value of the signal line of one set uniquely determines the logical value of the signal line of the other set, it is an operation of assigning the logical value. FIG. 2 is a diagram showing an example of the extended implication operation. In FIG. 2, 1m and 2m are AND gates, 3m, 4m, 5m, and 6m are signal lines. Figure 2
In (a), the logical value of the signal line 4m is 0. In this case, the logical values of the signal lines 5m and 6m are not uniquely determined, but since the AND gates 1m and 2m represent the same logic, the signal lines 3m and 4m must always take the same logical value. Therefore, as shown in FIG. 2B, 0 is assigned to the logical value of the signal line 3m. Unique activation means activating all gates through which a failure signal must pass. That is, when assigning a signal value to an input signal line of a gate through which a failure signal always passes, to which the failure signal never reaches, assign 1 if the gate is AND or NAND, and assign 0 if the gate is OR or NOR. . Figure 3
FIG. 6 is a diagram showing an example of unique activation. In FIG.
1n, 2n, 6n, 7n, and 8n are AND gates, 3
n, 4n, and 5n are OR gates, 9n is a hypothetical failure point, 10n, 11n, and 12n are signal lines. Figure 3
In (a), the logic value of 9n is 0/1 (0 in a normal circuit, 1 in a faulty circuit). This fault signal must be propagated to the output edge in order to generate the test pattern. In the circuit of FIG. 3A, the gates 2n and 5
n and 8n are gates that must pass through in order for the fault signal to propagate to the output edge. Figure 3 (b)
Indicates that 1 is assigned to the signal lines 10n and 12n, 0 is assigned to the signal line 11n, and the gates 2n, 5n, and 8n are activated. On the other hand, gates 3n and 4n and gates 6n and 7n
Does not assign a signal value because it is currently unknown whether the signal passes through any of its gates. In the method using the circuit simplification method, it is difficult to determine the principle undetected failure and generate the test pattern by converting the problem of the principle undetected failure judgment problem to "Is the output of the circuit always 0?" And reducing the target circuit. This is a method for efficiently performing the principle of undetected failure determination and test pattern generation by removing the redundancy in the circuit.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The method such as MHSchulz and the method using the circuit simplification method have a great effect on the faults for which it is difficult to generate test patterns or determine undetected faults in principle. There is a problem that the improvement is not yet sufficient. For example, in the method using the circuit simplification method, the circuit is composed of only NOR gates and input edges. 2-input Exclusive OR logic (abbreviated as EOR logic below)
A + B and 3-input EOR logic A + B + C are configured by NOR gates as shown in FIGS. 4 (a) and 4 (b), respectively. Also, the combination of EOR logic (A + B) + C and A + (B
+ C) is configured by NOR gates as shown in FIGS. 4C and 4D, respectively. Due to the nature of the EOR logic, (A + B) + C = A + (B + C) = A + B + C, but in the method using the circuit reduction method, as shown in FIG.
It cannot be recognized that the NOR gate expressions in (c) and (d) represent mutually equivalent logics. Since the logic circuit of the arithmetic unit system includes a large number of EOR logics, the inability to grasp the information in the circuit based on the property of the EOR logic means that the test pattern generation of the arithmetic unit system and the principle undetected failure judgment are efficient. It means that you cannot do it. The object of the present invention is to remedy such problems and to improve EO in a circuit.
Recognizing the R logic, grasping the redundancy of the circuit based on the property of the EOR logic in a unified manner, and removing the redundant part, the principle of undetected failure judgment using the circuit simplification method is efficiently performed. It is an object of the present invention to provide a theoretical undetected failure determination method and a test pattern generation method for a logic circuit.

[0004]

In order to achieve the above object, the principle undetected failure determination method and test pattern generation method for logic circuits of the present invention are characterized by executing the following steps. That is, of the combinational circuits obtained by dividing the target logic circuit, the first step of extracting all those including the target undetected fault location, and the second step of converting each divided circuit into an equivalent circuit expressed only by NOR gates.
The output becomes 1 for the input pattern (test pattern) that detects the target undetected fault in the equivalent circuit converted in the step and the second step, and the output becomes 0 for the other input patterns. The third step of converting this equivalent circuit into a single output circuit, and the fourth step of determining whether or not there is an input pattern in which the output of the single output circuit obtained in the third step is 1. In particular, the fourth step involves EOR logic and E in the target 1 output circuit.
First sub-step of extracting and reducing NOR logic, first
A second substep in which a plurality of gates representing the same logic in the circuit obtained in the substep are replaced by one gate, and 0 is independently set in the circuit obtained in the second substep.
Or a set of gates in the circuit that can control the output to be 1,
Signals at the boundary between the circuit area reachable from the branch point and the circuit area unreachable from the branch point are extracted by extracting a signal line branch point on the input side from this set of gates. A third sub-step of updating the line (leading signal line) to the output side from the set of extracted gates, and a fourth sub-step of reducing the redundant logic in the circuit obtained in the third sub-step.
From the fifth sub-step, it is judged whether or not there is an input pattern in which the output of the one-output circuit is 1 by trying the logic value assignment of the signal line in the circuit obtained in the sub-step and the fourth sub-step. Become. Further, as a result of the judgment in each divided circuit, if the test pattern does not exist in any of the divided circuits, it is judged that the failure is a failure in which the test pattern does not exist in the whole circuit, that is, a principle undetected failure. If a test pattern exists in any of the divided circuits, the fifth test pattern is output.
Perform the step.

[0005]

In the present invention, the target logic circuit is divided into some combinational circuits, and each divided circuit is converted into an equivalent circuit composed of one kind of basic gate. Next, the equivalent circuit is
It is converted into a one-output circuit that outputs a true value only for an input pattern that detects a failure. Further, the EOR logic and the ENOR logic in the one-output circuit are recognized and reduced, and it is determined whether or not there is an input pattern such that the output of the obtained circuit becomes 1. More specifically, target 1
The EOR logic and the ENOR logic in the output circuit are extracted and reduced, and a plurality of gates representing the same logic in the obtained circuit are replaced by one gate. In the circuit thus obtained, 0 or 1 is independently provided. By extracting a set of gates in the circuit that can control the output, such that there is a branch point of the signal line on the input side from this set of gates,
The leading signal line at the boundary between the circuit area reachable from the branch point and the circuit area unreachable from the branch point is updated to the output side from the set of extracted gates, and the redundant circuit in the circuit thus obtained is updated. The logic is simplified, and further, the logic obtained is tried to assign the logic value of the signal line to determine whether or not there is an input pattern in which the output of the one-output circuit becomes 1. As a result, if there is no test pattern for any of the divided circuits, it is determined as a principle undetected failure,
If a test pattern exists in any of the divided circuits, the test pattern is output. In this way, by recognizing the EOR logic and the ENOR logic in the circuit and simplifying the redundant logic in the circuit based on the properties of the EOR logic and the ENOR logic, the principle of undetected failure determination of the logic circuit of the arithmetic unit system It is possible to uniformly grasp the redundancy of the circuit that makes it difficult, eliminate the redundant circuit portion, and efficiently perform the principle undetected failure determination. Moreover, a test pattern can be easily generated using this determination result.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 5 is a configuration diagram of a computer system to which the principle undetected failure determination method of logic circuit and test pattern generation method of the present invention is applied. In FIG. 5, a processing device 10 stores a principle undetected failure determination program 20 which is a processing program of the present embodiment, and an external storage device includes a logic circuit which is a target of the failure determination of the present embodiment. Data 3
0, hypothetical failure table 40, 4 regarding failures in the circuit
5 and the test pattern data 50 which is the output result are stored. The logic circuit data 30 is shown in FIG. 6, and the configurations of the output assumptive failure table 40, the input assumptive failure table 45, and the test pattern data 50 are shown in (a1), (a2), and (b) of FIG. 7, respectively. . Figure 6
The logic circuit data 30 shown in (1) represents the logic circuit to be subjected to the failure determination as the connection relationship between the gates, and the data is stored in a table format. The data corresponding to each gate is composed of fields as described below. The item number (No.) 31 is a number indicating an entry in the table corresponding to each gate. Element (E
LEMENT) 32 is an ID 32a for identifying each gate
And its gate type (KIND) 32b. In the field of the output gate (OUTPUT GATE) 33, the output value 33a of the element 32 and the number of gates connected to the output side of the element 32 (OUT NU
M. ) 33b and IDs 33c and 33d of these gates are stored. Input gate
In the field 34, the number of gates (IN NUM.) 34a connected to the input side of the element 32, IDs (I1, I2 ...) 34b, 34d of these gates, and input values (V1, V2 ...・) 34c and 34e are stored. In the field of control data (CONTROL DATA) 35, the output signal line of the element 32 is a bound signal line,
Information 35a indicating either the head signal line or an unbound signal line other than the head signal line is registered. Number of output stages (PO
The number of gate stages from the output gate of the circuit of the element 32 is registered in the field of LEVEL) 35b. Also,
As an example, each entry in FIG. 6 stores data corresponding to the logic circuit shown in FIG. As shown in FIG. 6, input / output edges are also registered in the logic circuit data 30.

Information output tables relating to faults assumed for diagnosing logic circuits are stored in a table format in the output hypothetical fault table 40 and the input hypothetical fault table 45 shown in (a1) and (a2) of FIG. . This FIG.
In the output assumed failure table 40 of 1), the data corresponding to each output failure is composed of the fields described below. The item number (No.) 41 is a number indicating the entry of the table corresponding to each output failure. The fault (FAULT) 42 is composed of an ID 42a for identifying the output signal line of which gate each output fault is supposed to be and a fault type (KIND) 42b. In the field of the related area (RELATED REGION) 43, the ID 43a of the output gate of the related area including the failure 42, and whether the failure 42 is determined to be a principle undetected failure in the related area having the ID 43a as an output gate, or a test pattern Is stored, or information indicating whether it is in a state in which it is determined that there is an item or whether the determination process has not been performed is stored. In addition, FIG.
In the input assumed failure table 45 of 2), the data corresponding to each input failure is composed of the fields described below. The item number (No.) 46 is a number indicating the entry of the table corresponding to each input failure. The fault (FAULT) 47 is an ID 47a for identifying on which input signal line of each gate each input fault is supposed.
It is composed of an INPUT ID 47b for identifying which input gate the hypothetical fault input signal line of the element 47a is connected to, and a fault type (KIND) 47c thereof. In the field of the related area (RELATED REGION) 48, the ID 48a of the output gate of the related area including the failure 47, and whether the failure 47 is determined to be a principle undetected failure in the related area having the output gate of the ID 48a, or a test pattern Is stored, or information 48b indicating whether or not the state is present, or whether the determination process is not yet performed is stored. Further, the entry of FIG. 7 (a1) has an example of FIG.
Data is stored when the fault included in the logic circuit shown in (a) is regarded as an output fault (0 stuck-at fault of the output signal line of the gate 6b). In the entry of FIG. 7 (a2), as an example, the above failure is input failure (gate 5b
The data is stored when it is regarded as a 0 stuck-at fault of the input signal line 12b. Further, in the test pattern data 50 shown in FIG. 7B, test pattern data obtained as a result of the failure determination of this embodiment, that is, data to be input to the input edge is stored in a table format. The data corresponding to each input edge is composed of fields as described below. Item number (No.) 5
1 is a number indicating the entry of the table corresponding to each input edge. ID52 is an identifier of each input edge.
The set value (VALUE) 53 is a value to be set at the input edge. Case No. (TEST CASE No.)
54 is a number for identifying various test patterns. For the failure (FAULT) 55, the case No. (TE
ST CASE No. ) The entry number 41 in the contingency fault table indicating for which contingency the test pattern 54 is generated is stored. In the entry of FIG. 7B, as an example, data corresponding to the input edge of the logic circuit shown in FIG. 13A described later is stored.

First, a first embodiment of the present invention will be described.
FIG. 1 is a diagram showing the flow of each part of the principle undetected failure determination processing of the logic circuit in the first embodiment of the present invention. 1 represents the target combination circuit X and the target undetected failure f. 1
On the other hand, consider Problem 1 "Is the failure f a principle undetected failure in the circuit X?" 2 is a 1-output combination circuit Y obtained by performing a conversion on the fault f for the 1-target combination circuit X.
Represents On the other hand, considering Problem 2 “Is the output of circuit Y always 0?”, Problem 1 and Problem 2 are equivalent.
2'is a NOR gate, an EOR gate, an ENOR gate,
And an equivalent circuit Y ′ of the two circuits Y composed only of input edges. Considering the problem 2 ′ “Is the output of the circuit Y ′ always 0?” With respect to the 2 ′, the problem 1 and the problem 2 ′ are equivalent problems. Reference numeral 4 represents a process for simplifying the circuit by a reduction process or the like. Reference numeral 5 represents a search for an input pattern in which the output of the circuit becomes 1 due to the logic value assignment trial in the circuit after the reduction processing. This search gives the answer to question 2 '. If the answer to question 2'is YES, the answers to questions 2 and 1 are also YE
If S and the answer to question 2'is NO, then the answers to questions 2 and 1 are also NO.

FIG. 8 is a flow chart showing the outline of the principle undetected failure judgment processing and test pattern generation processing of the logic circuit in the first embodiment of the present invention. Note that this processing is based on the principle undetected failure determination program 20 of FIG. In step 100, the relevant area is examined for all undetected faults. In step 200, it is checked whether or not there is a related area which is not yet the target of the principle undetected failure determination. If it exists, the processing branches to step 300, and if not, the processing branches to step 1100. Step 30
In 0, one related area which is not yet the target of the principle undetected failure determination is selected. In step 400, the related area selected in step 300 is converted into an equivalent circuit composed of only NOR gates and input edges. Step 5
In 00, it is checked whether or not the related area converted in step 400 is a related area having an undetected failure, and the related area is not yet subjected to the principle undetected failure determination. If so, the process branches to step 600, and if not, the process branches to step 200. In step 600, one of the undetected faults included in the related region converted in step 400, which has not been subjected to the principle undetected fault determination for this related region, is selected. In step 700, it is determined whether the target undetected fault selected in step 600 is a theoretical undetected fault in the relevant region converted in step 400. In sub-step 700a of step 700, the output becomes 1 for the test area in the relevant area of the target undetected fault of the related area subjected to the NOR gate conversion in step 400, and for the other input patterns. Convert to a 1-output circuit so that the output becomes 0. Substep 70 of step 700
At 0b, it is determined whether or not the output of the 1-output circuit obtained at sub-step 700a becomes 0 for any input pattern. In step 900, it is checked whether or not it is determined in step 700 that a test pattern can be generated in the relevant area including the target undetected failure. If yes, the process branches to step 1000, and if not, the process branches to step 500. . In step 1000, a test pattern for the target undetected fault is generated. In step 1100, the determination result of each undetected fault in each related area is edited to determine whether each undetected fault is a theoretical undetected fault in the entire circuit.

The steps of FIG. 8 will be described in detail below. FIG. 9 is a detailed flowchart of the related area investigation shown in step 100 of FIG. In step 101, it is checked whether or not there is an undetected failure in which the range of the related area including the undetected failure part has not been checked. If not, the process ends. In step 102, one of the undetected faults, for which the range of the related region including the undetected fault has not been investigated, is selected. In step 103, it is checked whether or not there is a cone that has not been subjected to the related area check for the undetected fault selected in step 102, and if it exists, step 104
If not, the process branches to step 101. Here, the cone is a one-output partial circuit of a partial circuit (combinational circuit) divided on the premise of the scan design method. In step 104, one cone that has not been subjected to the relevant area investigation for the undetected fault selected in step 102 is selected. In step 105, step 102
The gate on the most input side among the gates through which all the paths from the undetected fault location selected in step 4 to the output edge of the cone pass is defined as DM, and the region RG that outputs DM is related. It is a candidate for the area. Step 1
Steps 06 to 109 are processes for determining whether or not the related area candidate can be finally determined as the related area. In step 106, the output destination of the gate DM is sent to step 10
It is checked whether or not the output edge of the cone selected in 4 exists, and if it exists, the region RG is obviously a related region, and therefore the process branches to step 110, and if it does not exist, the process branches to step 107. In step 107, it is checked whether or not the test pattern of the stuck-at-0 fault or the stuck-at-1 fault of the output signal line of the gate DM has been generated. If the test pattern has been generated, the process branches to step 108, and the stuck-at-0 fault occurs. Alternatively, if the test pattern has not been generated for any one stuck-at fault, step 109 is performed.
Branch to. In step 108, it is checked whether or not the fan-out destination gates in the cones of all gates other than the gate DM in the partial circuit RG are included in all the partial circuits RG. If not, the process branches to step 109. In step 109, among the gates through which all the paths from the gate DM to the output edge of the cone pass, the one on the most input side is newly set as DM, and a new related region candidate that outputs this DM is selected. RG. In step 110, the relevant area is determined to be RG.

FIG. 10 is a diagram showing a related area in the first embodiment of the present invention. 1a, 2a, and 3a represent cones including undetected faults, and 4a represents hypothetical failure locations of undetected faults. 5a and 6a represent signal lines, and the signal lines 5a
It is assumed that the 0 stuck-at fault or the 1 stuck-at fault in 6a has been detected. Reference numeral 7a represents a relevant area for the undetected cones 1a and 2a, and 8a represents a relevant area for the cone 3a. In the cone 1a, DM and RG are 9a and 7a, respectively, when the relevant region is determined.
Further, FIG. 11 shows an example of conversion of the equivalent expression of the AND gate, the NAND gate, the OR gate, and the NOR gate used in step 400 of FIG. 8 by the NOR gate.

FIG. 12 is a detailed flowchart of the principle undetected failure determination in the relevant area of the target undetected failure shown in step 700 of FIG. Step 701 is
Corresponding to step 700a in FIG.
2 to 706 correspond to step 700b in FIG. In step 701, the related area converted into the NOR gate in step 400 of FIG. 8 has an output of 1 for the test pattern in the related area of the target undetected fault, and for the other input patterns. Convert to a 1-output circuit so that the output becomes 0. In step 707, EOR logic and ENO in the circuit obtained in step 701
Recognizing the R logic, converting the circuit to an equivalent circuit composed of NOR gate, EOR gate, ENOR gate and input edge, and reducing the EOR gate and ENOR gate in the circuit. In step 702, it is checked whether or not there are two or more gates having the same set of inputs in the circuit converted in step 701, and if they exist, those gates are replaced by one gate. In step 703, the head signal line is updated. Here, among the unbounded signal lines, the one adjacent to the bounded signal line is called a head signal line. An unbound signal line is a signal line that cannot be reached from any branch point in the circuit to the output side.A bound signal line is an output line that is traced from an appropriate branch point in the circuit. A signal line that can be reached as you go. In step 704, circuit simplification processing is performed to simplify complicated parts in the circuit.
In step 705, it is checked during the reduction process of step 704 whether the target undetected fault is determined to be a principle undetected fault in the relevant area, or whether it is determined that a test pattern can be generated. If any determination is made, the process is terminated, and if no determination is made, the process branches to step 706. In step 706, various logic value assignments are made to the circuit subjected to the reduction processing in step 705,
It is determined whether the target undetected failure is a theoretical undetected failure in the relevant area.

FIG. 13 is a diagram showing an example of circuit conversion for the assumed fault shown in step 701 of FIG. FIG.
(A) is a circuit diagram of a related area to be converted. Reference numerals 1b, 2b, 3b, 4b, 5b, and 6b denote NOR gates forming a related region, and 7b, 8b,
It is assumed that 9b, 10b, and 11b represent input edges of the related area, 12b represents a hypothetical fault location of the target undetected fault, and the type of fault is a 1 stuck-at fault. FIG. 13B is a circuit diagram after the conversion regarding the assumed failure location 12b, and 13b represents an output NOR gate of the newly added circuit. FIG.
In (b), the connection between the NOR gates 6b and 5b is separated, and the connection is newly connected between the NOR gates 6b and 13b. The circuit shown in FIG.
In (a), the output of the NOR gate 13b becomes 1 for an input pattern in which a failure signal is set at the assumed failure location 12b, and NO for other input patterns.
It has the property that the output of the R gate 13b becomes zero. FIG. 13C is a circuit diagram after the portion from the assumed failure point 12b to the first branch point is converted, and 14b shows the first branch point from the assumed failure point 12b to the output side. In FIG. 13C, the connection between the input edge 9b and the NOR gate 5b is separated, and the connection is newly connected between the input edge 9b and the NOR gate 13b. FIG. 13 (c)
In the circuit represented by
The output of the NOR gate 13b becomes 1 for an input pattern in which the failure signal is set in b and the failure signal is propagated from the assumed failure location 12b to the branch point 14b, and for other input patterns. Is NOR gate 1
It has the property that the output of 3b becomes 0.

FIG. 13D is a circuit diagram after copying the portion from the branch point 14b to the output of the related area. 15
b, 16b, 17b, 18b, and 19b are each N
The gates are copies of the OR gates 1b, 2b, 3b, 4b, and 5b. Here, for example, the copied portion (NOR
The partial circuit composed of the gates 1b, 2b, 3b, 4b, and 5b) is a copy of the normal circuit (NOR gates 15b, 16b, 17) that takes a logical value when there is no failure.
b), 18b, and 19b) represents a fault circuit that takes a logical value when a fault exists. (Conversely, the copied portion may be regarded as a defective circuit and the copied portion as a normal circuit.) Further, the portion 20b constitutes an exclusive OR. In FIG. 13D, the output logical value of the NOR gate 5b (the input side cut of the normal circuit) is set to 0, and N
The output implication value of the OR gate 19b (the input side cut of the faulty circuit) is set to 1 to perform the forward implication. Logical value is 0 or 1
Signal line connection (output lines of gates 5b and 19b)
And all the input connections connected to the gates (the gates 17b and 18b having the input logical value of 1) having the output logical value of 0 and the input logical value of 1 are present, and the resulting output is floated. When the gate is deleted, the circuit shown in FIG. 13 (e) is obtained. In the circuit shown in FIG. 13 (e), a failure signal is set in the assumed failure point 12b in FIG. 13 (a), and an input in which the failure signal is propagated from the assumed failure point 12b to the output of the related area. The output of the NOR gate 13b becomes 1 for the pattern, that is, the test pattern in the related area of the target assumed fault, and the output of the NOR gate 13b becomes 0 for the other input patterns.

FIG. 14 is a detailed flow chart of the EOR logic extraction in the EOR logic extraction / reduction processing shown in step 707 of FIG. In step 851, the NOR gate E for which it is desired to determine whether the output logic is the EOR logic or the ENOR logic is selected. In step 852, the output logical value of the NOR gate E is set to 1 and the backward implication is performed. As a result of the backward implication, NOR gates whose output logical value is 0 and whose input logical value is 1 do not exist are I ₁ , I ₂ , ...
I _m , and all logical values are returned to X. Step 8
At 53, backward implication is performed with all input logical values of I _i set to 0 (i = 1, 2, ..., M). However, this rearward implication is performed only for a gate having one logic value X. As a result of the backward implication, the NOR gate or the input edge where the output logical value is 0 or 1 and X exists in the input logical value is set as J _i1 , J _i2 , ..., J _{in (i)} , and the backward implication is performed once. Every time it is performed, all the logical values are returned to X. In step 854, m sets {J _i1 , J _i2 , ..., J
It is checked whether or not _{in (i)} } (i = 1, 2, ..., M) is the same set, and if they are the same, J ₁ = J ₁₁ = J
_{21 = ··· = J m1, J} 2 = J 12 = J 22 = ··· = J m2,
.., J _n = J _{1n (1)} = J _{2n (2)} = ... = J _{mn (m)} , the process branches to step 855, and if not the same, the process ends. In step 855, a set of sets of logical values (V ₁ , V ₂ , ..., V _n ) set in the gates J ₁ , J ₂ , ..., J _n by the backward implication of m times in step 853. The GV is examined, and if GV = {(U ₁ , U ₂ , ..., U _n ) | U _i = 1 the number of i is an even number}, the output of the NOR gate E is J
It is determined that the output of ₁ , J ₂ , ..., J _n is EOR logic, and the number of i for which GV = {(U ₁ , U ₂ , ..., U _n ) | U _i = 1 is If the number is an odd number}, the output of the NOR gate E is J
It is determined that the output of ₁ , J ₂ , ..., J _n is ENOR logic. In step 856, NOR in step 855
The output of the gate E is EO of the output of J ₁ , J ₂ , ..., J _n.
If it is determined to be the R logic, the process branches to step 857, and if it is determined that the output of the NOR gate E is the ENOR logic of the outputs of J ₁ , J ₂ , ..., J _n , the step 8 is performed.
The process branches to 58, and if not, the process ends. At step 857, the NOR gate E is used for J ₁ , J ₂ , ...
Replace the logic up to J _n with an EOR gate. At step 858, the NOR gate E is used for J ₁ , J ₂ , ..., J.
Replace the logic up to _n with ENOR gates.

FIG. 15 is a diagram showing a specific example of the EOR logic extraction processing in the EOR logic extraction / reduction processing shown in step 707 of FIG. In FIG. 15, 1s, 2
s, 3s, 4s, 5s, 6s, 7s, 8s, 9s, 10
s, 11s, 12s, and 13s represent NOR gates. Here, the EOR logic determination target gate is the NOR gate 3s. FIG. 15A shows a state in which the output logical value of the NOR gate 3s is set to 1 and the backward implication is performed (step 852 in FIG. 14). Here, step 8 in FIG.
I ₁ , I ₂ , I ₃ , and I ₄ in 52 are NOR gates 4s, 5s, 6s, and 7s, respectively. FIG. 15B shows N
The output logical value of the OR gate 4s (= I ₁ ) is set to 1 to represent the state in which the backward implication is performed (step 853). Here, J ₁₁ , J ₁₂ , and J ₁₃ in step 853 of FIG.
Are NOR gates 11s, 12s, and 13s, respectively. FIG. 15C shows a state in which the output implication value of the NOR gate 5s (= I ₂ ) is set to 1 and the backward implication is performed (step 853). Here, step 853 of FIG.
J ₂₁ , J ₂₂ , and J ₂₃ in FIG.
s, 12s, 13s. FIG. 15D shows a state in which the output implication value of the NOR gate 6s (= I ₃ ) is set to 1 and backward implication is performed (step 853). Here, J ₃₁ , J ₃₂ , and J ₃₃ in step 853 of FIG. 14 are NOR gates 11s, 12s, and 13s, respectively. Figure 1
5 (e) represents a state in which the output implication value of the NOR gate 7s (= I ₄ ) is set to 1 and backward implication is performed (step 853). Here, J in step 853 of FIG.
₄₁ , J ₄₂ and J ₄₃ are NOR gates 11s and 12 respectively.
s and 13s. Where {J ₁₁ , J ₁₂ , J ₁₃ } =
_{{J 21, J 22, J} 23} = {J 31, J 32, J 33} =
It can be seen that {J ₄₁ , J ₄₂ , J ₄₃ } = {11s, 12s, 13s} (step 854). Also, FIG.
The set of logical value sets set at the outputs of the NOR gates 11s, 12s, and 13s by the four backward implications in (b), (c), (d), and (e) is {(0, 0, 0). ), (0, 1,
1), (1, 0, 1), (1, 1, 0)}, which is the same set as {(U ₁ , U ₂ , U ₃ ) | U _i = 1 is an even number} Is. Therefore, the output of the NOR gate 3s is determined to be equivalent to the EOR logic of the NOR gates 11s, 12s and 13s (step 856). Figure 15
(F) shows NOR gate 3s to NOR gate 11s,
This shows a circuit in which the logic up to 12s and 13s is replaced by the EOR gate 14s (step 857).

FIG. 16 shows a reduction example of the EOR gate and the ENOR gate in the EOR logic extraction / reduction processing shown in step 707 of FIG. In addition, in FIG.
A specific example of the process of putting together the common logic shown in step 702 of FIG. In FIG. 17A, 1c, 2c, 3
c, 4c, 5c, 6c, and 7c represent NOR gates. Here, both NOR gates 4c and 5c are NOR
It has gates 6c and 7c as fan-in destination gates. Therefore, since the NOR gates 4c and 5c have the same input relationship, the NOR gates 4c and 5c can be integrated into one. FIG. 17B shows the NOR gate 6
c, 7c and 5c and NOR gates 5c and 2
17c is disconnected from the NOR gates 4c and 2c and 3c.
This shows a circuit in which the R gate 5c is replaced with 4c.

FIG. 18 is a detailed flowchart for updating the head signal line shown in step 703 of FIG. Here, among the unbounded signal lines, the one adjacent to the bounded signal line is called a head signal line. An unbound signal line is a signal line that cannot be reached from any branch point in the circuit to the output side.A bound signal line is an output line that is traced from an appropriate branch point in the circuit. A signal line that can be reached as you go. In step 711, it is checked whether or not there is a head signal line having a branch that has not been checked for the possibility of updating the head signal line. If it exists, the process branches to step 712. The process ends.
In step 712, one of the head signal lines having a branch that has not been investigated for the possibility of updating the head signal line is selected, and this head signal line is set to H. Step 7
In 13, the forward implication is performed by setting the logical value of the head signal line H to 0. In step 714, all the gates of the output logical value X (where the input logical value has changed but the output logical value has not changed to X) due to the forward implication are all independent of each other. The logical value of the output signal line to 0
Or whether the gate can be controlled to 1, that is,
It is checked whether the input edge can be traced through the gate of the output logical value X having no branch point, and if traced, step 71
If not, the process branches to step 718.
In step 715, the connection of the signal line having a logical value of 0 or 1 is disconnected. In step 716, the gate connected to the bound signal line whose output floated during the process of step 715 is deleted. In step 717, the head signal line H
Justify the logical value of. Here, the justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the signal line as the output signal line matches the logical value of the signal line. Step 71
At 8, it is checked whether the logical value of the head signal line H is 1, and 1
If so, the process branches to step 719, and if not 1, the process branches to step 720. In step 719, the top signal line H
Perform a forward implication by setting the logical value of X to X. Step 72
At 0, the logical value of the head signal line H is set to X to perform forward implication. In step 721, the logical value of the head signal line H is set to 1 to perform forward implication. Then step 714
Repeat the process from.

FIG. 19 is a diagram showing an example of updating the head signal line shown in step 703 of FIG. In FIG. 19A, 1d, 2d, 3d, 4d, 5d, 6d, 7d,
And 8d are NOR gates, 9d, 10d, 11d, 1
2d and 13d are the input edges, 14d, 15d, 1
6d, 17d, and 18d represent signal lines. Here, the leading signal lines are the signal lines 14d, 15d, 16d, and 17d.
Therefore, the signal line 14d has a branch, and the signal lines 15d and 16
d and 17d have no branch. FIG. 19B shows a state in which the output logical value of the head signal line 14d having a branch is set to 0 and the forward implication is performed (step 713 in FIG. 18). Here, forward implication becomes impossible, and the output logical value is X.
NOR gates 2d, 3d, and 4d do not have branches from 2d to input edge 9d, 3d to input edge 10d, and 4d to input edge 11d, and the input edge passes through the gate whose output logical value is X. The outputs of the NOR gates 2d, 3d, and 4d can be controlled to 0 or 1 independently of each other. FIG. 19 (c)
19B shows a state in which the connection of the signal line having a logical value of 0 or 1 in FIG. That is, in FIG. 19B, the signal lines 12d,
19 is assigned to the logical value of the signal line 12d so that the NOR operation result of the logical value of 13d becomes equal to the logical value 0 of the signal line 14d, for example, as shown in FIG. Note that FIG.
In FIG. 9 (c), the first signal line is only the signal line 18d,
The top signal lines are the signal lines 14d, 15d, 1 of FIG.
The signal lines 18d on the output side are updated from 6d and 17d.

FIG. 20 is a detailed flowchart of the reduction processing of the circuit shown in step 704 of FIG. The reduction processing of the circuit in this embodiment includes three types of reduction processing, that is, reduction processing A1, reduction processing A, and reduction processing B. In the reduction process A1, redundant logic on the input side of the output gate of the circuit is reduced. In the reduction process A, the redundant logic on the input side of the multi-input gate (excluding the output gate of the circuit) of the circuit is reduced. In the reduction process B, the influence of the logical value of the head signal line on the output logical value of the circuit is examined, and when the logical value of the head signal line is 0, the logical value has only the influence of trying to set the output of the circuit to 1. Then, if the logic value of the head signal line is fixed by assigning 0, and the logic value of the head signal line is 1, the logic value has only the effect of trying to set the output of the circuit to 1. It is fixed by assigning 1 to the logical value of.
In step 731 of FIG. 20, it is checked whether or not there is a multi-input gate capable of performing the reduction processing A. If it exists, the process branches to step 732, and if it does not exist, the process branches to step 737. In step 732, the multi-input gate R capable of the reduction processing A is selected. In step 733, it is checked whether the multi-input gate R is the output gate of the circuit, and if so, the process branches to step 734, and if not, step 73.
Branch to 5. In step 734, the reduction process A1 is performed for the multi-input gate R. In step 735, the reduction process A is performed for the multi-input gate R. Step 736
Then, in the middle of the reduction process A1 or the reduction process A, is it determined whether the target undetected fault is a theoretical undetected fault in the relevant area or a test pattern can be generated? Is checked, and if any of them is determined, the process is ended, and if none of them is determined, the process branches to step 731. Step 737
Then, it is checked whether or not there is a leading signal line that can be subjected to the reduction processing B. If it exists, the process branches to step 738, and if it does not exist, the processing ends. Among the unbound signal lines, the one that is adjacent to the bound signal line is called the head signal line. An unbound signal line is a signal line that cannot be reached from any branch point in the circuit to the output side.A bound signal line is an output line from an appropriate branch point in the circuit. A signal line that can be reached by following it. In step 738,
A leading signal line H capable of the reduction processing B is selected. In step 739, the reduction process B is performed on the head signal line H.
In step 740, in the middle of the reduction process B, the target undetected fault is a theoretical undetected fault in the relevant region,
Alternatively, it is checked whether or not it is possible to generate a test pattern, and if either is determined, the process is ended, and if neither is determined, the process branches to step 741. To do. In step 741, it is checked whether or not there is a new head signal line that can be subjected to the reduction processing B. If it exists, the process branches to step 738, and if it does not exist, the process branches to step 742. Step 74
In step 2, it is checked whether or not there is a multi-input gate capable of the reduction processing A. If it exists, the process branches to step 732, and if it does not exist, the processing ends.

FIG. 21 is a detailed flowchart of the reduction process A1 shown in step 734 of FIG. In step 751, the output logical value of the multi-input gate R is set to 1 and an implication operation is performed. However, the implication operation is not performed on the unbound signal line. In step 752, a contradiction occurs during the implication operation (2 of 0 and 1 via different paths during the implication operation).
It is checked whether or not a situation in which two values are about to be set in the same signal line) has occurred. If so, the process branches to step 758, and if not, the process branches to step 753. In step 753, a gate having an output logical value of 0 and an input logical value of 0 or X and a gate having a leading signal line having a logical value of 0 or 1 as an output signal line are registered as termination gates (including input edges). To do. In step 754, the connection of the signal line whose logical value is 0 or 1 is disconnected. Step 755
Then, for each terminal gate, if the output signal line is the head signal line, the output logical value is justified up to the input edge, and if the output signal line is a bound signal line and the number of inputs is 1 or more. A wire is connected between the terminal gate and the multi-input gate R. Here, justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the signal line. is there. In step 756,
Whether or not the number of inputs of the multi-input gate R is 0 is checked. If 0, the process branches to step 757, and if not 0, the process branches to step 759. In step 757, it is assumed that the target undetected fault can generate a test pattern in its related area. In step 758, the subject undetected fault is determined to be a theoretical undetected fault in its associated area. In step 759, the floating gate whose number of outputs becomes 0 during processing is deleted. In step 760, the logical value is 0 or 1.
All logic values of the signal line of are returned to X.

FIG. 22 is a diagram showing an example of the reduction processing A1 shown in step 734 of FIG. In FIG. 22A, 1e, 2e, 3e, 4e, 5e, 6e, 7e, 8
e and 9e are NOR gates, 10e, 11e, 12
e, 13e, and 14e represent input edges. here,
The multi-input gate that is the target of the reduction process A1 is NOR
It is the gate 1e. FIG. 22B shows the NOR gate 1e.
The output logical value of 1 is set to 1 to represent the implication (step 751 in FIG. 21). Here, NOR gate 8
e, 9e, and the input edge 10e are termination gates (step 753). FIG. 22C shows connection of signal lines having logical values of 0 or 1 (1e and 2e, 1e and 3e, 1e and 4e, 2e and 8e, 2e and 6e, 3e and 5e, 4e and 6).
e, 5e and 8e, 5e and 10e, 6e and 9e, and 6e
And 10e) is disconnected (step 75
4), connection processing of the termination gates 8e and 9e (step 7)
55) and the floating gates 2e, 7e, and 11e are deleted (step 759).

FIG. 23 is a detailed flowchart of the reduction process A shown in step 735 of FIG. In step 771, the output logical value of the multi-input gate R is set to 1 to perform backward implication. However, no implication is applied to the unbound signal line. In step 772, it is checked whether or not an inconsistency (a situation in which two values of 0 and 1 are set to the same signal line via different paths during implication operation) occurs during implication. If not, the process branches to step 773. Step 77
In 3, the gate having the output logical value of 0 and the input logical value of 0 or X and the gate having the leading signal line of the logical value of 0 or 1 as the output signal line are registered as the termination gates. In step 774, the circuit on the output side from the termination gate is separated into a part that converges on the multi-input gate R and a part that does not converge. In step 775, forward implication is performed from the termination gate in the part where the termination gate converges to the multi-input gate R. However, no implication is made on the output side of the multi-input gate R. In step 776, it is checked whether a contradiction occurs during the forward implication, and if so, step 77.
9; otherwise, to step 777. In step 777, the connection of the signal line having a logical value of 0 or 1 is disconnected from all the input connection of the gate having an output logical value of 0 and having an input logical value of 1 exists. In step 778, for each termination gate, if this termination gate has an output logic value of 0 and the number of inputs is 1 or more, or if the output signal line of this termination gate is a leading signal line with a logic value of 0, A wire is connected between the terminal gate and the multi-input gate R. Further, if this termination gate has an output logical value of 1 and the number of inputs is 1 or more, or if the output signal line of this termination gate is a leading signal line with a logical value of 1, then NOR is newly added.
A gate N is added, and wiring is connected between the termination gate and the NOR gate N and between the NOR gate N and the multi-input gate R. In step 779, the output logical value of the multi-input gate R is set to 0 to perform the forward implication. In step 780, among the signal lines on the output side of the multi-input gate R, the connection of the signal line whose logical value is 0 or 1 is disconnected. In step 781, the floating gate whose output number is 0 during the above processing is deleted. In step 782, the output logical value of the circuit is checked, and if 0, it branches to step 783, if 1 branches to step 784, and if X branches to step 785. In step 783, the target undetected fault is determined to be a theoretical undetected fault in its associated area. In step 784, it is determined that the target undetected fault can generate a test pattern in its related area. In step 785, all the logical values of the signal line whose logical value is 0 or 1 are returned to X.

FIG. 24 is a diagram showing an example of the reduction processing A shown in step 735 of FIG. In FIG. 24A, 1f, 2f, 3f, 4f, 5f, 6f, 7f, 8
f and 9f represent NOR gates. Here, the multi-input gate R that is the target of the reduction process A is the NOR gate 2
f. FIG. 24 (b) shows a state in which the output logical value of the NOR gate 2f is set to 1 and the backward implication is performed (FIG. 2).
3 step 771). Here, the termination gates are NOR gates 4f, 7f, and 8f (step 773).
FIG. 24C shows a state in which the circuits from the NOR gates 4f, 7f, and 8f to the output side are separated into a portion that converges on the NOR gate 2f and a portion that does not converge (step 77).
4). In FIG. 24C, NOR gates 10f and 11f are newly added to separate the circuit. Figure 24
(D) shows the NO gates from the NOR gates 4f, 7f, and 8f.
In the portion that converges on the R gate 2f, the NOR gate 4
It represents a state in which the forward implication is performed from f, 7f, and 8f (step 775). In FIG. 24 (e), the connection of signal lines whose logical value is 0 or 1 and the output logical value are 0, and
This shows a state in which all the input connections of the gate having an input logical value of 1 are disconnected (step 777), the processing of the termination gate (step 778) and the removal of the floating gate (step 781) are performed.

FIG. 25 is a detailed flowchart of the reduction process B shown in step 739 of FIG. In step 801, it is checked whether or not the EOR gate and the ENOR gate are included in any of the paths from the head signal line H to the output of the circuit. If they are not included in any of the paths, the process branches to step 791. If it is included in any of the routes, the process ends. In step 791, it is checked whether or not all paths from the head signal line H to the output of the circuit are composed of an even number of gates (including input edges), and if they are, branch to step 792 to configure. If not, the process branches to step 793. Step 7
At 92, the output logical value of the head signal line H is set to 0 to perform the forward implication. In step 793, it is checked whether or not all the paths from the head signal line H to the output of the circuit are composed of an odd number of gates (including input edges), and if they are structured, the process branches to step 794 to configure. If not, the process ends. In step 794, the logical value of the head signal line H is set to 1 to perform forward implication. In step 795, the connection of the signal line whose logical value is 0 or 1 is disconnected. In step 796, the logical value of the head signal line H is justified. Here, the justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the signal line. That is. In step 797, the floating gate whose output number is 0 during the processing is deleted. At step 798, the output logical value of the circuit is 0.
If so, branch to step 799; if 1 then step 80
The process branches to 0, and if X, the process ends. Step 799
Then, the target undetected failure is determined to be a principle undetected failure in the relevant area. In step 800, the target undetected fault is determined to be capable of generating a test pattern in its related area.

FIG. 26 is a diagram showing an example of the reduction processing B shown in step 739 of FIG. In FIG. 26A, 1g, 2g, 3g, 4g, and 5g represent NOR gates, 6g and 7g represent input edges, and 8g represents signal lines. Here, the head signal line H that is the target of the reduction processing B is the signal line 8g, and there are two paths from the signal line 8g to the output of the circuit, that is, the input edge 7g-> N.
OR gate 4g-> NOR gate 2g-> NOR gate 1g and input edge 7g-> NOR gate 5g-> NO
Each of the R gate 3g-> NOR gate 1g is composed of four gates including the input edge 7g. When the logical value of the head signal line 8g is 0, the output logical values of the NOR gates 4g and 2g tend to be 1 and 0, respectively, and the output logical values of the NOR gates 5g and 3g are 1 and 0, respectively. Therefore, the logical value of the NOR gate 1g tends to be 1. On the contrary, when the logic value of the signal line 8g is set to 1, the logic value of the NOR gate 1g tends to become 0. If the output of the circuit obtained by fixing the logic value of the signal line 8g so that the output logic value of the NOR gate 1g, that is, the output logic value of the circuit is 1, is always 0, the output of the original circuit is always 0. have. FIG. 26B shows a state in which the logical value of the signal line 8g is set to 0 and the forward implication is performed (step 792). In FIG. 26C, the connection of the signal line whose logical value is 0 or 1 in FIG.
Step 795), floating gates (gates 2g and 4g)
Is deleted (step 797).

FIG. 27 is a detailed flowchart of the judgment by the logical value allocation trial shown in step 706 of FIG. In step 811a, step 70 in FIG.
The implication operation is performed by setting 1 to the output logical value of the circuit obtained in 4. During the implication operation, it is checked each time whether the output signal line of each gate that is the target of the implication operation is an unjustified signal line, and if it is an unjustified signal line, the output signal line is registered. Here, the unjustified signal line is an output signal line of a gate such that the operation result of the input logical value does not match the output logical value. In Step 812a, Step 8
The unjustified signal lines generated by the implication operation of 11a are justified up to the head signal line, and if all the unjustified signal lines are justified, it is determined that the test pattern of the target undetected failure exists. On the other hand, if the justification is not successful no matter how the logical value is assigned, it is judged that the target undetected fault is a theoretical undetected fault in the relevant area. Here, the justification is to determine the logical value up to the head signal line so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the target signal line. In step 813a, if it is determined in step 812a that the test pattern exists, the process branches to step 814a, and if not determined, the process ends. In step 814a, the leading signal line whose logical value is set to either 0 or 1 is justified up to the input edge. Here, the justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the target signal line.

FIG. 28 is a detailed flowchart of the justification for the unjustified signal line shown in step 812a of FIG. In step 821a, 0 is set to the contradiction flag. The contradiction flag indicates whether or not a contradiction (a situation in which two values of 0 and 1 are about to be set on the same signal line via different routes during the implication operation) in the implication operation of steps 826a and 830a. The contradiction flag is 0, which means that there is no contradiction, and the contradiction flag is 1, which means that the contradiction has occurred. In step 822a, if the contradiction flag is 0, the process branches to step 823a.
Branch to 8a. In step 823a, if there is an unjustified signal line in the circuit, the process branches to step 824a; otherwise, the process branches to step 827a. At step 824a, one is selected from the registered unjustified signal lines. In step 825a, backward tracing is performed using the unjustified signal line selected in step 824a as a starting point. In the backward tracing, the signal line having the logical value X is traced from the signal line which is the starting point toward the input side,
Set a logical value in the signal line at the location where the tracking was terminated. In step 826a, an implication operation is performed based on the logical value set in step 825a. In step 827a, it is determined that there is a test pattern in the relevant area of the target undetected failure. In step 828a, backtracking for resolving the contradiction is performed. In step 829a,
If it is determined in step 828a that the target undetected failure is a principle undetected failure, the process ends. If not, the process branches to step 830a. In step 830a, an implication operation is performed based on the logical value of the signal line changed in the process of the back track 828a.

FIG. 29 is a detailed flowchart of the backward tracking shown in step 825a of FIG. In step 831a, a gate whose output signal line is an unjustified signal line is set as a target gate UIOBJN for backward tracing, and a logical value of the unjustified signal line is set to a target value UIOBJL.
In step 832a, if the output signal line of UIOBJN is the head signal line, the process branches to step 834a, and if it is not the head signal line, the process branches to step 833a. Step 83
In 3a, the input gate for UIOBJN,
In addition, one gate whose output logic value is X is selected, the selected input gate is set as UIOBJN, and UIOBJN is updated. If the UIOBJN before update is a NOR gate, the value of UIOBJL is inverted (0-> 1, 1->).
0) to update the value of UIOBJL,
UIOBJN before update is EOR gate or ENOR
In the case of a gate, if it is easier to control the output of the updated UIOBJN from 1 to 0, UIOBJL is set to 0, otherwise UIOBJL is set to 1
Update the value of BJL. However, when the UIOBJN before update has an EOR gate and the number of inputs having a logical value of X is one, the UIOBJL is updated to a value obtained by EORing all the input logical values of the UIOBJN before update that are not X and UIOBJL. If the previous UIOBJN is an ENOR gate and the number of inputs whose logical value is X is 1, the UIOBJN before update is
UIOBJL is updated to a value obtained by performing an OR operation on all input logical values other than X and UIOBJL. Step 834a
Then, the value of UIOBJL is set to the output logical value of UIOBJN. In step 835a, the ID of UIOBJN is stacked on a predetermined stack provided in the processing device 10.

FIG. 30 is a detailed flowchart of the backtrack shown in step 828a of FIG. In step 841a, it is checked whether or not the stack is empty. If the stack is empty, the process branches to step 847a, and if not, the process branches to step 842a. In step 842a, it is checked whether or not the logic value of the gate corresponding to the ID stacked on the top of the stack has been inverted, and if inverted, the process branches to step 843a. To do. In step 843a, the output logic value of the gate corresponding to the ID stacked on the top of the stack is returned to X. In step 844a, an implication operation is performed.
In step 845a, the gate is removed from the stack, i.e., the ID stacked on top of the stack is removed. In step 846a, the output logical value of the gate corresponding to the ID stacked on the top of the stack is inverted (0->
1, 1-> 0). In step 847a, it is determined that the target undetected failure in the relevant area is the principle undetected failure.

FIG. 31 is a diagram showing an example of determination processing by the logical value allocation trial shown in step 706 of FIG. In FIG. 31, 1r, 2r, 3r, 4r, 5r,
6r and 7r each represent a NOR gate, 8r represents an input edge, and 9r, 10r, 11r, 12r, 1
3r, 14r, and 15r all represent signal lines. 31A shows a circuit in which the output logical value of the circuit obtained in the reduction processing 704 shown in FIG. 12 is set to 1 and the implication operation is performed (step 811a in FIG. 27). Here, since the output logical values of the NOR gates 2r and 3r whose output signal lines are the signal lines 9r and 10r are 0 and the input logical values are all X, the signal lines 9r and 10r are both unjustified. It is a signal line. 31B is a diagram in which 9r is selected from the unjustified signal lines included in the circuit shown in FIG. 31A to perform the backward tracking (step 824 of FIG. 28).
a, step 825a). Here, (rear tracking target gate, target value) is (2r, 0)-> (4r, 1)->
(6r, 0)-> (8r, 1) are sequentially updated (Fig. 2
Step 833a of 9). FIG. 31C is a diagram showing the result of performing the implication operation 826a by setting the final target value 1 in the final target gate 8r for backward tracking (step 834a). Here, the gate 8r for which the logical value is set is stacked on the stack (step 835a). Here, the output logical value of the NOR gate 3r is 0, but the NOR operation result of the input logical values 0 and 0 is 1, and thus the logical values are inconsistent. 31D is a diagram showing a result of backtracking and implication operations performed on the circuit shown in FIG. 31C (steps 828a and 82 in FIG. 28).
9a). The logical value of the gate 8r stacked on the top of the stack is inverted from 1 to 0 (step 846 in FIG. 30).
a) When the implication operation is performed, a contradiction occurs in the NOR gate 2r this time. FIG. 31 (e) is a diagram showing a result of backtracking further performed on the circuit of FIG. 31 (d).
Since the gate 8r stacked on the top of the stack has already undergone the logic value inversion, the logic value is returned to X (step 843).
a), the implication operation is performed (step 844a), and the target gate for the next backtrack is searched. However, since the stack is empty, the target undetected fault is determined to be a theoretical undetected fault in the relevant area. Yes (step 847)
a).

FIG. 32 is a detailed flowchart showing an alternative method of backward tracking shown in step 825a of FIG. Steps 831b, 833b, 834 shown in FIG.
b and 835b are steps 831a and 831a shown in FIG.
It is the same as 833a, 834a, and 835a. In this embodiment, the backward tracking is terminated by updating the target gate (UIOBJN) and the target value (UIOBJL) only once.

FIG. 33 is a detailed flowchart of the test pattern generation shown in step 1000 of FIG.
In step 1008, the leading signal line whose output logical value becomes 0 or 1 during the processing in step 700 of FIG. 8 is justified up to the input edge. Here, the justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the signal line. That is. In step 1009, the test pattern in the relevant area of the generated target undetected fault is assigned to the input of the relevant area, and the output of the output gate of the relevant area to the input outside the relevant area in the entire logic circuit. A test pattern (already generated) in the entire circuit with 0 stuck-at fault or 1 stuck-at fault of the signal line is assigned and merged.

FIG. 34 is a detailed flowchart for editing the judgment result shown in step 1100 of FIG. In step 1101, it is checked whether or not there is an undetected fault for which the determination result has not been edited. If it exists, the process branches to step 1102. If not, the process ends. In step 1102, one undetected fault for which the determination result has not been edited is selected. Step 1103
Then, it is checked whether or not the undetected fault is determined to be the principle undetected fault in all the relevant areas including the undetected fault selected in step 1102, and if it is determined, the process branches to step 1104 to determine If not, the process branches to step 1105. In step 1104, the undetected fault selected in step 1102 is determined to be a theoretical undetected fault in the entire circuit. In step 1105, it is checked whether or not the test pattern of the undetected fault selected in step 1102 is generated. If it is generated, the process branches to step 1106, and if it is not generated, the process branches to step 1107. In step 1106, it is determined that the undetected fault selected in step 1102 has successfully generated the test pattern. In step 1107, it is determined that it has not been possible to determine whether the undetected failure selected in step 1102 is a theoretical undetected failure.

Next, a second embodiment of the present invention will be described.
In this embodiment, the principle undetected failure determination process and test pattern generation process of a logic circuit are performed with the same system configuration as that of the first embodiment. Although these processes are based on the procedure shown in FIG. 8, in step 400 of FIG. 8, NAND conversion of the related area is performed instead of NOR conversion of the related area. In the following, a change unit (first
Only the part different from the embodiment of FIG. Fig. 35
Is the NAND of the related area in the second embodiment of the present invention.
It is a figure which shows the conversion of the equivalent expression used by conversion. Figure 3
5 is the NAN of the related area shown in step 400 of FIG.
It is a conversion example of an equivalent expression used in D conversion, and
N, ND, NAND, OR, and NOR gates
It is expressed by a combination of AND gates. Further, in step 701 shown in FIG. 12 (details of step 700 in FIG. 8), the output becomes 0 for the test pattern in the relevant area of the target undetected fault in the relevant area that has undergone the NAND gate conversion, For other input patterns, the output pattern is converted into a one-output circuit that outputs 1. The details of the updating of the head signal line shown in step 703 of FIG. 12 are the same as those shown in FIG. 18, and the details of the circuit simplification processing shown in step 704 are the same as those shown in FIG. 20, respectively. Further, among the unbound signal lines, the one adjacent to the bound signal line is called a head signal line. What is an unbounded signal line?
A signal line that can not be reached from any branch point in the circuit to the output side, and a bound signal line is a signal that can be reached by tracing from the appropriate branch point in the circuit to the output side. It is a line. In addition, FIG. 14 (step 70 in FIG. 12)
In step 852 shown in (Details of 7), instead of setting the output logical value of E to 1 and performing the backward implication, setting the output logical value of E to 0 and performing the backward implication. Also, in step 853, instead of setting all input logical values of I to 0 and performing backward implication, set all input logical values of I to 1 and performing backward implication. Further, in step 751 of FIG. 21 (details of step 734 in FIG. 20), the implication is performed by setting the logical value of R to 0 instead of setting 1 to the logical value of R and performing implication. Also, in step 771 of FIG. 23 (details of step 735 in FIG. 20), instead of setting the logical value of R to 1 and performing backward implication, the logical value of R is set to 0.
Is set to perform implication backwards, and in step 779,
Instead of setting the logical value of R to 0 and performing forward implication, setting the logical value of R to 1 and performing forward implication. Further, in step 783, it is determined that a test pattern can be generated instead of determining that the target undetected fault is a principle undetected fault in the relevant area, and in step 784, the target undetected fault is the test pattern. Is determined to be a principle undetected failure, instead of determining that generation is possible. Further, in step 792 of FIG. 25 (details of step 739 of FIG. 20), instead of setting the logical value of H to 0 and performing forward implication, setting the logical value of H to 1 and performing forward implication, In 794, instead of setting the logical value of H to 1 and performing the forward implication, setting the logical value of H to 0 and performing the forward implication. Further, in step 799, it is determined that a test pattern can be generated instead of determining that the target undetected fault is a principle undetected fault in the relevant area, and in step 800, the target undetected fault is the test pattern. Is determined to be a principle undetected fault in the relevant area instead of being determined to be possible. 27 (step 70 in FIG. 12).
In step 811a (details of 6), instead of setting the output logic value of the output gate of the circuit to 1 and performing the implication operation, the output logic value of the output gate of the circuit is set to 0 and the implication operation is performed. 28 and 2 showing the first embodiment.
Regarding FIG. 9, FIG. 30, FIG. 32, FIG. 33, FIG. 34, etc., the same processing as these is performed in this embodiment.

Next, a third embodiment of the present invention will be described.
FIG. 36 is a diagram showing an outline of the principle undetected failure determination processing of the logic circuit including the uncertain input edge according to the third embodiment of the present invention. Other than 21, it is the same as that shown in FIG. For Problem 1, consider Problem 1 "Is the failure f a principle undetected failure in the circuit X?" Reference numeral 2 represents a one-output combination circuit Y obtained by converting the combination circuit X, which is the target of 1, with respect to f. On the other hand, considering Problem 2 “Is the output of circuit Y always 0?”, Problem 1 and Problem 2 are equivalent. Reference numeral 21 is a 1-output combination circuit Y ′ that does not include any uncertain input edges obtained by converting the 2-output 1-output combination circuit.
Represents Considering the problem 3, “Is the output of the circuit Y ′ always 0?”, The problems 2 and 3 are equivalent. Three
Represents an equivalent circuit Y ″ of 21 circuits Y ′ composed of NOR gates, EOR gates, ENOR gates, and input edges only. Considering the problem 3 ′ “Is the output of the circuit Y ″ always 0?” With respect to 3, the problems 3 and 3 ′ are equivalent problems. Reference numeral 4 represents a process for simplifying the circuit by a reduction process or the like. Reference numeral 5 represents a search for an input pattern in which the output of the circuit becomes 1 due to the logic value assignment trial in the circuit after the reduction processing. This search gives the answer to question 3 '. If the answer to question 3'is YES, the answers to questions 3, 2 and 1 are also YES, and if the answer to question 3'is NO, then question 3
The answer to question 2 and question 1 is also NO.

In the present embodiment, the flow of the principle undetected failure determination processing in the logic circuit is the same as the flow chart of FIG. 8 shown in the first embodiment. FIG. 37 is a detailed flowchart of the principle undetected failure determination in the relevant area of the target undetected failure shown in step 700 of FIG. 37, the processes other than step 720 are the same as those in FIG. That is, in step 720, in step 7
The circuit obtained in 01 is converted into a circuit that does not include an uncertain input edge. The uncertain input edge refers to an input edge that cannot be determined to be 0 or 1, and is hereinafter referred to as a U input edge.

FIG. 38 is a detailed flowchart of the circuit conversion for removing the U input edge in step 720 of FIG. In this embodiment, two types of circuit conversions A2 and B1 are performed to remove the U input edge. The output destination gate can be set to 0 or 1 regardless of the principle of undetected failure determination and test pattern generation processing (that is, 0 or 1).
A correct judgment result can be obtained even if the principle undetected failure judgment is performed on the circuit for which the setting is made, and a correct test pattern can be obtained even if the test pattern is generated. ). The circuit conversion for removing the U input edge is called circuit conversion A2. Furthermore, for the U input edge that could not be removed by the circuit conversion A2, U
A circuit conversion B1 is a circuit conversion for removing these U input edges by synthesizing a circuit in which 0 is set in the input edge and a circuit in which 1 is set. Step 72
In step 1, it is determined whether or not there is a U input edge in the circuit to be handled, and if it exists, the process proceeds to step 722. It should be noted that the presence or absence of the U input edge can be checked by checking the presence or absence of a gate in the logic circuit data shown in FIG. 6 in which the gate type 32b is the input edge and the output logical value 33a is an uncertain value. You can In step 722, it is checked whether or not there is a U input edge for which the circuit conversion A2 is not executed. If it exists, the process branches to step 723, and if it does not exist, the process branches to step 724. In step 723, circuit conversion A2 of the U input edge is performed. In step 724, it is checked whether or not the U input edge exists, and if it exists, the process branches to step 725, and if it does not exist, the processing ends. Step 725
Then, the circuit conversion B1 of the U input edge is performed.

FIG. 39 is a detailed flowchart of the circuit conversion A2 shown in step 723 of FIG. In step 723a, it is checked whether or not there is any output gate of the target U input edge which has not been checked yet. In step 723b, one of the output gates of the U input edge that has not been examined is selected. In step 723c,
Check whether there is any input gate other than the U input edge in the output gate selected in step 723b,
If it exists, the process branches to step 723d, and if it does not exist, the process branches to step 723h. In step 723d,
One of the input gates of the output gates selected in step 723b other than the U input edge is selected. Step 72
In 3e, it is checked whether the logic value of the input gate selected in step 723d is X and whether the input gate is an unbounded signal line or a leading signal line having no branch, and the condition is satisfied. If yes, step 723f
If the condition is not satisfied, the process branches to step 723c. In step 723f, a logical value is set in the input gate selected in step 723d. Step 723
In f, if the circuit is composed of a NOR gate and an input edge, the logical value is set to 1, and the circuit is set to N.
If it consists of AND gate and input edge,
Set 0 as a logical value. In step 723g, the logic value set in the selected input gate is justified up to the input edge. Here, the justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the target signal line. On the other hand, step 723h
Then, the implication operation is performed based on the logical value set in step 723f. In step 723i, the logical value is 0 or 1.
Disconnect the connection of the signal line that is set to either of. At step 723j, the gate whose output is floating is deleted.

FIG. 40 is a diagram showing a circuit conversion A2 in the third embodiment of the present invention. In FIG. 40 (a),
U1 represents the U input edge and I1 and G1 represent the NOR gate. Further, by setting the logical value of I1 to 1, the logical value of the output destination gate G1 of U1 can be controlled to 0. Further, since I1 is an unbounded signal line, setting the logic value of I1 to 1 only controls the logic value of G1 to 0, and does not affect other circuit parts. FIG. 40 (b) shows
In FIG. 40A, the logical value of I1 is set to 1 and the forward implication operation is performed to justify the logical value of I1 up to the input edge (step 723f, step 723g of FIG. 39,
(Step 723h), the connection of the signal line which is set to a value of 0 or 1 is disconnected (Step 723i), and the gate whose output is floating is deleted (Step 723j).
The obtained circuit is shown. In FIG. 40B, the U input edge U1 has been removed. The circuit conversion A2 is shown in FIG.
A specific example of a U input edge that cannot be used is shown below. Fig. 40 (c)
At, U2 represents the U input edge and I2, G2, and G3 represent the NOR gates. Also, set the logical value of I2 to 1
Setting the output destination gate G2 of U2 to 0. However, if the logical value of I2 is set to 1, the logical value of the NOR gate G3 other than G2 is affected, so that the circuit conversion A2 for U2 is impossible.

FIG. 41 is a detailed flowchart of the circuit conversion B1 shown in step 725 of FIG. In step 725a, it is checked whether or not the U input edge exists, and if it exists, the process branches to step 725b, and if it does not exist, the processing ends. At step 725b, one U input edge is selected. In step 725c, the circuit on the output side as viewed from the target U input edge selected in step 725b is copied. The copy operation is performed as follows.
First, one copy gate is created for each of all the gates that can be traced from the target U input edge selected in step 725b and except the output gate of the circuit. Further, as described below, the input signal line of each copy gate is connected. An input signal line is connected between the copy gate A ′ of the gate A and all the input gates of A or the copy gates of the input gates. here,
If A's input gate B has a copy gate (ie, B is reachable from the target U input edge), connect a signal line between B's copy gates B'and A ', where B is a copy gate. If (i.e., B is unreachable from the target U input edge), then connect a signal line between B and A '. Finally, a signal line is connected between the copy gate of the input gate connected to the output gate of the circuit and the output gate of the circuit. In step 725d, a logical value 0 is set in the target U input edge UE1 and a logical value 1 is set in the copy gate UE2 of UE1. Here, conversely, the logical value 1 may be set to UE1 and the logical value 0 may be set to UE2. In step 725e, an implication operation is performed. In step 725f, the connection of the signal line whose logical value is set to 0 or 1 is disconnected. In step 725g, the gate whose output is floating is deleted.

FIG. 42 is a diagram showing a circuit conversion B1 in the third embodiment of the present invention. In FIG. 42 (a),
U3 represents the U input edge, R1, R2, R3, R4,
R5, R6, R7, and R8 represent NOR gates, and
1 represents the output NOR gate of the circuit. U3 is circuit conversion A
2 is an impossible U input edge. FIG. 42B shows the circuit after copying the output side from U3 in the circuit shown in FIG. In FIG. 42 (b), U3 ′ represents a U input edge obtained by copying U3, and C4, C5, C7, and C8 represent NOR gates obtained by copying R4, R5, R7, and R8, respectively (step of FIG. 41). 725
c). 42 (c), the logical value 0 is set to U3 and the logical value 1 is set to U3 ′ shown in FIG. 42 (b) to perform the implication operation, and the signal line having the logical value 0 or 1 is disconnected. , A circuit in which a gate whose output is floated is deleted (step 725d, step 725e, step 725f, step 725g). In FIG. 42C, the target U input edge U3 has been removed.

[0043]

According to the present invention, by cutting out only the necessary circuit area and removing the redundancy of the circuit, the principle undetected failure determination of the arithmetic unit logic circuit can be efficiently performed.
Moreover, a test pattern can be easily generated by using the result of this principle undetected failure determination.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an outline of a principle undetected failure determination process of a logic circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of an extended implication operation.

FIG. 3 is a diagram showing an example of unique activation.

FIG. 4 is a diagram showing an example of a conventional reduction method.

FIG. 5 is a configuration diagram of a computer system to which the principle undetected failure determination method of logic circuit and the test pattern generation method of the present invention are applied.

6 is a diagram showing a configuration of logic circuit data 30 of FIG.

FIG. 7 is a diagram showing the configurations of an output hypothetical failure table 40, an input hypothetical failure table 45, and test pattern data 50 shown in FIG.

FIG. 8 is a flow chart showing an outline of the principle undetected failure determination processing and test pattern generation processing of the logic circuit in the first embodiment of the present invention.

FIG. 9 is a detailed flowchart of the related area investigation shown in step 100 of FIG.

FIG. 10 is a diagram showing a related area in the first exemplary embodiment of the present invention.

FIG. 11: A used in step 400 of FIG.
It is a figure which shows the conversion example of the equivalent expression by the NOR gate of ND, NAND, OR, and NOR gate.

12 is a detailed flowchart of the principle undetected failure determination in the relevant area of the target undetected failure shown in step 700 of FIG.

FIG. 13 is a diagram showing an example of circuit conversion for the assumed failure shown in step 701 of FIG.

FIG. 14 is a detailed flowchart of EOR logic extraction in the EOR logic extraction / reduction processing shown in step 707 of FIG.

15 is a diagram showing a specific example of EOR logic extraction processing in the EOR logic extraction / reduction processing shown in step 707 of FIG.

16 is a diagram showing a reduction example of the EOR gate and the ENOR gate in the EOR logic extraction / reduction processing shown in step 707 of FIG.

FIG. 17 is a diagram showing a specific example of a process of putting together the common logic shown in step 702 of FIG.

FIG. 18 is a detailed flowchart of updating the head signal line shown in step 703 of FIG.

FIG. 19 is a diagram showing an example of updating the head signal line shown in step 703 of FIG.

20 is a detailed flowchart of the reduction processing of the circuit shown in step 704 of FIG.

FIG. 21 is a reduction process A shown in step 734 of FIG. 20.
It is a detailed flowchart of 1.

22 is a reduction process A shown in step 734 of FIG.
It is a figure which shows the example of 1.

FIG. 23 is a reduction process A shown in step 735 of FIG. 20.
2 is a detailed flowchart of FIG.

FIG. 24 is a reduction process A shown in step 735 of FIG. 20.
It is a figure which shows the example of.

FIG. 25 is a reduction process B shown in step 739 of FIG. 20.
2 is a detailed flowchart of FIG.

FIG. 26 is a reduction process B shown in step 739 of FIG. 20.
It is a figure which shows the example of.

27 is a detailed flowchart of the determination by the logical value allocation trial shown in step 706 of FIG.

28 is a detailed flowchart of justification for the unjustified signal line shown in step 812a of FIG. 27. FIG.

FIG. 29 is a detailed flowchart of the backward tracking shown in step 825a of FIG. 28.

FIG. 30 is a detailed flowchart of the backtrack shown in step 828a of FIG. 28.

FIG. 31 is a diagram showing an example of determination processing by the logical value allocation trial shown in step 706 of FIG.

32 is a detailed flowchart showing an alternative method of backward tracking shown in step 825a of FIG. 28. FIG.

FIG. 33 is a detailed flowchart of test pattern generation shown in step 1000 of FIG.

34 is a detailed flowchart of editing the determination result shown in step 1100 of FIG.

FIG. 35 is an N of the related area in the second embodiment of the present invention.
It is a figure which shows the conversion of the equivalent expression used by AND conversion.

FIG. 36 is a diagram showing an outline of a principle undetected failure determination process of a logic circuit including an uncertain input edge according to the third example of the present invention.

37 is a detailed flowchart of the principle undetected failure determination in the relevant area of the target undetected failure shown in step 700 of FIG. 8. FIG.

38 is a detailed flowchart of the circuit conversion for U input edge removal in step 720 of FIG. 37. FIG.

FIG. 39 is the circuit conversion A shown in step 723 of FIG. 38.
2 is a detailed flowchart of 2.

FIG. 40 is a circuit conversion A2 in the third embodiment of the present invention.
FIG.

41 is a circuit conversion B shown in step 725 of FIG.
It is a detailed flowchart of 1.

FIG. 42 is a circuit conversion B1 in the third embodiment of the present invention.
FIG.

[Explanation of symbols]

1 target combination circuit X and target undetected fault f 2 1 output circuit Y 2 ′ obtained by performing conversion on target undetected fault f to target combination circuit X 2 NOR gate, EOR gate, ENOR gate,
1 output circuit Y'4 equivalent to one output circuit Y composed of and input edges 4 Reduction process 5 Logical value assignment trial 10 Processor 20 Principle undetected failure judgment program 30 Logic circuit data 40 Output assumption failure table 45 Input assumption Failure table 50 Test pattern data

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Takao Nishida 1 Horiyamashita, Hinoyama, Hadano, Kanagawa Pref., General Computer Division, Hitachi, Ltd. (72) Inventor Jun Matsushima 1 Horiyamashita, Hadano, Kanagawa Factory General Computer Division

Claims (19)

[Claims] 1. A fault diagnosing method for a logic circuit according to a scan design method, wherein all of the division circuits including a combinational circuit obtained by division at a flip-flop and an input / output edge, including target undetected faults, are extracted. 1 step, a second step of converting the divided circuit into an equivalent circuit composed of only one kind of basic gate, and outputting a true value for an input pattern for detecting the undetected fault in the equivalent circuit However, for other input patterns, there is a third step of converting the equivalent circuit into a one-output circuit that outputs a false value, and whether there is an input pattern in which the output of the one-output circuit becomes a true value. A fourth step of determining whether or not the test result of the undetected fault is a fault that does not exist in the entire circuit when the determination result in each divided circuit does not include all the input patterns. A fifth sub-step for making a decision, the fourth sub-step including a first sub-step for extracting and reducing EOR logic and ENOR logic in the one-output circuit obtained in the third step, and the first sub-step. In the second substep of combining a plurality of gates representing the same logic in the circuit obtained in the step into one gate, and in the circuit obtained in the second substep, the output can be controlled to a true value or a false value independently of each other. By recognizing a set of gates in the circuit in which a branch point of a signal line exists on the input side of the set of gates, a circuit area reachable from the branch point and an unreachable point from the branch point A third sub-step for updating a signal line at the boundary of the circuit region to the output side from the set of gates, and a fourth sub-step for reducing the redundant logic in the circuit obtained in the third sub-step. , The fourth And a fifth sub-step for determining whether or not there is an input pattern in which the output of the one-output circuit is a true value by trying the logical value assignment of the signal line in the circuit obtained in the step. Principle of undetected failure judgment method of logic circuit characterized by. 2. The test pattern creation method using the principle undetected failure determination method for a logic circuit according to claim 1, wherein the undetected failure determined to have the input pattern in the fourth step is: A test pattern generation method for a logic circuit, which is characterized in that a test pattern is generated from logic value information of an input edge having a fixed value. 3. The method for determining a principle undetected failure of a logic circuit according to claim 1, wherein the first step includes a first substep of extracting all one-output divided circuits including an undetected failure part. , For each of the one-output dividing circuits, an input edge of the one-output dividing circuit, and an output signal line in which either a stuck-at-0 fault or a stuck-at-1 fault in the one-output dividing circuit has already been detected. A second sub-step of recognizing the one having the smallest circuit scale among the one-output circuits surrounded by the undetected failure location as a related area necessary for the principle undetected failure determination, and the overlapping related areas are removed. And a third sub-step for performing the principle undetected failure determination method for a logic circuit, which is characterized in that the principle undetected failure determination is performed only in an effective related area. 4. The logical undetected failure determination method for a logic circuit according to claim 1, wherein in the third step, the circuit output is applied to an input pattern for setting a failure signal at an undetected failure location. A first sub-step of converting the equivalent circuit into a circuit in which the logical value becomes a true value and the output logical value of the circuit becomes a false value for other input patterns, and a failure signal at the undetected failure point For an input pattern that propagates a fault signal from the undetected fault point to the branch point of the first signal line, the output logical value of the circuit becomes a true value, and for other input patterns Is a second sub-step for converting the circuit obtained in the first sub-step into a circuit in which the output logical value of the circuit is a false value, and a failure signal is set to the undetected failure point, and the undetected failure point is set. The first signal line For an input pattern that propagates a fault signal to a branch point and propagates the fault signal from the branch point to the output of the equivalent circuit, the output logical value of the circuit becomes a true value, and for other input patterns And a third sub-step for converting the circuit obtained in the second sub-step into a circuit whose output logical value is a false value. 5. The method for determining an undetected failure of a logic circuit according to claim 4, wherein in the first sub-step, if the undetected failure is a stuck-at failure having a false value as an output value, the undetected failure signal line. Is connected between the basic gate having the output signal line and the newly provided output basic gate by interposing a 1-input basic gate that inverts the logical value, and the undetected fault signal line is disconnected. If the detected fault is a stuck-at fault having a true value as an output value, a connection is connected between a basic gate having an undetected fault signal line as an output signal line and a newly provided output basic gate, and the undetected fault signal line A principle of undetected failure determination method of a logic circuit characterized by disconnecting the wiring. 6. The logic undetected failure determination method according to claim 4, wherein in the first sub-step, if the undetected failure is a stuck-at failure having a false value as an output value, the undetected failure signal line. Is connected between the basic gate having the output signal line and the newly provided output basic gate by interposing a 1-input basic gate that inverts the logical value, and the undetected fault signal line is disconnected. If the detected fault is a stuck-at fault having a true value as an output value, a connection is connected between a basic gate having an undetected fault signal line as an output signal line and a newly provided output basic gate, and the undetected fault signal line The connection is separated, and in the second sub-step, for each basic gate on the path from the undetected fault location in the circuit obtained in the first sub-step to the branch point of the first signal line,
A new output basic gate is connected to the output of an input basic gate to the basic gate which is not on the path, and the connection between the basic gate and all input basic gates to the basic gate is disconnected. A principle of undetected failure determination method for a characteristic logic circuit. 7. The principle undetected failure determination method for a logic circuit according to claim 4, wherein in the first substep, if the undetected failure is a stuck-at failure having a false value as an output value, the undetected failure signal line. Between the basic gate having an output signal line and a newly provided output basic gate with a 1-input basic gate for inverting the logic value connected to disconnect the undetected fault signal line. If the detected fault is a stuck-at fault having a true value as an output value, a connection is connected between a basic gate having an undetected fault signal line as an output signal line and a newly provided output basic gate, and the undetected fault signal line The connection is separated, and in the second sub-step, for each basic gate on the path from the undetected fault location in the circuit obtained in the first sub-step to the branch point of the first signal line,
A newly provided output basic gate is connected to the output of the input basic gate to the basic gate which is not on the path, and the connection between the basic gate and all the input basic gates to the basic gate is disconnected, In the third sub-step, the circuit area in the circuit obtained in the second sub-step in which the fault signal can propagate is separated into a normal circuit not including an undetected fault and a fault circuit including an undetected fault, and newly A two-input exclusive OR composed of basic gates is provided, the input of the two-input exclusive OR is connected to each output of the normal circuit and the failure circuit, and the output of the two-input exclusive OR and the first substep A principle undetected failure determination method for a logic circuit, characterized in that a connection is connected between a newly provided output basic gate and a one-input basic gate that inverts a logical value. 8. The method for determining a principle undetected failure of a logic circuit according to claim 1, wherein in the first substep, EOR logic and ENOR logic in the circuit are recognized and expressed by an EOR gate and an ENOR gate. If there is an n-input EOR gate in the input gate of the first substep and the m-input EOR gate in the circuit (m, n: integer), replace both gates with (m + n-1) -input EOR gate, and m If the input gates of the input EOR gates have n-input ENOR gates, both gates are (m + n-1) input ENORs.
If there is an n-input EOR gate in the input gate of the m-input ENOR gate, replace both gates with (m
+ N-1) Replaced with input ENOR gate, m input EN
If the input gates of the OR gates have n-input ENOR gates, the second sub-step of replacing both the gates with (m + n-1) -input EOR gates, and the input gates of the EOR gates in the circuit have 1-input basic gates. If an even number exists, all the input gates of the one-input basic gate and the EO
R gate is directly connected and the 1 input basic gate is deleted.
If there is an odd number of 1-input basic gates in the input gates of the EOR gate, all the input gates of the 1-input basic gates are directly connected to the EOR gates, and the 1-input basic gates are all deleted to convert the EOR gates into ENOR gates. Replace, E
When there is an even number of 1-input basic gates in the input gates of the NOR gates, all the input gates of the 1-input basic gates are directly connected to the ENOR gates, and the 1-input basic gates are all deleted, and the input gates of the ENOR gates are deleted. If there is an odd number of one-input basic gates, all the input gates of the one-input basic gates are directly connected to the ENOR gates, all the one-input basic gates are deleted, and the ENOR gates are replaced with EOR gates. A method for determining undetected failure in principle of a logic circuit, comprising: 9. The principle undetected failure determination method for a logic circuit according to claim 8, wherein in the first substep, the output implication value of the multi-input basic gate in the circuit is set to 1 and the implication is performed backward. A first substep of registering a stop gate, a second substep of performing an implication backward by setting the output logical value of each implication stop gate registered in the first substep to 1, and registering an implication stop gate; A third substep of checking whether the output of the multi-input basic gate is equivalent to the EOR logic or the ENOR logic of the output of the implication stop gate registered in the second substep, and the third substep When it is determined that the multi-input basic gate is equivalent to the EOR logic, the multi-input gate to the implication stop gate registered in the second substep are EO.
If the multi-input basic gate is determined to be equivalent to ENOR logic in the third sub-step, the multi-input gate to the implication stop gate registered in the second sub-step are ENOR gates. And a fourth sub-step of replacing with. 10. The method for determining a principle undetected failure of a logic circuit according to claim 1, wherein the third sub-step comprises:
A first sub-step of setting a logical value 0 or 1 in the head signal line having a branch, performing a forward implication, and registering a basic gate whose implication has stopped, and a logical value X on the input side of the registered basic gate A second sub-step of determining whether or not the output logical value of the registered basic gate can be independently controlled to 0 or 1 by controlling the logical value of the head signal line to 0 or 1, and the second sub-step. By disconnecting the connection of the signal line whose logical value is set to 0 or 1 in the first sub-step, when it is determined in the step that the output logical value of the registered basic gate can be independently controlled to 0 or 1 , A third updating the leading signal line from the registered basic gate to the output side
And a sub-step of (4). 11. The method for determining a principle undetected failure of a logic circuit according to claim 1, wherein the fourth sub-step comprises:
A first substep for reducing a redundant partial circuit on the input side of a multi-input basic gate in the circuit obtained in the third substep, and an output basic gate of the circuit obtained in the first substep. For a leading signal line in which any of the paths is composed of an even number of basic gates, the logical value of the leading signal line is set to a false value for forward implication, and the logical value is 0 or 1.
For the head signal line in which the connection of the signal line established in step 1 is cut off and any path to the output basic gate of the circuit obtained in the first substep is composed of an odd number of basic gates, A second substep of performing a forward implication by setting the logical value of the signal line to a true value and disconnecting the connection of the signal line whose logical value is set to 0 or 1; Failure determination method. 12. The principle undetected failure determination method for a logic circuit according to claim 12, wherein in the first substep, backward implication is performed by using the logical value of the multi-input basic gate as a true value, and the backward implication is performed. A first sub-step of registering the basic gate at the stop, a second sub-step of removing an unnecessary logic circuit between the multi-input basic gate and the registered basic gate, and logic of the registered basic gate. If the value is a false value, a wire is connected between the registered basic gate and the multi-input basic gate, and if the logical value of the registered basic gate is a true value, it is connected between the registered basic gate and the multi-input basic gate. And a third sub-step of connecting the wires by interposing a 1-input basic gate that inverts the logic value. 13. The method for determining a principle undetected failure of a logic circuit according to claim 1, wherein the fifth sub-step comprises:
A first substep of setting a true value to the output logical value of the circuit obtained in the fourth substep and performing an implication operation, and the unjustified signal line generated in the first substep are justified;
If the justification is successful, it is determined that there is an input pattern in which the output of the one-output circuit is a true value, and if the justification cannot be done no matter how the logical value is assigned, the output of the one-output circuit is If it is determined in the second substep that there is no input pattern that makes a true value and in the second substep that there is an input pattern that makes the output of the one output circuit a true value, a logical And a third sub-step that justifies a leading signal line whose value is set to 0 or 1 up to an input edge. 14. The method for determining a principle undetected failure of a logic circuit according to claim 13, wherein in the second sub-step, the presence or absence of an unjustified signal line is checked while no contradiction occurs due to an implication operation. If there is no unjustified signal line, it is determined that there is an input pattern in which the output of the one output circuit is a true value, and if there is, one unjustified signal line is selected and A theoretical undetection of a logic circuit, comprising a first substep of performing tracking and implication operation, and a second substep of performing backtracking and implication operation when a contradiction occurs due to the implication operation. Failure determination method. 15. The method for determining a principle undetected failure of a logic circuit according to claim 14, wherein in the first sub-step, the presence or absence of an unjustified signal line is checked, and if there is no unjustified signal line, the one output is output. It is determined that there is an input pattern in which the output of the circuit becomes a true value, and if there is, an unvalidated signal line is selected, and a gate having the unvalidated signal line as an output signal line is used as a backward tracking target gate. The backward tracking target gate is one of the input gates whose logical value is undetermined until the backward tracking target gate becomes a gate whose output is the first signal line, with the logical value of the unjustified signal line as the target value. And a target value is repeatedly updated, the final target value is set to the output signal line of the final back-tracking target gate, and an implication operation is performed. 16. The method for determining a principle undetected failure of a logic circuit according to claim 14, wherein in the second sub-step, all the signal lines for which logical values have been set in the backward tracing of the first sub-step have already been logical values. If it has been inverted, it is determined that there is no input pattern such that the output of the one output circuit becomes a true value. If it has not been inverted, the logic value is the last logical value among the signal lines whose logic value is not inverted. Select the one with
The principle of undetected failure determination of a logic circuit characterized in that all logical values of a signal line whose logical value is set after the signal line are returned to undetermined, the logical value of the signal line is inverted, and implication operation is performed. Method. 17. The method for determining a principle undetected failure of a logic circuit according to claim 14, wherein in the first sub-step, the presence or absence of an unjustified signal line is checked, and if there is no unjustified signal line, the one output is output. It is determined that there is an input pattern in which the output of the circuit becomes a true value, and if there is, an unvalidated signal line is selected, and a gate having the unvalidated signal line as an output signal line is used as a backward tracking target gate. With the logical value of the unjustified signal line as the target value, the backward tracking target gate is updated to one of the input gates of the logical value X of the backward tracking target gate, the target value is updated, and the output signal of the backward tracking target gate is updated. A theoretical undetected failure determination method for a logic circuit characterized by setting a target value on a line and performing an implication operation. 18. The method for determining a principle undetected failure of a logic circuit according to claim 1, wherein in the fourth step, an uncertain input edge in the one-output circuit obtained in the third step is removed. In the first sub-step for converting the one-output circuit into a one-output circuit not including an uncertain input edge, and in the circuit obtained in the first sub-step, EO
A second sub-step of extracting and reducing the R logic and the ENOR logic, and a third sub-step of combining a plurality of gates representing the same logic in one output circuit obtained in the second sub-step into one gate, A set of gates in the circuit that can control the output to a true value or a false value independently of each other in the circuit obtained in the third substep, and a branch point of the signal line exists on the input side of this gate set. A fourth sub-step of updating the signal line at the boundary between the circuit area reachable from the branch point and the circuit area unreachable from the branch point by recognizing the object from the set of gates to the output side; The fourth
The fifth sub-step for reducing redundant logic in the circuit obtained in the sub-step, and the circuit obtained in the fifth sub-step by trying the logic value assignment of the signal line
And a sixth sub-step for determining whether or not there is an input pattern in which the output of the output circuit becomes a true value. 19. The theoretical undetected failure determination method for a logic circuit according to claim 18, wherein the output value of the output destination gate is set to 0 in the first substep without affecting the theoretical undetected failure determination. Alternatively, the first substep of removing the uncertain input edge by controlling the output logical value of the output gate of the uncertain input edge that can be controlled to 1 and the control shown in the first substep are impossible. A second sub-step of removing an uncertain input edge by synthesizing a circuit in the case of inputting 0 and a circuit in the case of inputting 1 to the uncertain input edge Undetected failure determination method.