JPH05233749A - Logical equivalence verifying method - Google Patents

Abstract

PURPOSE:To efficiently attain a logical equivalence verification by systematically obtaining the redundancy of a circuit making the logical equivalence verification difficult, and removing the redundant part. CONSTITUTION:Tow logic being the objects of the logical equivalence verification are expressed by the combined circuits constituted only of an NOR gate and an input edge (step 100). The outputs of the two combined circuits obtained by the step 100 are combined by an exclusive OR, and the corresponding input edges are gathered, so that one output circuit can be obtained (step 200). Whether or not the output of one output circuit obtained by the step 200 is turned to 0 for any input pattern is judged (step 300). Whether or not the unequivalence of the objective logic is judged by the step 300 is checked (step 500). and when it is Judged, the processing is transferred to a step 600, and when it is not judged, the processing is ended. The input pattern by which the objective logic is not equivalent, that is, irregular pattern is prepared (step 600).

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to combinatorial logic equivalence verification.

[0002]

2. Description of the Related Art The following methods have been mainly proposed as the equivalence verification method for combinational logic. A method of simulating and verifying all input patterns and XNOR (Negation of exclusive OR) of outputs of two combinational logic circuits
IEEE ITC-86, p is a method of checking whether or not there is an input pattern in which the output is 0 by justification.
p. 350-359 (1986). Among these, the latter method by justification performs implication operation with the output logic value of the circuit connecting the outputs of the two combinational logic circuits by XNOR as 1, and the unjustified signal line generated in the process of implication operation is logically processed. Test pattern generation algorithm D algorithm and PODE for combinational circuits in circuit fault diagnosis
This is a justification method using the justification method in M. (The justification is to determine the logical value up to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the target signal line.) 2
IEEE T is a method of expressing one combinational logic by a binary decision graph (BDD) and performing equivalence verification by judging the structural match of the graph.
RANSACTIONS ON COMPUTERS, VOL. C-35, NO.8, AUG.
pp. 677-691 (1986). FIG. 35 shows an example of BDD representation of the combinational logic.

[0003]

The logical equivalence verification has the following problems with the increase in scale of the logic circuit.

In the simulation verification with all the input patterns, there arises a problem that the number of input patterns increases in the order of exponent. In the justification method,
There is a problem of re-justification, that is, the number of backtracks increases in an exponential order in the worst case. Further, in the method of comparing BDDs, there is a problem that the depth of BDDs increases in an exponential order in the worst case. The increase in the number of backtracks and the increase in BDD depth are caused by the fact that the circuit redundancy becomes wider and more complicated due to the increase in the scale of the logic circuit. The redundancy of this circuit includes the redundancy that the original logic had and the redundancy that results from combining two similar logics.

Since the conventional method does not take a method of catching and removing the redundancy of these circuits, it has a drawback that a complicated circuit including the redundancy must be handled as it is.

An object of the present invention is to efficiently grasp the logic by grasping the redundancy of the circuit which makes the logic equivalence verification difficult in order to solve the above problems, and removing the redundant portion. Equivalence verification is performed.

[0007]

The present invention performs the following steps in order to achieve the above object. The first step of converting the target combinational logic into an equivalent circuit expressed only by NOR gates. A second step in which the corresponding input edges of the two combinational circuits obtained in the first step are combined into one and the output is exclusive ORed. A third step of determining whether or not there is an input pattern in which the output of the one-output circuit obtained in the second step is 1. Furthermore, the third step consists of the substeps described below. A first substep of the third step in which a plurality of gates representing the same logic in the target 1 output circuit are replaced by one gate. In the circuit obtained in the first sub-step, the set of gates in the circuit that can control the outputs to be 0 or 1 independently of each other, and in which the branch point of the signal line exists on the input side from this set of gates By extracting, the signal line (leading signal line) at the boundary between the circuit area reachable from the branch point and the circuit area unreachable from the branch point is updated to the output side from the set of extracted gates. Second sub-step of 3 steps. A third sub-step of the third step for reducing redundant logic in the circuit obtained in the second sub-step. The fourth substep of the third step of converting the circuit obtained in the third substep into one head signal line 1 output circuit. 1 obtained in the 4th substep
A fifth substep of the third step of determining whether or not there is an input pattern in which the output of the head signal line 1 output circuit becomes 1. Furthermore, if it is determined in the third step that the two target combinational circuits are not equivalent, a fourth step of generating a counterexample pattern from the deterministic logical value information of the input edge whose value has been determined in the third step.

[0008]

According to the above means, a plurality of gates representing the same logic in the circuit are represented by one gate, and a set of gates in the circuit capable of controlling the output to 0 or 1 independently of each other in the circuit. By recognizing that there is a branch point of the signal line on the input side of the set, a signal line (leading signal line) at the boundary between the circuit area reachable from the branch point and the circuit area not reachable from the branch point ) Is updated to the output side from the set of gates described above, and further, by reducing redundant logic in the circuit,
The redundancy of the circuits that makes the logical equivalence verification difficult can be grasped in a unified manner, and the redundant circuit parts can be removed to efficiently perform the logical equivalence verification.

[0009]

【Example】

(Embodiment 1) FIG. 31 shows the configuration of a computer system for implementing the present invention. A logical equivalence verification program 20 which is a processing program of the present invention is stored in the processing device 10, and a logical circuit data 30, a Boolean expression data 40, and an output result which are targets of the logical equivalence verification of the present invention are stored in an external storage device. Counter example pattern data 50 is stored.

The logic circuit data 30 shown in FIG. 31 is shown in FIG.
2, the structure of the Boolean expression data 40 is shown in FIG. 33, and the structure of the counterexample pattern data 50 is shown in FIG.

The logic circuit data 30 shown in FIG. 32 represents a logic circuit to be subjected to logic equivalence verification as a connection relationship between respective gates, and the data is stored in a table format. The data corresponding to each gate is composed of fields as described below. Item number (N
o. ) 31 is a number indicating an entry in the table corresponding to each gate. The element (ELEMENT) 32 includes an identifier (ID) 32a of each gate and a type (KI) of the gate.
ND) 32b. Output gate (OUT
In the field of (PUT GATE) 33, the output value (VALUE) 33a of the element 32, the number of gates (OUTNUM) 33b connected to the output side of the element 32, and the IDs (OUT1, OUT2, ...) 33c of these gates, 33d,
... is stored. Input gate (INPUT GAT
E) In the field 34, the number of gates (INNUM) 34a connected to the input side of the element 32, IDs (I1, I2, I3, ...) 34b, 34d of these gates,
34f, ..., and input values (V1, V2, ...) 34c, 3
4e, ... Are stored. Control data (CONTROLDAT
The field A) 35 stores information that is set or referred to during the processing of the present invention. In particular, in the field of the output signal line information (KIND OF LINE) 35a, the output signal line of the element 32 is bound to the bound signal line (bound line).
Information indicating either e), the head signal line (head line), or an unbounded signal line (free line) other than the head signal line is registered. Also, the number of output stages (PO LEVEL) 35b
The number of gate stages from the output gate of the circuit of the element 32 is registered in the field of.

As an example, each entry in FIG. 32 stores data corresponding to the logic circuit shown in FIG. As shown in FIG. 30, input / output edges are also registered in the logic circuit data 30.

In the Boolean expression data 40 shown in FIG. 33,
Among the logics subject to logical equivalence verification, those described by Boolean expressions are stored in a table format. The data corresponding to each element of the Boolean expression is composed of fields as described below. The item number (No.) 41 is a number indicating an entry in the table corresponding to each element of the Boolean expression. Information indicating whether the element of the Boolean expression is a variable or an operator is registered in the KIND 42. In the Boolean 43, the variable name is registered when the element is a variable, and the operator type is registered when the element is an operator. In each entry of FIG. 33, as an example, Boolean data of the form X = A & B is stored.

In the counterexample pattern data 50 shown in FIG. 34, counterexample pattern data obtained as a result of the logical equivalence verification of the present invention is stored in a table format. The data corresponding to each input edge is composed of fields as described below. The item number (No.) 51 is a number indicating the entry of the table corresponding to each input edge. ID5
2 is an identifier of each input edge. Setting value (VALU
E) 53 is a value to be set at the input edge. As an example, the entry of FIG. 34 stores data corresponding to the input edge of the logic circuit shown in FIG.

First, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the flow of each part of the logical equivalence verification processing according to the present invention. Reference numeral 1 represents combinational circuits X and Y representing the target logic. For example, consider Problem 1 “Is circuit X and circuit Y equivalent circuits?”. Reference numeral 2 represents a one-output combination circuit Z obtained by taking the exclusive OR of the outputs of the circuit X and the circuit Y of 1 and collecting the corresponding input edges into one. On the other hand, considering Problem 2 “Is the output of circuit Z always 0?”, Problem 1 and Problem 2 are equivalent.
Reference numeral 3 represents a process for simplifying the circuit by a reduction process or the like. Four
The reduction of the head signal line of means the process of reducing the head signal line by one. Here, of the unbounded signal lines, the one that is adjacent to the bounded signal line is called the head signal line. An unbound signal line is a signal line that cannot be traced from any branch point in the circuit to the output side, and a bound signal line is traced from an appropriate branch point in the circuit to the output side. A signal line that can be reached as you go. By repeatedly performing the processes 3 and 4 on the circuit Y, the final circuit (1 head signal line 1 output circuit) shown by 5 is finally obtained. For 5,
Considering the problem 3 "Is the output of the final circuit always 0?", The problem 3 is equivalent to the problem 2, and since the number of head signal lines that affect the output of the circuit is one, Problem 3 can be easily solved. If the answer to question 3 is YES, then the answers to questions 2 and 1 are also YES, and if the answer to question 3 is NO, then the answers to question 2 and 1 are also NO.

FIG. 2 is a flow chart showing the outline of the first embodiment of the logical equivalence verification processing according to the present invention. In step 100, the two logics to be subjected to logic equivalence verification are represented by a combinational circuit composed only of NOR gates and input edges. In step 200, the outputs of the two combinational circuits obtained in step 100 are connected by exclusive OR, and the corresponding input edges are combined to obtain one output circuit.
This 1-output circuit has an output of 0 for any input pattern if the original two target logics are equivalent, and an output for its counterexample pattern if the original two target logics are not equivalent. It has the property of becoming 1. Step 30
At 0, it is determined whether the output of the 1-output circuit obtained at step 200 becomes 0 for any input pattern. In step 500, it is checked whether or not it is determined in step 300 that the target logic is not equivalent. If it is determined, the process proceeds to step 600, and if it is not determined, the process ends. In step 600, an input pattern in which the target logic is not equivalent, that is, a counterexample pattern is generated.

Hereinafter, each of these steps will be described in detail with reference to the drawings.

FIG. 3 is a detailed flowchart of the NOR conversion of the target logic shown in step 100 of FIG. In step 101, the description format of the first target logic is checked, and if it is a circuit description format, branch to step 103, and if it is a Boolean expression description format, branch to step 102. In step 102, the Boolean expression description of the first target logic is converted into a circuit description. In step 103, the description format of the second target logic is checked, and if it is the circuit description format, step 10
5, and if it is a Boolean expression description format, it branches to step 104. In step 104, the Boolean expression description of the second target logic is converted into a circuit description. In step 105, the two target logic circuits obtained in steps 101 to 104 are converted into a circuit composed of only NOR gates and input edges.

FIG. 4 is a conversion example of an equivalent expression used in the NOR conversion of the target circuit shown in step 105 of FIG. 3, which is a 2-input AND, NAND, OR, and NOR.
Each gate is expressed by a combination of NOR gates.

FIG. 5 shows step 300 of FIG.
3 is a detailed flowchart of a process for determining whether or not the output of the 1-output circuit obtained in step 200 of FIG. 2 is always 0. In step 301, it is checked whether or not there are two or more gates having the same set of inputs in the circuit obtained in step 200 of FIG. 2, and if they exist, those gates are replaced by one gate. In step 302, the top signal line is updated. Here, of the unbounded signal lines, the one that is adjacent to the bounded signal line is called the head signal line. An unbound signal line is a signal line that cannot be traced from any branch point in the circuit to the output side, and a bound signal line is traced from an appropriate branch point in the circuit to the output side. A signal line that can be reached as you go. In step 303, circuit simplification processing is performed to simplify complicated parts in the circuit.
In step 304, it is checked during the reduction process of step 303 whether the two target logics are equal or not, and if any of the determinations is made, the process is terminated, If neither determination is made, the process branches to step 305. Step 305
Then, reduction of the head signal line included in the circuit subjected to the reduction processing in step 303 is performed to obtain 1 head signal line 1
Convert to output circuit.

FIG. 6 shows a concrete example of the processing of putting together the common logic shown in step 301 of FIG. In FIG. 6A, 1c, 2c, 3c, 4c, 5c, 6c and 7c represent NOR gates. Here, NOR gates 4c and 5c
Both have NOR gates 6c and 7c as fan-in destination gates. Therefore, since the NOR gates 4c and 5c have the same input relationship, the NOR gates 4c and 5c
Can be combined into one. FIG. 6B shows N
By disconnecting the connection between the OR gates 6c, 7c and 5c and the connection between the NOR gates 5c, 2c and 3c, and connecting the connection between the NOR gates 4c and 2c and 3c, as shown in FIG.
2 shows a circuit in which the NOR gate 5c of is replaced by 4c.

FIG. 7 is a detailed flowchart for updating the head signal line shown in step 302 of FIG. Here, of the unbounded signal lines, the one that is adjacent to the bounded signal line is called the head signal line. An unbound signal line is a signal line that cannot be traced from any branch point in the circuit to the output side, and a bound signal line is traced from an appropriate branch point in the circuit to the output side. A signal line that can be reached as you go. In step 311, it is checked whether or not there is a head signal line having a branch that has not been checked for the possibility of updating the head signal line. If it exists, the process branches to step 312, and if it does not exist. The process ends. In step 312, one of the head signal lines having a branch that has not been investigated for the possibility of updating the head signal line is selected, and this head signal line is set to H. Step 31
In 3, the logical value of the head signal line H is set to 0 and the forward implication is performed. In step 314, all the gates of the output logical value X (where the input logical value has changed but the output logical value has remained unchanged at X) due to the forward implication are all independent of each other. It is checked whether the gate can control the logical value of the output signal line to 0 or 1, that is, whether the gate can be traced to the input edge through the gate of the output logical value X having no branch point.
If not traceable, the process branches to step 318. In step 315, the connection of the signal line whose logical value is 0 or 1 is disconnected. In step 316, the gate connected to the bound signal line whose output floated during the process of step 315 is deleted. At step 317, the logical value of the head signal line H is justified. Here, the justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the signal line as the output signal line matches the logical value of the signal line. Step 318
Then, it is checked whether the logical value of the head signal line H is 1, and if it is 1, the process branches to step 319.
Branch to 20. In step 319, the logical value of the head signal line H is set to X, and the forward implication is performed. Step 320
Then, the logical value of the head signal line H is set to X to perform the forward implication. In step 321, the logical value of the head signal line H is set to 1
Set to and do forward implications. Then, the process from step 314 is repeated.

FIG. 8 shows an example of updating the head signal line shown in step 302 of FIG. In FIG. 8A, 1
d, 2d, 3d, 4d, 5d, 6d, 7d, and 8d are
NOR gates 9d, 10d, 11d, 12d, and 1
3d designates the input edges as 14d, 15d, 16d, 17
d and 18d represent signal lines. Here, the head signal lines are the signal lines 14d, 15d, 16d, and 17d, and the signal line 14d has a branch, and the signal lines 15d, 16d, and 17d.
d has no branch. FIG. 8B shows a state in which the output logical value of the head signal line 14d having a branch is set to 0 and the forward implication is performed (step 713). Here, the NOR implication becomes impossible, and the output logical value becomes X, the NOR gate 2d,
Since 3d and 4d do not have branches like 2d to input edges 9d and 3d to input edges 10d and 4d to input edge 11d, they can be traced to the input edge through the gate whose output logical value is X. , NOR gate 2
The outputs of d, 3d, and 4d can be controlled to 0 or 1 independently of each other. In FIG. 8C, the logical value is 0 in FIG. 8B.
Alternatively, the connection of the signal line 1 is cut off (step 715), and the output logical value of the input edge 12d is set to 1 by justifying the signal line 14d. That is, in FIG. 8B, the logic operation of the signal line 12d is performed so that the NOR operation result of the logic values of the signal lines 12d and 13d becomes equal to the logic value 0 of the signal line 14d, for example, as shown in FIG. 8C. Assign 1 to the value. In FIG. 8C, the head signal line is only the signal line 18d, and the head signal line is the signal lines 14d and 15 in FIG. 8A.
The signal lines 18d on the output side are updated from d, 16d, and 17d.

FIG. 9 is a detailed flowchart of the reduction processing of the circuit shown in step 303 of FIG. For the circuit reduction processing, there are three types of reduction processing A1, reduction processing A, and reduction processing B.
There are various types of reduction processing. In the reduction process A1, redundant logic on the input side of the output gate of the circuit is reduced. In the reduction process A, the redundant logic on the input side of the multi-input gate (excluding the output gate of the circuit) of the circuit is reduced. Simplification process B
Then, the influence of the logical value of the head signal line on the output logical value of the circuit is examined, and when the logical value of the head signal line is 0, the logical value has only the effect of making the output of the circuit 1 If the logic value of the head signal line is fixed by assigning 0, and the logic value of the head signal line has a value of 1, the logic value of the head signal line only has the effect of trying to set the output of the circuit to 1. Assign 1 to and fix. In step 331, it is checked whether or not there is a multi-input gate capable of the reduction processing A. If it exists, the process branches to step 332, and if it does not exist, the process branches to step 337. In step 332, the multi-input gate R capable of the reduction processing A is selected. In step 333, it is checked whether the multi-input gate R is the output gate of the circuit, and if so, the process branches to step 334, and if not, the process branches to step 335. In step 334, the reduction process A1 is performed on the multi-input gate R. In step 335, reduction processing A is performed on the multi-input gate R. In step 336, it is checked in the middle of the reduction processing A1 or the reduction processing A whether or not the two target logics are equivalent or not equivalent to each other. If not, the process branches to step 331. In step 337, it is checked whether or not there is a leading signal line that can be subjected to the reduction processing B. If it exists, the processing branches to step 338, and if it does not exist, the processing ends.

(Of the unbounded signal lines, the one adjacent to the bounded signal line is called the head signal line. The unbounded signal line is traced from any branch point in the circuit to the output side. The signal line that is not attached, and the bound signal line is a signal line that can be reached by tracing from an appropriate branch point in the circuit to the output side.) In step 338, the reduction process B is performed. A possible head signal line H is selected. In step 339, the reduction process B is performed on the head signal line H. Step 340
Then, in the middle of the reduction process B, it is checked whether or not the two target logics are equivalent or not equivalent, and if any of them is determined, the process is terminated, and If not, step 3
Branch to 41. In step 341, it is checked whether or not there is a new head signal line that can be subjected to the reduction process B. If it exists, the process branches to step 338, and if it does not exist, the process branches to step 342. In step 342, the reduction process A
It is checked whether or not there is a multi-input gate capable of performing the above process. If it exists, the process branches to step 332, and if not, the process ends.

FIG. 10 is a detailed flowchart of the reduction process A1 shown in step 334 of FIG. In step 351, the output logical value of the multi-input gate R is set to 1 and an implication operation is performed. However, the implication operation is not performed on the unbound signal line. In step 352, a contradiction occurs during the implication operation (2 of 0 and 1 via different paths during the implication operation).
It is checked whether or not a situation in which two values are about to be set in the same signal line) has occurred. If so, the process branches to step 358, and if not, the process branches to step 353. In step 353, a gate having an output logical value of 0 and an input logical value of 0 or X and a gate having a leading signal line having a logical value of 0 or 1 as an output signal line are registered as termination gates (including input edges). To do. In step 354, the connection of the signal line whose logical value is 0 or 1 is disconnected. Step 355
Then, for each terminal gate, if the output signal line is the first signal line, the output logical value is justified up to the input edge, and if the output signal line is a bound signal line and the number of inputs is 1 or more. A wire is connected between the terminal gate and the multi-input gate R. Here, the justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the signal line. is there. In step 356, it is checked whether or not the number of inputs of the multi-input gate R is 0. If 0, the process branches to step 357, and if not 0, the process branches to step 359. In step 357, it is determined that the two target logics are not equivalent. In step 358, it is determined that the two target logics are equivalent. In step 359, the floating gate whose number of outputs becomes 0 during processing is deleted. Step 3
At 60, all the logical values of the signal line whose logical value is 0 or 1 are X.
Return to.

FIG. 11 shows an example of the reduction process A1 shown in step 334 of FIG. In FIG. 11A, 1
e, 2e, 3e, 4e, 5e, 6e, 7e, 8e and 9e are NOR gates, 10e, 11e, 12e, 13
e and 14e represent input edges. Here, the multi-input gate that is the target of the reduction process A1 is the NOR gate 1
It is e. FIG. 11B shows a state in which the output logical value of the NOR gate 1e is set to 1 and implication is performed (step 351). Here, the NOR gates 8e and 9e and the input edge 10e are termination gates (step 35).
3). FIG. 11C shows connection of signal lines having logical values 0 or 1 (1e and 2e, 1e and 3e, 1e and 4e, 2e and 8e,
2e and 6e, 3e and 5e, 4e and 6e, 5e and 8e, 5
e and 10e, 6e and 9e, and 6e and 10e) are disconnected (step 354), the termination gates 8e and 9e are connected (step 355), and the floating gate 2 is connected.
The state in which e, 7e, and 11e are deleted (step 359) is shown.

FIG. 12 is a detailed flowchart of the reduction processing A shown in step 335 of FIG. Step 3
At 71, the output logical value of the multi-input gate R is set to 1 to perform backward implication. However, no implication is applied to unbound signal lines. In step 372, it is checked whether or not a contradiction occurs during implication (a situation in which two values 0 and 1 are set to the same signal line via different paths during implication operation). If it does not occur, the process branches to step 373. Step 373
Then, the output logical value is 0 and the input logical value is 0.
Alternatively, a gate having X and a gate having a leading signal line having a logical value of 0 or 1 as an output signal line are registered as termination gates. In step 374, the circuit on the output side from the termination gate is separated into a part that converges on the multi-input gate R and a part that does not converge. In step 375, forward implication is performed from the termination gate in the part where the termination gate converges to the multi-input gate R. However, no implication is made on the output side of the multi-input gate R. In step 376, it is checked whether a contradiction occurs during the forward implication, and if so, step 379.
If not, the process branches to step 377. In step 377, the connection of the signal lines whose logical value is 0 or 1 and the output logical value that is 0 and the input logical value is 1
Disconnect all input connections to the gate where is present. In step 378, for each termination gate, if this termination gate has an output logic value of 0 and the number of inputs is 1 or more, or if the output signal line of this termination gate is a leading signal line of logic value 0, A wire is connected between the terminal gate and the multi-input gate R. If this termination gate has an output logic value of 1 and the number of inputs is 1 or more, or if the output signal line of this termination gate is the first signal line with a logic value of 1, a NOR gate N is newly added, Connections are connected between the termination gate and the NOR gate N, and between the NOR gate N and the multi-input gate R. In step 379, the output logical value of the multi-input gate R is set to 0 to perform forward implication. In step 380, among the signal lines on the output side of the multi-input gate R, the connection of the signal line whose logical value is 0 or 1 is disconnected. In step 381, the floating gate whose output number becomes 0 during the above processing is deleted. In step 382, the output logical value of the circuit is checked. If 0, the process branches to step 383, to 1 to step 384, and to X to step 385. In step 383, it is determined that the two target logics are equivalent. In step 384, it is determined that the two target logics are not equivalent. In step 385, the logical value is 0
Alternatively, all the logical values of the signal line of 1 are returned to X.

FIG. 13 is an example of the reduction process A shown in step 335 of FIG. In FIG. 13A, 1
f, 2f, 3f, 4f, 5f, 6f, 7f, 8f, and 9f represent NOR gates. Here, the multi-input gate R that is the target of the reduction process A is the NOR gate 2f. FIG. 13B shows a state in which the output implication value of the NOR gate 2f is set to 1 and the backward implication is performed (step 3).
71). Here, the termination gates are NOR gates 4f, 7
f and 8f (step 373). FIG. 13 (c)
Shows a state in which the circuits from the NOR gates 4f, 7f, and 8f to the output side are separated into a portion that converges on the NOR gate 2f and a portion that does not converge (step 374). Figure 15
In (c), NOR gates 10f and 11f are newly added to separate the circuit. FIG. 13D shows NO.
In the portion where the R gates 4f, 7f, and 8f converge to the NOR gate 2f, the state in which the forward implication is performed from the NOR gates 4f, 7f, and 8f is shown (step 37).
5). In FIG. 13 (e), the connection of signal lines having a logical value of 0 or 1 and the output logical value of 0, and the input logical value of 1
Shows the state in which all the input connections of the gate in which there is a line are disconnected (step 377), the processing of the termination gate (step 378) and the removal of the floating gate (step 381) have been performed.

FIG. 14 shows a detailed flowchart of the reduction processing B shown in step 339 of FIG. Step 3
At 91, it is checked whether all the paths from the head signal line H to the output of the circuit are composed of an even number of gates (including input edges), and if so, step 39.
2 and to step 393 if not configured. In step 392, the output logical value of the head signal line H is set to 0 to perform forward implication. In step 393, it is checked whether or not all the paths from the head signal line H to the output of the circuit are composed of an odd number of gates (including input edges). If not, the process ends. In step 394, the logical value of the leading signal line H is set to 1 to perform forward implication. In step 395, the connection of the signal line whose logical value is 0 or 1 is disconnected. In step 396, the logical value of the head signal line H is justified. Here, the justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the signal line. That is. In step 397, the number of outputs is 0 during processing.
Delete the floating gate that became. In step 398,
If the output logical value of the circuit is 0, the process branches to step 399.
If it is 1, the process branches to step 400, and if it is X, the process ends. In step 399, it is determined that the two target logics are equivalent. In step 400, it is determined that the two target logics are not equivalent.

FIG. 15 is an example of the reduction process B shown in step 339 of FIG. In FIG. 15A, 1
g, 2g, 3g, 4g, and 5g represent NOR gates, 6g and 7g represent input edges, and 8g represents signal lines. Here, the leading signal line H that is the target of the reduction processing B is the signal line 8g, and there are two paths from the signal line 8g to the output of the circuit, that is, the input edge 7g → the NOR gate 4g → the NOR gate 2g. → NOR gate 1g and input edge 7g → NOR gate 5g → NOR gate 3g →
Both NOR gates 1g are 4 including the input edge 7g.
It consists of individual gates. When the logical value of the head signal line 8g is set to 0, the output logical values of the NOR gates 4g and 2g tend to be 1 and 0, respectively, and the NOR gate 5
Since the output logical values of g and 3g tend to be 1,0, respectively, the logical value of the NOR gate 1g tends to be 1.
On the contrary, when the logical value of the signal line 8g is set to 1, the logical value of the NOR gate 1g tends to become 0. NOR gate 1g
If the output of the circuit obtained by fixing the logic value of the signal line 8g so that the output logic value of the above, that is, the output logic value of the circuit is 1, is always 0, the output of the original circuit also has the property of always 0. FIG. 15B shows a state in which the logical value of the signal line 8g is set to 0 and the forward implication is performed (step 392). FIG. 15C shows a state in which the connection of the signal line whose logical value is 0 or 1 in FIG. 15B is separated (step 395) and the floating gates (gates 2g and 4g) are deleted (step 397). Represent

FIG. 16 is a detailed flowchart of the reduction of the head signal line shown in step 305 of FIG. In step 411, it is checked whether or not the number of head signal lines is 1, and if it is 1, it is not necessary to perform reduction, and therefore the process branches to step 425. If it is not 1, the process branches to step 412. At step 412, processing for one step of reduction of the head signal line is performed. Steps 413 to 429 shown in FIG. 16 are the same as the reduction process 303 shown in FIG. However, in step 419, it is checked whether or not the leading signal line H capable of the reduction processing B exists, and if it exists, the process branches to step 420, and if it does not exist, the process branches to step 411. Further, in step 424, it is checked whether or not there is a multi-input gate R capable of the reduction processing A. If it exists, the process branches to step 414, and if it does not exist, the process branches to step 411. In step 425, it is examined how the output value of the circuit is determined by the logical value of the first signal line H, and whether the two target logics are equivalent,
Or determine if they are not equivalent.

FIG. 17 is a detailed flowchart of the processing for one step of reduction of the head signal line shown in step 412 of FIG. (Of the unbounded signal lines, the one that is connected to the bounded signal line via a branch point or a gate is called the head signal line. The unbounded signal line is traced from any branch point in the circuit to the output side. However, the bound signal line is a signal line that can be reached by tracing from an appropriate branch point in the circuit to the output side.) In step 431, the reduction is performed. Check whether there is a possible leading signal line, and if there is, step 4
If not, the process branches to step 434. Here, the reduction-capable head signal line means that the number of output stages on an arbitrary path from the head signal line to the output of the circuit is two or more, and all the gates included in the path are one-input gates. It is a certain head signal line.
In step 432, the head signal line H that can be reduced
Select one. In step 433, the reduction of the reduction-enabled head signal line H is performed. Step 43
At 4, one multi-input bound signal line L having two or more output stages is selected. In step 435, the vicinity of the multi-input bound signal line L is replaced with an equivalent expression using one input gate instead of the multi-input bound signal line L. Here, "neighborhood" means
In this embodiment, the first stage and the second stage on the input side of the gate of interest are
It is the range of the output side gate to the destination.

FIG. 18 shows an example of the reduction of the reduction-enabled head signal line shown in step 433 of FIG. In FIG. 18A, 1h, 2h, 3h, 4
h, 5h, 6h, 7h, 8h, 9h, 10h, and 11
h represents a NOR gate, and 12h represents an input edge. Here, the output gate of the circuit is the NOR gate 1h, the head signal line H targeted for reduction is the signal line 13h, and the outputs of the NOR gates 8h and 9h are the signal line 13h.
The output from the NOR gates 10h and 11h is an odd number among the paths from the signal line 13h to the output of the circuit. It merges with the one that consists of the gate. FIG. 18B shows a circuit in which the signal line 13h is reduced. Here, NOR gates 2h, 3h, 4
h, 5h, 6h, 7h and the input edge 12h are deleted, and NOR gates 14h, 15h, 16h and 17h are newly added. Further, in FIG. 18A, from the signal line 13h, two gates 8h and 9h, which were merged into a path including an even number of gates in the path from the signal line 13h to the output of the circuit, Of the paths leading to the output of the circuit, the two gates 10h and 11h, which were merged into the path including an odd number of gates therein, are paired one by one to form NOR gates 14h, 15h and 16h, and It is a fan-in destination gate for 17h.

FIG. 19 is an example of the one-input gate representation of the multi-input signal line L shown in step 435 of FIG. In FIG. 19 (a), 1l, 2l, 3l, 4l, 5l,
6l, 7l, and 8l represent NOR gates. here,
The output gate of the circuit is the NOR gate 11 and the gate L that is the target of the one-input gate expression is the NOR gate 3l. FIG. 19B shows a state in which the NOR gate 3l is converted into a one-input gate representation. 9l and 10l are NOR
A gate obtained by copying the gate 2l is represented, and 11l, 12l, and 13l are gates obtained by converting the NOR gate 3l into a one-input gate representation. The circuit of FIG. 19 (b) and FIG. 19 (a)
Is equivalent to the circuit. The NOR gate 3l which has been the object of the one-input gate expression is converted to the gate 11l,
Like 12l and 13l, they are all 1-input gates.

FIG. 20 is a detailed flowchart of the final judgment shown in step 425 of FIG. Step 4
In 41, the logical value of the only first signal line H is y. In step 442, when the output of the circuit is represented by a function f (y) of y, what happens to f (y) is checked. If f (y) is 1 or ^ y (inversion of y), Step 443
If y, the process branches to step 444. If 0, the process branches to step 447. In step 443,
The logical value of the head signal line H is set to 0. In step 444,
The logical value of the head signal line H is set to 1. At step 445, the logical value of the head signal line H is justified. Here, the justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the signal line. That is. In step 446, it is determined that the two target logics are not equivalent. In step 447, it is determined that the two target logics are equivalent.

FIG. 21 is a detailed flowchart of the counterexample pattern generation shown in step 600 of FIG. In step 601, it is checked whether or not the input edge has been reduced in the equivalence verification processing of the two target logics.
If so, the process branches to step 602, and if not, the process ends. In step 602, the implication operation is performed by setting the logical value to the input edge whose output logical value is set to 0 or 1 while performing the logical equivalence verification process on the circuit that has undergone the reduction process. .. Step 603
Then, the connection of the signal line whose logical value is 0 or 1 is disconnected. In step 604, the floating gate whose output number becomes 0 during the processing of step 603 is deleted. In step 605, it is checked whether or not the output logical value of the circuit has become 1, and if it becomes 1, the process branches to step 609, and if it does not become 1, the process branches to step 606. In step 606, the output logic value of the output gate of the circuit is set to 1 to perform the implication operation. In Step 607, Step 6
The unjustified signal line generated during the implication of 06 is justified to the head signal line. Here, justification is to determine the logical value up to the leading signal line so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the signal line. is there. In step 608, the leading signal line having an output logical value of 0 or 1 is justified up to the input edge. Here, the justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the signal line. That is.

(Embodiment 2) Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a flow chart showing the outline of the second embodiment of the logical equivalence verification processing according to the present invention.
This is the same as the case of the above embodiment. However, in the second embodiment, in step 100 included in the flowchart of FIG. 2, the NAND conversion of the target logic is performed instead of the NOR conversion of the target logic. Also, in the second embodiment, in step 200, the exclusive OR is negated instead of the exclusive OR of the two target logic circuits.

In the following, only the changing unit of the process associated with the NAND conversion will be described.

FIG. 3 is a detailed flowchart of the NOR conversion of the target logic shown in step 100 of FIG.

FIG. 22 is a conversion example of an equivalent expression used in the NAND conversion of the target circuit shown in step 105 of FIG. 3, which is a 2-input AND, NAND, OR, and NO.
Each R gate is represented by a combination of NAND gates.

FIG. 5 is a detailed flowchart of the processing for determining whether the output of the circuit shown in step 300 of FIG. 2 is always 0.

FIG. 7 is a detailed flowchart of updating the head signal line shown in step 302 of FIG. (The unbounded signal line that is adjacent to the bounded signal line is called the top signal line. The unbounded signal line is a signal that cannot be reached from any branch point in the circuit to the output side. A bound signal line is a signal line that can be reached by tracing from an appropriate branch point in the circuit to the output side.) FIG.
6 is a detailed flowchart of the reduction processing of the circuit shown in step 303 of FIG.

FIG. 10 is a detailed flowchart of the reduction process A1 shown in step 334 of FIG. However, the second
In this embodiment, in step 351, the implication is performed by setting the logical value of R to 0 instead of setting the logical value of R to 1 and performing implication.

FIG. 12 is a detailed flowchart of the reduction process A shown in step 335 of FIG. However, in the second embodiment, in step 371, the logical value of R is set to 1
Is set to the logical value of R instead of carrying out the backward implication, and backward implication is carried out. In step 379, the logical value of R is set to 0 and the logical value of R is taken instead of carrying out the forward implication. Set 1 to perform forward implication. Further, step 38
In 3, instead of determining that the two target logics are equivalent, it is determined that the two target logics are not equivalent, and in step 384, instead of determining that the two target logics are not equivalent, the two target logics are equivalent. Determined to be

FIG. 14 is a detailed flowchart of the reduction process B shown in step 339 of FIG. However, in the second embodiment, in step 392, the logical value of H is set to 0.
Instead of performing the forward entailment, the logical value of H is set to 1 to perform the forward implication, and in step 394, the logical value of H is set to 1 and the logical value of H is set to 0 instead of performing the forward implication. And set the forward implication. Further, step 399
, It is determined that the two target logics are not equivalent, instead of determining that the two target logics are equivalent.
At 00, instead of determining that the two target logics are not equivalent, it is determined that the two target logics are equivalent.

FIG. 16 is a detailed flowchart of the reduction of the head signal line shown in step 305 of FIG.

FIG. 17 is a detailed flowchart of the processing for one step of the reduction of the head signal line shown in step 412 of FIG.

FIG. 23 is a detailed flowchart of the final determination shown in step 425 of FIG. Step 45
In 1, the logical value of only the first signal line H is set to y.
In step 452, when the output of the circuit is represented by the function f (y) of y, the value of f (y) is checked,
If f (y) is equal to 0 or y, go to step 453.
If y (inversion of y), go to step 454 and identify 1
If so, the process branches to step 457. In step 453, the logical value of the head signal line H is set to 0. Step 4
At 54, the logical value of the head signal line H is set to 1. At step 455, the logical value of the head signal line H is justified. Here, justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the target signal line. In step 456, it is determined that the two target logics are not equivalent. In step 457, 2
The two target logics are judged to be equivalent.

FIG. 21 is a detailed flowchart of the counterexample pattern generation shown in step 600 of FIG. However,
In the second embodiment, instead of setting the output logic value of the output gate of the circuit to 1 and performing the implication operation in step 606, the output logic value of the output gate of the circuit is set to 0 and the implication operation is performed.

(Embodiment 3) After the reduction processing, the operation of assigning a logical value to the signal line is tried, and the output of the circuit becomes 1
A third embodiment for determining whether or not such an input pattern that

FIG. 24 is a detailed flowchart for determining whether or not the output of the 1-output circuit obtained in step 200 of FIG. 2 shown in step 300 of FIG. 2 is always 0. Figure 2
Steps 301b to 304b shown in FIG. 4 are the same as Steps 301 to 304 shown in FIG. 5, and FIG. 24 executes Step 305b instead of Step 305 in FIG. If the determination process is not completed up to step 304b, in step 305b, it is checked whether or not the two target logics are equivalent by trying various assignments of logical values to the circuit that has undergone the reduction process 303b. judge.

FIG. 25 is a detailed flowchart of the judgment by the logical value allocation trial shown in step 305b of FIG. In step 411a, step 30 in FIG.
The implication operation is performed by setting 1 to the output logical value of the circuit obtained in 3b. During the implication operation, it is checked each time whether the output signal line of each gate that is the target of the implication operation is an unjustified signal line, and if it is an unjustified signal line, the output signal line is registered. Here, the unjustified signal line is an output signal line of a gate such that the operation result of the input logical value does not match the output logical value. In Step 412a, Step 4
The unjustified signal lines generated by the implication operation of 11a are justified up to the head signal line, and if all the unjustified signal lines are justified, it is determined that the two target logics are not equivalent. on the other hand,
If justification does not work well no matter how the logical values are assigned, it is determined that the two target logics are equivalent.
Here, the justification is to determine the logical value up to the head signal line so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the target signal line. In step 413a, if it is determined in step 412a that the two target logics are not equivalent, step 41
If the two target logics are determined to be equivalent, the process ends. In step 414a, the leading signal line whose logical value is set to either 0 or 1 is justified up to the input edge. Here, justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the target signal line.

FIG. 26 is a detailed flowchart of the justification for the unjustified signal line shown in step 412a of FIG. In step 421a, 0 is set to the contradiction flag. The inconsistency flag means whether or not an inconsistency (a situation in which two values of 0 and 1 are about to be set on the same signal line via different routes during the implication operation) in the implication operation of steps 426a and 430a. The contradiction flag is 0, which means that there is no contradiction, and the contradiction flag is 1, which means that the contradiction has occurred. In step 422a, if the contradiction flag is 0, the process branches to step 423a;
Branch to 8a. In step 423a, if there is an unjustified signal line in the circuit, the process branches to step 424a, and if not, the process branches to step 427a. At step 424a, one is selected from the registered unjustified signal lines. In step 425a, backward tracing is performed using the unjustified signal line selected in step 424a as a starting point. In the backward tracing, the signal line having the logical value X is traced from the signal line which is the starting point toward the input side,
Set a logical value for the signal line at the location where the tracking was terminated. In step 426a, an implication operation is performed based on the logical value set in step 425a. In step 427a, it is determined that the two target logics are not equivalent. Step 428a
Now, backtrack to resolve the contradiction. In step 429a, if it is determined in step 428a that the two target logics are equivalent, the process ends, and if not, the process branches to step 430a. In step 430a, an implication operation is performed based on the logical value of the signal line changed in the process of the back track 428a.

FIG. 27 is a detailed flowchart of the backward tracking shown in step 425a of FIG. Step 4
At 31a, a gate whose output signal line is an unjustified signal line is set as a target gate UIOBJN for backward tracing, and a logical value of the unjustified signal line is set to a target value UIOBJL. In step 432a, if the output signal line of UIOBJN is the head signal line, the process branches to step 434a, and if it is not the head signal line, the process branches to step 433a. In step 433a, which is an input gate for UIOBJN, and
One gate having an output logical value of X is selected, the selected input gate is set to UIOBJN, and UIOBJN is updated. The value of UIOBJL is updated by inverting (0 → 1, 1 → 0) the value of UIOBJL. In step 434a, the output logical value of UIOBJN is set to UIO.
Set the value of BJL. In step 435a, the ID of the UIOBJN is added to a predetermined stack provided in the processing device 10.
Pile up.

FIG. 28 is a detailed flowchart of the backtrack shown in step 428a of FIG. In step 441a, it is checked whether or not the stack is empty. If the stack is empty, the process branches to step 447a, and if not, the process branches to step 442a. In step 442a,
It is checked whether or not the logic value of the gate corresponding to the ID stacked on the top of the stack has been inverted, and if it has been inverted, the process branches to step 443a.
Branch to 6a. In step 443a, the stack 1
The output logical value of the gate corresponding to the ID piled up at the top is X
Return to. In step 444a, an implication operation is performed. In step 445a, the gate is removed from the stack, i.e., the ID stacked on top of the stack is removed.
In step 446a, the I on top of the stack
Invert the output logic value of the gate corresponding to D (0 → 1, 1 →
0) In step 447a, it is determined that the two target logics are equivalent.

FIG. 29 is a specific example of the determination process by the logical value allocation trial shown in step 305b of FIG.
In FIG. 29, 1r, 2r, 3r, 4r, 5r, 6
r and 7r each represent a NOR gate, 8r represents an input edge, and 9r, 10r, 11r, 12r, 13
Each of r, 14r, and 15r represents a signal line. Figure 2
Reference numeral 9 (a) represents a circuit in which the output logical value of the circuit obtained by the reduction processing 303b shown in FIG. 24 is set to 1 and the implication operation is performed (step 411a). Here, since the output logical values of the NOR gates 2r and 3r whose output signal lines are the signal lines 9r and 10r are 1 and the input logical values are all X, the signal lines 9r and 10r are both unjustified. It is a signal line. FIG. 29B is a diagram in which 9r is selected from the unjustified signal lines included in the circuit shown in FIG. 29A to perform backward tracking (steps 424a and 42).
5a). Here, (target gate and target value for backward tracking) is (2r, 0) → (4r, 1) → (6r, 0) → (8r,
1) is sequentially updated (step 433a). FIG. 29
(C) is a diagram showing a result of performing the implication operation 426a by setting the final target value 1 to the final target gate 8r for backward tracking (step 434a). Here, the gate 8r for which the logical value is set is stacked on the stack (step 435).
a). Here, although the output logical value of the NOR gate 3r is 0, the NOR operation result of the input logical values 0 and 0 is 1, and thus the logical values are inconsistent. FIG. 29D is the same as FIG.
9C is a diagram showing a result of performing backtracking and implication operations on the circuit shown in FIG. 9C (step 428). FIG.
a, step 429a). The logical value of the gate 8r stacked on the top of the stack is inverted from 1 to 0 (step 446
a) When the implication operation is performed, a contradiction occurs in the NOR gate 2r this time. FIG. 29E is a diagram showing a result of backtracking further performed on the circuit of FIG. 29D. Since the gate 8r stacked on the top of the stack has already undergone the logic value inversion, the logic value is returned to X (step 443a), the implication operation is performed (step 444a), and the gate to be the target of the next backtrack is selected. A search is performed, but since the stack is empty, it is determined that the two target logics are equivalent (step 447a).

FIG. 30 is a detailed flowchart of another embodiment of backward tracking shown in step 425a of FIG. Steps 431b, 433b, 43 shown in FIG.
4b and 435b are steps 431 shown in FIG.
a, 433a, 434a, and 435a. In the embodiment shown in FIG. 30, the target gate (UIOBJN)
The target tracking (UIOBJL) is updated once and the backward tracking is terminated.

[0061]

According to the present invention, the logical equivalence verification can be efficiently performed by removing the redundancy of the circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of a logical equivalence verification process in the present invention.

FIG. 2 is a flowchart of a logical equivalence verification process in the present invention.

FIG. 3 is a NO of the target logic shown in step 100 of FIG.
It is a detailed flowchart of R conversion.

[FIG. 4] NO of AND, NAND, OR, and NOR gates
It is a figure showing the R conversion example.

5 is a detailed flowchart of the logical equivalence determination shown in step 300 of FIG.

FIG. 6 is a diagram illustrating a specific example of a process of collecting common logic.

FIG. 7 is a detailed flowchart of updating the head signal line shown in step 301 of FIG.

FIG. 8 is a diagram illustrating an example of updating a head signal line.

9 is a detailed flowchart of the reduction processing shown in step 303 of FIG.

FIG. 10 is a reduction process A1 shown in step 334 of FIG.
2 is a detailed flowchart of FIG.

FIG. 11 is a diagram illustrating an example of reduction processing A1.

12 is a detailed flowchart of the reduction process A shown in step 335 of FIG.

FIG. 13 is a diagram illustrating an example of reduction processing A.

14 is a detailed flowchart of the reduction processing B shown in step 339 of FIG.

FIG. 15 is a diagram illustrating an example of reduction processing B.

16 is a detailed flowchart of the reduction of the input edge shown in step 305 of FIG.

FIG. 17 is a detailed flowchart of the input edge reduction (1 step) shown in step 412 of FIG. 16;

FIG. 18 is a diagram illustrating an example of reduction of an input edge.

FIG. 19 is a diagram illustrating an example of standardization of a circuit.

20 is a detailed flowchart of the final determination shown in step 425 of FIG.

FIG. 21 is a detailed flowchart of generation of counterexample pattern data shown in step 600 of FIG.

FIG. 22 shows AND, NAND, O in the second embodiment.
It is a figure showing the example of a conversion of R and a NOR gate.

FIG. 23 is step 42 of FIG. 16 in the second embodiment.
6 is a detailed flowchart of the final determination shown in FIG.

FIG. 24 is a detailed flowchart of the logical equivalence determination shown in step 300 in the third embodiment.

FIG. 25 is a detailed flowchart of the determination by the logical value allocation trial shown in step 305b of FIG.

FIG. 26 is a detailed flowchart of justification of the unjustified signal line shown in step 412a of FIG. 25.

FIG. 27 is a detailed flowchart of the backward tracking shown in step 425a of FIG.

FIG. 28 is a detailed flowchart of the backtrack shown in step 428a of FIG.

FIG. 29 is a diagram showing a specific example of the determination by the logical value allocation trial shown in step 305b.

FIG. 30 is a detailed flowchart of another embodiment of the backward tracking shown in step 425a of FIG. 26.

FIG. 31 is a configuration diagram of a computer system that implements the present invention.

FIG. 32 is a diagram showing a configuration of circuit data necessary for processing of the present invention.

FIG. 33 is a diagram showing a structure of Boolean expression data necessary for the processing of the present invention.

FIG. 34 is a diagram showing a configuration of counterexample pattern data necessary for the processing of the present invention.

[Fig. 35] Fig. 35 is a diagram illustrating an example of a BDD representation of combinational logic.

[Explanation of symbols]

1 ... Target combination circuits X and Y, 2 ... Target combination circuits X and Y
1 output circuit Z obtained by combining with an exclusive OR, 3 ... Reduction processing, 4 ... Reduction of head signal line, 5 ... Final circuit (1 head signal line 1 output circuit).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takahiro Nakata 1099, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Inside the Hitachi, Ltd. Systems Development Laboratory (72) Inventor Takao, 1099, Ozen-ji, Aso-ku, Kawasaki, Kanagawa Ceremony Company Hitachi Systems Development Laboratory (72) Inventor Yukio Ikitani 1 Horiyamashita, Hadano City, Kanagawa Pref., Kanagawa Plant, Hiritsu Manufacturing Co., Ltd. (72) Yuko Shimoda 1 Horiyamashita, Hadano City, Kanagawa Prefecture Hitachi Compu Ta Engineering Co., Ltd.

Claims (13)

[Claims] 1. A first step of converting a target combinational logic into an equivalent circuit composed of only one kind of basic gate in the logic equivalence verification for judging the equivalence of one combinational logic,
The corresponding input edges of the two combinational circuits obtained in the first step are combined into one, and the exclusive OR or the exclusive OR of the outputs is output depending on the type of the basic gate selected as a constituent element of the circuit in the first step. A second step of making a negative, a third step of determining whether or not there is an input pattern in which the output of the one-output circuit obtained in the second step is a true value, and the second step in the third step When it is determined that there is an input pattern in which the output of the one-output circuit obtained in step is a true value, that is, when it is determined that the two target combination circuits are not equivalent, the value is determined in the third step. And a fourth step of generating a counterexample pattern from the deterministic logical value information of the input edge. 2. In the third step of claim 1, a plurality of gates representing the same logic in the one output circuit are set to one.
A first step of arranging into one gate, and a set of gates in the circuit that can control the output to a true value or a false value independently of each other in the circuit obtained in the first step, and to the input side from this set of gates By recognizing the existence of the branch point of the signal line, the signal line at the boundary between the circuit area reachable from the branch point and the circuit area unreachable from the branch point is updated to the output side from the gate set. The second step to do,
A third step of reducing redundant logic in the circuit obtained in the second step, a fourth step of converting the circuit obtained in the third step into one head signal line and one output circuit, and the one head signal. A fifth step of determining whether or not there is an input pattern in which the output of the line 1 output circuit is a true value. 3. The second step of claim 2, wherein a logical value 0 or 1 is set in the head signal line having a branch, a forward implication is performed, and a basic gate whose implication has stopped is registered. Whether the output logical value of the registered basic gate can be independently controlled to 0 or 1 by controlling the step and the logical value of the head signal line of the logical value X on the input side of the registered basic gate to 0 or 1 In the second step of determining whether or not the output logical value of the registered basic gate can be independently controlled to 0 or 1 in the second step, the logical value is 0 or 1 in the first step. Thirdly, the head signal line is converted to a circuit updated from the registered basic gate to the output side by disconnecting the connection of the signal line determined in the third step.
A logical equivalence verification method comprising: 4. In the third step of claim 2, a redundant partial circuit on the input side of the multi-input basic gate in the circuit obtained in the second step of claim 2 is provided. For the first step of reduction and for the head signal line such that any path to the output base gate of the circuit obtained in the first step is composed of an even number of base gates, the logical value of the head signal line Is performed as a false value to perform forward implication, disconnect the connection of the signal line whose logical value is determined to be 0 or 1, and use an odd number of basic gates for any route to the output basic gate of the circuit obtained in the first step. A second step of performing forward implication on the head signal line to be configured by setting the logical value of the head signal line to a true value and disconnecting the connection of the signal line whose logical value is set to 0 or 1 Logical equivalence verification method. 5. The first step of claim 4, wherein the implication is performed backward with the logical value of the multi-input basic gate as a true value, and the basic gate where the backward implication has stopped is registered. And a second step of removing an unnecessary logic circuit between the multi-input basic gate and the registered basic gate, and if the logic value of the registered basic gate is a false value, the registered basic gate and the multi-input basic gate , And if the logic value of the registered basic gate is a true value, connect the wire between the registered basic gate and the multi-input basic gate by interposing a 1-input basic gate. A logical equivalence verification method comprising a third step. 6. The head signal line according to the fourth step of claim 2 for each of the remaining head signal lines except one of the circuits obtained in the third step of claim 2. To an equivalent circuit in which all the basic gates on the path from the circuit to the output basic gate of the circuit are 1-input basic gates that invert logical values except for the output basic gate and the input basic gate for the output basic gate. All the basic gates except the output basic gate on the path leading to the output basic gate of the equivalent circuit and the input basic gate for the output basic gate in the first signal line in the equivalent circuit. And a second step of removing a one-input basic gate that inverts a logical value. 7. The second basic step of claim 6 is an input basic gate for the output basic gate of the equivalent circuit, wherein an even number of logical values are provided between the input basic gate and the head signal line. , {A1, ..., Am}, and {B1, ..., Bn} the entire set having one-input basic gates that invert an odd number of logical values. }, A basic gate Cij (1 <= i <= m, 1 <= j <= n) is newly provided,
Connect all connections between Cij and all input basic gates connected to Ai, connect all connections between Cij and all input basic gates included in Bj, and connect all input basics connected from Ai to Ai. Separate the gate and output basic gate,
A method for verifying logical equivalence in which all input basic gates and output basic gates connected from Bj to Bj are disconnected. 8. In the third step of claim 1, a plurality of gates representing the same logic in the one output circuit are set to one.
A first step of arranging into one gate, and a set of gates in the circuit that can control the output to a true value or a false value independently of each other in the circuit obtained in the first step, and to the input side of this gate set. By recognizing the existence of the branch point of the signal line, the signal line at the boundary between the circuit area reachable from the branch point and the circuit area unreachable from the branch point is updated to the output side from the gate set. The second step to do,
The third step of reducing the redundant logic in the circuit obtained in the second step, and the output of the one-output circuit by trying the logic value assignment of the signal line in the circuit obtained in the third step A logical equivalence verifying method, which comprises a fourth step of determining whether or not an input pattern having a true value exists. 9. In the fourth step of claim 8, the true value is set to the output logical value of the circuit obtained in the third step of claim 8, and the implication operation is performed. 1
Step, and the unjustified signal line generated in the first step is justified, and if the justification is successful, it is determined that there is an input pattern in which the output of the one output circuit becomes a true value, and how If it cannot be justified even if a value is assigned, the second step of determining that there is no input pattern that makes the output of the one output circuit a true value, and the output of the one output circuit in the second step are A logical equivalence verifying method comprising a third step of validating a leading signal line having a logical value of 0 or 1 up to an input edge when it is determined that an input pattern having a true value exists. 10. In the second step of the claim 9, while the inconsistency due to the implication operation does not occur, the presence or absence of the unjustified signal line is checked, and if there is no unjustified signal line, the 1 output circuit. It is determined that there is an input pattern whose output is a true value, and if there is, an unvalidated signal line is selected, and the first step of performing backward tracking and implication operation from the unvalidated signal line; A logical equivalence verifying method comprising a backtrack and a second step of performing an implication operation when a contradiction occurs due to the operation. 11. In the first step of claim 10, whether or not there is an unjustified signal line is checked, and if there is no unjustified signal line, an input pattern in which the output of the one output circuit is a true value is obtained. It is determined that there is, and if there is, one unjustified signal line is selected, a gate having the unjustified signal line as an output signal line is a backward tracking target gate, and a logical value of the unjustified signal line is a target value. Then, until the backward tracking target gate becomes a gate that outputs the first signal line, the backward tracking target gate becomes one of the input gates of the logical value X of the backward tracking target gate, and the target value becomes the inverted logical value of the target value. A logic equivalence verification method that repeats updating, sets the final target value on the output signal line of the final rear tracking target gate, and performs an implication operation. 12. In the second step of claim 10, if all the signal lines having the logical values set in the backward tracing in the first step of claim 9 have already been inverted. , It is determined that there is no input pattern in which the output of the one-output circuit becomes a true value, and if not, the signal line whose logic value has not been inverted has the logic value set at the end. Then, all the logical values of the signal lines whose logical values are set after the signal line are returned to X, the logical value of the signal line is inverted, and the implication operation is performed. 13. In the first step of claim 10, the presence or absence of an unjustified signal line is checked, and if there is no unjustified signal line, an input pattern in which the output of the one output circuit is a true value is obtained. It is determined that there is, and if there is, one unjustified signal line is selected, a gate having the unjustified signal line as an output signal line is a backward tracking target gate, and a logical value of the unjustified signal line is a target value. Then, the backward tracking target gate is updated to one of the input gates of the logical value X of the backward tracking target gate, the target value is updated to the inverted logical value of the target value, and the target value is set to the output signal line of the backward tracking target gate. , A logical equivalence verification method that performs implications.