JPH055774A - Method for judging theoretical undetected trouble of logical circuit - Google Patents

Abstract

PURPOSE:To efficiently judge theoretical undetected trouble by unifically grasping the redundancy of a circuit to remove a redundant part. CONSTITUTION:All of the circuits X containing undetected trouble (f) among the divided combination circuits of an objective logical circuit are extracted. These circuits X are converted to equivalent circuits expressed by an NOR gate and these circuits are further converted to a 1 output combination circuit Y becoming output 1 only with respect to a test pattern removing undetected trouble. The circuits are simplified by simplifying processing 3 and a set of gates wherein a signal wire branch point is present on an input side are extracted and the reduction 4 of a head signal wire is performed to renew the head signal wire on an output side. The processings 3, 4 are repeatedly applied to the circuit Y to obtain the l head signal line 1 output circuit of a final circuit 5. It is judged whether a test pattern wherein the output of this circuit becomes 1 is present and, when no test pattern is present with respect to any divided circuits X, the trouble (f) is judged to be one wherein a test pattern is not present in a whole circuit, that is, theoretical undetected trouble.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault diagnosis of a logic circuit, and more particularly to a principle undetected fault judgment method and a test pattern generation method of a logic circuit composed of combinational circuits.

[0002]

2. Description of the Related Art In recent years, as the scale of logic circuits has increased, the mainstream of fault diagnosis methods for logic circuits is to directly generate fault diagnosis data for the entire logic circuit, and to combine multiple logic circuits with each other. The scan design method is being applied to the following, in which partial failure diagnosis data is generated for each combinational circuit and edited to generate failure diagnosis data for the entire logic circuit. Along with this, the circuit to be subjected to the fault diagnosis is also changed from the sequential circuit to the combinational circuit, and the fault diagnosis data generation method for the combinational circuit, especially the test pattern generation method and the fault simulation method, which are the core of the method, becomes an important issue. ing. Test pattern generation methods for combinational circuits have so far been performed by the Boolean differentiation method, D algorithm, PODEM (Path Oriented DE).
cision making), FAN (FAN out-oriented test gene
ration algorithm) has been proposed so that a test pattern with a high detection rate can be generated. Fan
The test pattern generation method based on the algorithm is IE
EE TRANSACTIONS ON COMPUTERS, VOL.C-32, NO.12, DEC
EMBER 1983, pp.1137-1144. However, regarding an undetected failure, it is often unclear whether the test pattern exists but could not be generated, or is undetected because the test pattern does not exist in principle. This is because the test pattern generation problem is the NP perfection problem, and in the worst case, it takes a processing time of the order of the exponent of the circuit scale, so that the test pattern generation is given up midway. In such cases,
There is a method of efficiently generating a test pattern for a fault having a test pattern, and determining a fault not having a test pattern as a theoretical undetected fault in principle. For this method, to date, MH
Schulz et al.'S method is IEEE TRANSACTIONS ON COMPUTER-AI
DED DESIGN, VOL.8, NO.7, JULY 1989, pp.811-816.

The method proposed by MH Schulz et al.
By adding the function of extended implication operation and unique activation to the test pattern generation system called RATES,
Although the logical value is uniquely determined, the logical value cannot be determined by the conventional implication operation or the like, and the logical value is set to the signal line. As a result, the need for backtracking can be grasped at an early stage, and the range of searching for a solution (test pattern) in the space of all input patterns can be narrowed. Can be removed.

When the logical value of the output signal line of the gate is uniquely determined by the logical value of the input signal line of the gate, the logical value is assigned to the output signal line, or by the logical value of the output signal line of the gate. The conventional implication operation is to assign a logical value to an input signal line of a gate when the logical value of the input signal line is uniquely determined. On the other hand, the extended implication operation means that two sets of signal lines, which are not necessarily in the relationship of an input signal line and an output signal line of a certain gate, are processed by the logical value of one set of signal lines When the logical value of the signal line of the set is uniquely determined, the logical value is assigned.

FIG. 27 shows an example of the extended implication operation. Figure 2
In FIG. 7, 1m and 2m are AND gates, 3m, and 4
m, 5m, and 6m represent signal lines. In FIG. 27A, the logical value of the signal line 4m is 0. In this case, the logical values of the signal lines 5m and 6m are not uniquely determined, but since the AND gates 1m and 2m express the same logic, the signal lines 3m and 4m must always take the same logical value. Therefore, as shown in FIG. 27 (b), 0 is assigned to the logical value of the signal line 3m.

Unique activation means activating all gates through which a failure signal must pass. That is, when assigning a signal value to an input signal line of a gate through which a failure signal does not necessarily pass, a value is assigned if the gate is AND or NAND, and 0 is assigned if it is OR or NOR. ..

FIG. 28 shows an example of unique activation. FIG. 28
In, 1n, 2n, 6n, 7n, and 8n are AND
Gates 3n, 4n, and 5n represent OR gates, 9n represents a hypothetical failure point, and 10n, 11n, and 12n represent signal lines. In FIG. 28A, the logical value of 9n is 0/1 (0 in a normal circuit, 1 in a failed circuit). This fault signal must propagate to the output edge in order to generate the test pattern. In the circuit of FIG. 28A, the gates 2n, 5n, and 8n are gates that must pass through in order for the fault signal to propagate to the output edge.
In FIG. 28B, 1 is assigned to the signal lines 10n and 12n,
The state in which 0 is assigned to 1n and the gates 2n, 5n, and 8n are activated is shown. On the other hand, the gates 3n and 4n and the gates 6n and 7n do not assign signal values because it is currently unknown whether the signal passes through any of the gates.

[0008]

The principle of undetected failure determination and test pattern generation has the following problems with the increase in scale of logic circuits.

First, since the redundancy of the circuit tends to be wider and more complicated due to the increase in the scale of the logic circuit, it is difficult to efficiently perform the principle undetected failure determination. There is.

Secondly, for the same reason as the first problem, there is a problem that a test pattern may not be efficiently generated although it exists.

Thirdly, since the scale of the logic circuit becomes large, the circuit range that must be searched for the principle of undetected failure determination also becomes large, so that it takes a lot of processing time for each circuit search. There is a point.

The method of MH Schulz et al. Is effective in solving the first and second problems, but since this method does not catch the redundancy of the circuit in a unified manner, it does not deal with a new kind of redundancy. Has a drawback that its redundancy cannot be grasped unless a function of extended implication operation corresponding to it is newly added. Moreover, this method does not solve the third problem.

A first object of the present invention is to integrally grasp the redundancy of the circuit which makes it difficult to determine the principle undetected failure in order to solve the first problem, and remove the redundant portion. By doing so, it is possible to efficiently perform the principle of undetected failure determination.

A second object of the present invention is to integrally grasp the redundancy of the circuit which makes the test pattern generation difficult in order to solve the second problem and remove the redundant portion. It is to generate test patterns efficiently.

A third object of the present invention is to cut out the circuit range that must be searched for making a principle undetected failure determination in order to solve the third problem, thereby cutting out the principle undetected. It is to shorten the processing time for failure determination.

[0016]

In order to achieve the above first object, the present invention executes the following steps. From the combinational circuits obtained by dividing the target logic circuit, all those including the target undetected fault location are extracted.
Step. Second step of converting each divided circuit into an equivalent circuit expressed only by NOR gates. The output becomes 1 for the input pattern (test pattern) for detecting the target undetected fault in the equivalent circuit converted in the second step,
The third step of converting this equivalent circuit into a 1-output circuit in which the output becomes 0 for other input patterns.
A fourth step of determining whether or not there is an input pattern in which the output of the one-output circuit obtained in the third step is 1.
Furthermore, the fourth step consists of the substeps described below. Multiple gates that represent the same logic in the target 1 output circuit
The first substep of the fourth step, which is replaced by one gate. In the circuit obtained in the first sub-step, the set of gates in the circuit that can control the outputs to be 0 or 1 independently of each other, and in which the branch point of the signal line exists on the input side from this set of gates By extracting, the signal line (leading signal line) at the boundary between the circuit area reachable from the branch point and the circuit area unreachable from the branch point is updated to the output side from the set of extracted gates. Second substep of the four steps. The third substep of the fourth step, which reduces the redundant logic in the circuit obtained in the second substep. The fourth substep of the fourth step of converting the circuit obtained in the third substep into one head signal line 1 output circuit. A fifth substep of the fourth step of determining whether or not there is an input pattern in which the output of the one head signal line 1 output circuit obtained in the fourth substep is 1. Further, as a result of the judgment in each divided circuit, if the test pattern does not exist in any divided circuit, it is judged that the failure is a failure in which the test pattern does not exist in the whole circuit, that is, a principle undetected failure. If there is a test pattern in any of the divided circuits, the fifth step of outputting this test pattern.

In order to achieve the above-mentioned second object, the present invention is directed to an undetected fault which is determined in the above-mentioned fourth step to have an input pattern for setting the output of the one-output circuit to 1. A test pattern is generated using the deterministic logical value information of the input edge whose value has been determined in the process of four steps.

In order to achieve the above-mentioned third object, the present invention executes the following three steps in the above-mentioned first step. A first step of extracting a combinational circuit including a target undetected fault and divided so that all outputs have one output. For each 1-output division circuit, the 1-output circuit, its input edge, and an output signal line in which either the 0 stuck-at fault or the 1 stuck-at fault in the 1-output divided circuit has already been detected are surrounded, Extracting a circuit area (relevant area) of the minimum unit necessary for the determination of a theoretical undetected failure from the one-output partial circuit that includes the target undetected failure point therein. 2 steps. Third step of removing related regions that overlap each other.
That is, in the present invention, the process is limited to the relevant area to perform the principle undetected failure determination.

[0019]

The above-mentioned first means is a set of gates in a circuit that can control the output to 0 or 1 independently of each other in the circuit by substituting a plurality of gates representing the same logic in the circuit with one gate. , By recognizing that there is a branch point of the signal line on the input side of this set of gates, the signal line on the boundary between the circuit area reachable from the branch point and the circuit area not reachable from the branch point By updating the (lead signal line) to the output side from the above gate set, and further simplifying the redundant logic in the circuit, it is possible to unify the redundancy of the circuit that makes it difficult to determine the principle undetected failure. Capture and remove redundant circuit parts,
This makes it possible to efficiently make a principle undetected failure determination.

The above-mentioned second means uniformly grasps the redundancy of the circuit which makes the test pattern generation difficult, and
It is possible to eliminate redundant circuit parts and efficiently generate a test pattern.

The above-mentioned third means shortens the processing time of the principle undetected failure determination.

[0022]

EXAMPLE FIG. 29 shows the configuration of a computer system for implementing the present invention. The processing device 10 stores a principle undetected failure determination program 20 which is a processing program of the present invention, and an external storage device, which is a target of the failure determination of the present invention, includes logic circuit data 30 and assumptions regarding failures in the circuit. The failure tables 40 and 45 and the test pattern data 50 that is the output result are stored.

The logic circuit data 30 shown in FIG. 29 is shown in FIG.
0 shows the configurations of the output assumed failure table 40, the input assumed failure table 45, and the test pattern data 50 in (b1), (b2), and (c) of FIG. 45, respectively.

The logic circuit data 30 shown in FIG.
The logic circuit that is the target of failure determination is represented as a connection relationship between each gate, and the data is stored in a table format. The data corresponding to each gate is composed of fields as described below. Item number (N
o. ) 31 is a number indicating an entry in the table corresponding to each gate. The element (ELEMENT) 32 includes an ID 32a for identifying each gate and the type (KIN) of the gate.
D) 32b. Output gate (OUTP
In the field of (UT GATE) 33, the output value 33a of the element 32, the number of gates (OUT NUM.) 33b connected to the output side of the element 32, and the IDs 33c and 33d of these gates are stored. Input gate (I
NP GATE) 34 field contains element 32
The number of gates connected to the input side of (IN NU
M. ) 34a, IDs (I1, I2 ...
・) 34b, 34d and input values (V1, V2 ...) 3
4c and 34e are stored. Control data (CONT
Information indicating whether the output signal line of the element 32 is a bound signal line, a head signal line, or an unbound signal line other than the head signal line is registered in the field of (ROL DATA) 35. The number of gate stages from the output gate of the circuit of the element 32 is registered in the field of the number of output stages (PO LEVEL) 35b.

As an example, each entry in FIG. 30 stores data corresponding to the logic circuit shown in FIG. As shown in FIG. 30, input / output edges are also registered in the logic circuit data 30.

The output hypothetical fault table 40 and the input hypothetical fault table 45 shown in (b1) and (b2) of FIG. There is.

In the output assumed failure table 40, the data corresponding to each output failure is made up of the following fields. The item number (No.) 41 is a number indicating the entry of the table corresponding to each output failure.
The fault (FAULT) 42 is an ID 42 that identifies on which output signal line of each gate each output fault is supposed.
a and its failure type (KIND) 42b. Related Area (RELATED REGION) 43
In the field of, the ID 43a of the output gate of the related area including the failure 42, and whether the failure 42 is determined to be a principle undetected failure in the related area having the output gate of the ID 43a, or a test pattern is determined to exist,
Alternatively, information indicating which state the determination process is not yet performed is stored.

In the input assumed failure table 45, the data corresponding to each input failure is composed of the fields described below. The item number (No.) 46 is a number indicating the entry of the table corresponding to each input failure.
The fault (FAULT) 47 is an ID 47 for identifying on which input signal line of each gate each input fault is supposed.
a, INPUT ID 47 identifying which input gate the contingent fault input signal line of element 47a is connected to
b and its failure type (KIND) 47c. Related area (RELATED REGION)
In the field 48, whether the fault 47 is determined to be a principle undetected fault or the test pattern is present in the ID 48a of the output gate of the related region including the fault 47 and the related region having the ID 48a as the output gate. Alternatively, information indicating whether the determination processing is not yet performed is stored.

In the entry of FIG. 45 (b1), as an example, the fault included in the logic circuit shown in FIG. 7 (a) described later is an output fault (0 stuck-at fault of the output signal line of the gate 6b).
The data when it is regarded as is stored. Figure 45 (b
In the entry 2), as an example, data is stored when the above failure is regarded as an input failure (0 stuck-at failure of the input signal line 12b of the gate 5b).

In the test pattern data 50 shown in FIG. 45 (c), test pattern data obtained as a result of the failure judgment of the present invention, that is, data to be input to the input edge is stored in a table format. The data corresponding to each input edge is composed of fields as described below. The item number (No.) 51 is a number indicating the entry of the table corresponding to each input edge. ID5
2 is an identifier of each input edge. Setting value (VALU
E) 53 is a value to be set at the input edge. Case N
o. (TEST CASE No.) 54 is a number for identifying various test patterns. Failure (FAU
LT) 55, case No. (TESTCASE N
o. ) Entry number 4 in the contingency table indicating for which contingency the 54 test pattern was generated
1 is stored. In the entry of FIG. 45C, as an example, data corresponding to the input edge of the logic circuit shown in FIG. 7A described later is stored.

First, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the flow of each part of the principle undetected failure determination processing of the logic circuit according to the present invention. Reference numeral 1 represents the target combination circuit X and the target undetected failure f. 1
On the other hand, consider Problem 1 “Is the failure f a principle undetected failure in the circuit X?”. 2 is a 1-output combination circuit Y obtained by performing a conversion on the fault f for the 1-target combination circuit X.
Represents. On the other hand, considering Problem 2 “Is the output of circuit Y always 0?”, Problem 1 and Problem 2 are equivalent.
Reference numeral 3 represents a process for simplifying the circuit by a reduction process or the like. Four
The reduction of the head signal line of means the process of reducing the head signal line by one. Here, of the unbounded signal lines, the one that is adjacent to the bounded signal line is called the head signal line. An unbound signal line is a signal line that cannot be traced from any branch point in the circuit to the output side, and a bound signal line is traced from an appropriate branch point in the circuit to the output side. A signal line that can be reached as you go. By repeatedly performing the processes 3 and 4 on the circuit Y, the final circuit (1 head signal line 1 output circuit) shown by 5 is finally obtained. For 5,
Considering the problem 3 "Is the output of the final circuit always 0?", The problem 3 is equivalent to the problem 2, and since the number of head signal lines that affect the output of the circuit is one, Problem 3 can be easily solved. If the answer to question 3 is YES, then the answers to questions 2 and 1 are also YES, and if the answer to question 3 is NO, then the answers to question 2 and 1 are also NO.

FIG. 2 is a diagram showing a first principle of undetected failure judgment processing and test pattern generation processing of a logic circuit according to the present invention.
3 is a flowchart showing the outline of the embodiment of FIG. In step 100, the relevant area is examined for all undetected faults. In step 200, it is checked whether or not there is a related area that has not yet been the target of the principle undetected failure determination. In Step 300, 1 is set to the related area that is not yet the target of the principle undetected failure determination.
Choose one. In step 400, the related area selected in step 300 is converted into an equivalent circuit composed of only NOR gates and input edges. In step 500, it is checked whether or not the related area converted in step 400 is a related area having an undetected failure, and the related area is not yet subjected to the principle undetected failure determination. If yes, go to step 600, otherwise go to step 200
Branch to. In step 600, of the undetected faults included in the related region converted in step 400, one that has not been subjected to theoretical undetected fault determination for this related region is selected. In Step 700, Step 60
It is determined whether the target undetected fault selected in 0 is a theoretical undetected fault in the relevant region converted in step 400. In sub-step 700a of step 700, the output becomes 1 for the relevant area subjected to the NOR gate conversion in step 400 for the test pattern in the relevant area of the target undetected fault, and for the other input patterns. Convert to a 1-output circuit so that the output becomes 0. In sub-step 700b of step 700, it is determined whether or not the output of the one-output circuit obtained in sub-step 700a becomes 0 for any input pattern. In step 900, it is checked whether or not it is determined in step 700 that the test pattern can be generated in the relevant area including the target undetected fault. If yes, the process branches to step 1000, and if not, the process branches to step 500. To do. In step 1000, a test pattern for the target undetected fault is generated. In step 1100, the judgment result in each related area of each undetected failure is edited,
It is determined whether each undetected fault is a principle undetected fault in the entire circuit.

Each of these steps will be described in detail below with reference to the drawings.

FIG. 3 is a detailed flowchart of the related area investigation shown in step 100 of FIG. Step 1
In 01, it is checked whether or not there is an undetected failure in which the range of the related area including the undetected failure point is not checked, and if there is, the process branches to step 102 and exists. If not, the process ends. Step 10
In step 2, one of the undetected faults, for which the range of the related area including the undetected fault has not been investigated, is selected. In step 103, it is checked whether or not there is a cone that has not been subjected to the relevant area check for the undetected fault selected in step 102.
4; if not, branch to step 101. Here, the cone is a one-output partial circuit of a partial circuit (combinational circuit) divided on the premise of the scan design method. In step 104, one cone that has not been subjected to the relevant area investigation for the undetected fault selected in step 102 is selected. In step 105, step 102
The gate on the most input side among the gates that passes through all the paths from the undetected fault location selected in step 4 to the output edge of the cone selected in step 104 is DM, and the region RG that outputs DM is related. It is a candidate for the area. Step 1
Steps 06 to 109 are processes for determining whether or not the related area candidate can be finally determined as the related area. In step 106, the output destination of the gate DM is sent to step 10
It is checked whether or not the output edge of the cone selected in 4 exists, and if it exists, the region RG is obviously a related region, so the process branches to step 110, and if it does not exist, the process branches to step 107. In step 107, it is checked whether or not the test pattern of the stuck-at-0 fault or the stuck-at-1 fault of the output signal line of the gate DM has been generated. If the test pattern has been generated, the process branches to step 108, and the stuck-at-0 fault occurs. Alternatively, if no test pattern is generated for any one stuck-at fault, step 109 is performed.
Branch to. In step 108, it is checked whether or not the fan-out destination gates in the cone of all gates other than the gate DM in the partial circuit RG are included in all the partial circuits RG. If not, the process branches to step 109. In step 109, among the gates through which all the paths from the gate DM to the output edge of the cone pass, the one on the most input side is newly set as DM, and a new related region candidate that outputs this DM is selected. RG. In step 110, the relevant area is determined to be RG.

FIG. 4 shows an example of the related area. 1a, 2
Symbols a and 3a represent cones including undetected faults, and 4a represents hypothetical fault locations of undetected faults. Reference numerals 5a and 6a represent signal lines, and it is assumed that the 0 stuck-at fault or the 1 stuck-at fault on the signal lines 5a and 6a has been detected. Reference numeral 7a represents a relevant area for the undetected fault cones 1a and 2a, and 8a represents a relevant area for the cone 3a. In cone 1a,
DM and RG are 9 each at the time when the related area is determined.
a and 7a.

FIG. 5 shows the NO of the AND, NAND, OR, NOR gates used in step 400 of FIG.
It is an example of conversion of an equivalent expression by an R gate.

FIG. 6 is a detailed flowchart of the principle undetected failure determination in the relevant area of the object undetected failure shown in step 700 of FIG. Step 701 shown in FIG. 6 corresponds to 700a in FIG. 2, and steps 702 to 706 also correspond to 700b in FIG. In step 701, the related area converted into the NOR gate in step 400 of FIG. 2 has an output of 1 for the test pattern in the related area of the target undetected fault, and for the other input patterns. 1 so that the output becomes 0
Convert to output circuit. In Step 702, Step 7
It is checked whether or not there are two or more gates having the same set of inputs in the circuit converted by 01, and if they exist, those gates are replaced by one gate. In step 703, the head signal line is updated. Here, of the unbounded signal lines, the one that is adjacent to the bounded signal line is called the head signal line. An unbound signal line is a signal line that cannot be traced from any branch point in the circuit to the output side, and a bound signal line is traced from an appropriate branch point in the circuit to the output side. A signal line that can be reached as you go. Step 70
In 4, the circuit is reduced to simplify complicated parts in the circuit. In step 705, it is checked during the reduction process of step 704 whether the target undetected fault is determined to be a principle undetected fault in the relevant region, or whether it is determined that a test pattern can be generated. If any determination is made, the process is terminated, and if no determination is made, the process branches to step 706.
In step 706, the head signal line included in the circuit subjected to the reduction process in step 705 is reduced,
Convert to 1 head signal line 1 output circuit.

FIG. 7 shows an example of circuit conversion for the assumed fault shown in step 701 of FIG. FIG. 7A shows a circuit diagram of a related area to be converted.
Reference numerals 1b, 2b, 3b, 4b, 5b, and 6b denote NOR gates forming the related regions, and 7b, 8b, 9b, and 10.
b and 11b represent input edges of the relevant region, and 12b
Represents the assumed failure location of the target undetected failure, and the failure type is assumed to be the 1 stuck-at failure. FIG. 7 (b) shows a hypothetical failure point 1
In the converted circuit diagram for 2b, 13b represents the output NOR gate of the newly added circuit. In FIG. 7B, N
The connection between the OR gates 6b and 5b is disconnected, and NOR
A new wire is connected between the gates 6b and 13b.
In the circuit shown in FIG. 7B, the output of the NOR gate 13b becomes 1 for the input pattern in which the failure signal is set at the assumed failure location 12b in FIG. It has the property that the output of the NOR gate 13b becomes 0 for the input pattern. FIG. 7C is a circuit diagram after the portion from the assumed failure point 12b to the first branch point is converted, and 14b shows the first branch point from the assumed failure point 12b to the output side. In FIG. 7C, the connection between the input edge 9b and the NOR gate 5b is cut off,
A new connection is connected between the input edge 9b and the NOR gate 13b. In the circuit shown in FIG.
In (a), a failure signal is set at the assumed failure point 12b,
Further, the output of the NOR gate 13b becomes 1 for an input pattern in which a failure signal is propagated from the assumed failure location 12b to the branch point 14b, and the output of the NOR gate 13b becomes 0 for other input patterns. It has the property of becoming. .. FIG. 7D is a circuit diagram after copying the portion from the branch point 14b to the output of the related area. 15b,
16b, 17b, 18b, and 19b are NOR
Gates 1b, 2b, 3b, 4b, and 5b are copied. Here, for example, the copied portion (the NOR gates 1b, 2b, 3b, 4b, and 5b) is a normal circuit that takes a logical value when there is no failure, and the copied portion (the NOR gates 15b and 16b). , 17b,
The partial circuit composed of 18b and 19b) represents a fault circuit that takes a logical value when a fault exists. (Conversely, the copied portion may be regarded as a faulty circuit and the copied portion as a normal circuit.) Further, the portion 20b constitutes an exclusive OR. In FIG. 7D, the output logic value of the NOR gate 5b (the input side cut of the normal circuit) is set to 0, and the output logic value of the NOR gate 19b (the input side cut of the fault circuit) is set to 1 and the front is set. Make implications. The connection of the signal lines having the logical value of 0 or 1 (the output line of the gates 5b and 19b) and the gate having the output logical value of 0 and the input logical value of 1 (the gate 17b having the input logical value of 1 and By disconnecting all the input connections connected to 18b) and deleting the gate whose output floats due to this, the circuit of FIG. 7 (e) is obtained. In the circuit shown in FIG. 7E, a failure signal is set in the assumed failure point 12b in FIG. 7A, and an input in which the failure signal is propagated from the assumed failure point 12b to the output of the relevant region. The output of the NOR gate 13b becomes 1 for a pattern, that is, a test pattern in the relevant region of the target assumed fault, and the output of the NOR gate 13b becomes 0 for other input patterns.

FIG. 8 shows a concrete example of the processing for putting together the common logic shown in step 702 of FIG. In FIG. 8A, 1c, 2c, 3c, 4c, 5c, 6c, and 7c represent NOR gates. Here, NOR gates 4c and 5c
Both have NOR gates 6c and 7c as fan-in destination gates. Therefore, since the NOR gates 4c and 5c have the same input relationship, the NOR gates 4c and 5c
Can be combined into one. FIG. 8B shows N
By disconnecting the connection between the OR gates 6c, 7c and 5c and the connection between the NOR gates 5c, 2c and 3c, and connecting the connection between the NOR gates 4c and 2c and 3c, as shown in FIG.
It shows a circuit in which the NOR gate 5c in (a) is replaced with 4c.

FIG. 9 is a detailed flowchart for updating the head signal line shown in step 703 of FIG. Here, of the unbounded signal lines, the one that is adjacent to the bounded signal line is called the head signal line. An unbound signal line is a signal line that cannot be traced from any branch point in the circuit to the output side, and a bound signal line is traced from an appropriate branch point in the circuit to the output side. A signal line that can be reached as you go. In step 711, it is checked whether or not there is a head signal line having a branch that has not been checked for the possibility of updating the head signal line. If it exists, the process branches to step 712, and if it does not exist. The process ends. In step 712, one of the head signal lines having a branch that has not been investigated for the possibility of updating the head signal line is selected, and this head signal line is set to H. Step 71
In 3, the logical value of the head signal line H is set to 0 and the forward implication is performed. In step 714, all the gates of the output logical value X (where the input logical value has changed but the output logical value has not changed to X) due to the forward implication are independent of each other. Is checked to see if the gate can control the logical value of the output signal line to 0 or 1, that is, whether the gate can be traced to the input edge through the gate having the output logical value X having no branch point.
If not traceable, the process branches to step 718. In step 715, the connection of the signal line whose logical value is 0 or 1 is disconnected. In step 716, the gate connected to the bound signal line whose output has floated during the process of step 715 is deleted. At step 717, the logical value of the head signal line H is justified. Here, the justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the signal line as the output signal line matches the logical value of the signal line. Step 718
Then, it is checked whether the logical value of the head signal line H is 1, and if it is 1, the process branches to step 719, and if it is not 1, the process proceeds to step 7
Branch to 20. In step 719, the logical value of the head signal line H is set to X, and the forward implication is performed. Step 720
Then, the logical value of the head signal line H is set to X to perform the forward implication. In step 721, the logical value of the head signal line H is set to 1
Set to and do forward implications. Then, the processing from step 714 is repeated.

FIG. 10 shows an example of updating the head signal line shown in step 703 of FIG. In FIG. 10A, 1d, 2d, 3d, 4d, 5d, 6d, 7d and 8d are NOR gates, and 9d, 10d, 11d and 12 are NOR gates.
d and 13d are the input edges, 14d, 15d, 16
d, 17d, and 18d represent signal lines. Here, the leading signal lines are the signal lines 14d, 15d, 16d, and 17d.
Then, the signal line 14d has a branch, and the signal lines 15d, 16
d and 17d have no branch. FIG. 10B shows a state in which the output logical value of the head signal line 14d having a branch is set to 0 and the forward implication is performed (step 713). Here, the implication is not possible, and the output logical value is X. N
The OR gates 2d, 3d, and 4d have no branch from 2d to the input edge 9d, 3d to the input edge 10d, and from the 4d to the input edge 11d, and are traced to the input edge through the gate whose output logical value is X. Because you can
The outputs of the NOR gates 2d, 3d, and 4d can be controlled to 0 or 1 independently of each other. FIG.10 (c) is FIG.
In (b), the connection of the signal line having a logical value of 0 or 1 is separated (step 715), and the output logical value of the input edge 12d is set to 1 by justifying the signal line 14d. That is, in FIG. 10B, the logic operation of the signal line 12d is performed so that the NOR operation result of the logic values of the signal lines 12d and 13d becomes equal to the logic value 0 of the signal line 14d, for example, as shown in FIG. Assign 1 to the value. In FIG. 10 (c), the head signal line is only the signal line 18d, and the head signal line is the signal lines 14d, 15d, 16d, and 17 of FIG. 10 (a).
The signal line 18d on the output side is updated from d.

FIG. 11 is a detailed flowchart of the reduction processing of the circuit shown in step 704 of FIG. There are three types of reduction processing of the circuit, that is, reduction processing A1, reduction processing A, and reduction processing B. In the reduction process A1, redundant logic on the input side of the output gate of the circuit is reduced. In the reduction process A, the redundant logic on the input side of the multi-input gate (excluding the output gate of the circuit) of the circuit is reduced. Simplification process B
Then, the influence of the logical value of the head signal line on the output logical value of the circuit is examined, and when the logical value of the head signal line is 0, the logical value has only the effect of making the output of the circuit 1 If the logic value of the head signal line is fixed by assigning 0, and the logic value of the head signal line has a value of 1, the logic value of the head signal line only has the effect of trying to set the output of the circuit to 1. Assign 1 to and fix. In step 731, it is checked whether or not there is a multi-input gate capable of the reduction processing A. If it exists, the process branches to step 732, and if it does not exist, the process branches to step 737. In step 732, the multi-input gate R capable of the reduction processing A is selected. In step 733, it is checked whether the multi-input gate R is the output gate of the circuit, and if so, the process branches to step 734, and if not, the process branches to step 735. In step 734, the reduction process A1 is performed on the multi-input gate R. In step 735, the reduction process A is performed for the multi-input gate R. In step 736, in the middle of the reduction process A1 or the reduction process A, it is determined that the target undetected fault is a theoretical undetected fault in the relevant region, or a test pattern can be generated. It is checked whether or not there is any, and if any of them is determined, the process is ended, and if none of them is determined, the process branches to step 731. In step 737, it is checked whether or not there is a leading signal line that can be subjected to the reduction processing B.
The process branches to 8 and if not present, the process ends. (The unbound signal line that is adjacent to the bound signal line is called the top signal line. The unbound signal line is a signal that cannot be reached from any branch point in the circuit to the output side. The bound signal line is a signal line that can be reached by tracing from an appropriate branch point in the circuit to the output side.) In step 738, a reduction process B is possible. The signal line H is selected. In step 739, the reduction process B is performed on the first signal line H. In step 740, it is determined whether or not the target undetected fault is a theoretical undetected fault in the relevant area or it is possible to generate a test pattern during the reduction process B. Look up,
If either is determined, the process is terminated, and if neither is determined, the process branches to step 741. In step 741, it is checked whether or not there is a new head signal line that can be subjected to the reduction processing B, and if it exists, step 73
8; otherwise, to step 742. In step 742, it is checked whether or not there is a multi-input gate capable of the reduction processing A.
The process branches to 32, and if not present, the process ends.

FIG. 12 is a detailed flowchart of the reduction process A1 shown in step 734 of FIG. In step 751, the output logical value of the multi-input gate R is set to 1 and an implication operation is performed. However, the implication operation is not performed on the unbound signal line. In step 752, there is a contradiction during the implication operation (2 of 0 and 1 via different paths during the implication operation).
It is checked whether or not a situation in which two values are about to be set in the same signal line) occurs, and if so, the process branches to step 758, and if not, the process branches to step 753. In step 753, a gate having an output logical value of 0 and an input logical value of 0 or X and a gate having a leading signal line having a logical value of 0 or 1 as an output signal line are registered as termination gates (including input edges). To do. In step 754, the connection of the signal line whose logical value is 0 or 1 is disconnected. Step 755
Then, for each terminal gate, if the output signal line is the first signal line, the output logical value is justified up to the input edge, and if the output signal line is a bound signal line and the number of inputs is 1 or more. A wire is connected between the terminal gate and the multi-input gate R. Here, justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the signal line. is there. In step 756,
Whether or not the number of inputs of the multi-input gate R is 0 is checked. If 0, the process branches to step 757, and if not 0, the process branches to step 759. In step 757, it is assumed that a test pattern can be generated for the target undetected fault in the relevant area.
In step 758, the target undetected fault is determined to be a theoretical undetected fault in the relevant region. Step 75
In 9, the floating gate whose number of outputs becomes 0 during processing is deleted. In step 760, all the logical values of the signal line having the logical value of 0 or 1 are returned to X.

FIG. 13 is an example of the reduction process A1 shown in step 734 of FIG. In FIG. 13 (a),
1e, 2e, 3e, 4e, 5e, 6e, 7e, 8e, and 9e are NOR gates, 10e, 11e, 12e, 1
3e and 14e represent input edges. Here, the multi-input gate that is the target of the reduction process A1 is the NOR gate 1e. FIG. 13B shows a state in which the output logical value of the NOR gate 1e is set to 1 and implication is performed (step 751). Here, the NOR gates 8e and 9e and the input edge 10e are termination gates (step 7).
53). FIG. 13C shows connection of signal lines of logical value 0 or 1 (1e and 2e, 1e and 3e, 1e and 4e, 2e and 8).
e, 2e and 6e, 3e and 5e, 4e and 6e, 5e and 8
e, 5e and 10e, 6e and 9e, and 6e and 10e) are disconnected (step 754), the termination gates 8e and 9e are connected (step 755), and the floating gates 2e, 7e, and 11e are deleted. The state in which (step 759) has been performed is shown.

FIG. 14 is a detailed flowchart of the reduction process A shown in step 735 of FIG. In step 771, the output logical value of the multi-input gate R is set to 1 to perform backward implication. However, no implication is applied to unbound signal lines. In step 772, it is checked whether or not there is a contradiction during implication (a situation in which two values of 0 and 1 are about to be set to the same signal line through different routes during implication operation), and if so, the step is executed. If it does not occur, the process branches to step 773. Step 77
In 3, a gate having an output logical value of 0 and an input logical value of 0 or X and a gate having a leading signal line having a logical value of 0 or 1 as an output signal line are registered as termination gates. In step 774, the circuit on the output side from the termination gate is separated into a part that converges on the multi-input gate R and a part that does not converge. In step 775, forward implication is performed from the termination gate in the part where the termination gate converges to the multi-input gate R. However, no implication is made on the output side of the multi-input gate R. In step 776, it is checked whether or not a contradiction occurs during the forward implication, and if so, step 77.
If not, the process branches to step 777. In step 777, the connection of the signal lines having a logic value of 0 or 1 is disconnected from all the input connections of the gates having an output logic value of 0 and having an input logic value of 1. In step 778, for each termination gate, if this termination gate has an output logic value of 0 and the number of inputs is 1 or more, or if the output signal line of this termination gate is a leading signal line with a logic value of 0, A wire is connected between the terminal gate and the multi-input gate R. If this end gate has an output logic value of 1 and the number of inputs is 1 or more, or if the output signal line of this end gate is a head signal line having a logic value of 1, a new NOR is newly added.
A gate N is added, and wiring is connected between the termination gate and the NOR gate N and between the NOR gate N and the multi-input gate R. In step 779, the output logical value of the multi-input gate R is set to 0 to perform the forward implication. In step 780, among the signal lines on the output side of the multi-input gate R, the connection of the signal line whose logical value is 0 or 1 is disconnected. In step 781, the floating gate whose output number becomes 0 during the above processing is deleted. In step 782, the output logical value of the circuit is examined. If 0, the process branches to step 783, if 1 to step 784, and if X, branches to step 785. In step 783, the target undetected failure is determined to be a theoretical undetected failure in the relevant area. In step 784, it is determined that the target undetected fault can generate a test pattern in the relevant area. Step 7
In 85, all the logical values of the signal line whose logical value is 0 or 1 are X.
Return to.

FIG. 15 is an example of the reduction process A shown in step 735 of FIG. In FIG. 15A, 1
f, 2f, 3f, 4f, 5f, 6f, 7f, 8f, and 9f represent NOR gates. Here, the multi-input gate R that is the target of the reduction process A is the NOR gate 2f. FIG. 15B shows a state in which the output implication value of the NOR gate 2f is set to 1 and backward implication is performed (step 7).
71). Here, the termination gates are NOR gates 4f and 7
f and 8f (step 773). FIG. 15 (c)
Shows a state in which the circuits from the NOR gates 4f, 7f, and 8f to the output side are separated into a portion that converges on the NOR gate 2f and a portion that does not converge (step 774). Figure 15
In (c), NOR gates 10f and 11f are newly added to separate the circuit. FIG. 15D shows NO.
In the portion where the R gates 4f, 7f, and 8f converge to the NOR gate 2f, the state in which the forward implication is performed from the NOR gates 4f, 7f, and 8f is represented (step 77).
5). In FIG. 15 (e), the connection of signal lines having a logical value of 0 or 1 and the output logical value of 0, and the input logical value of 1
Shows the state in which all the input connections of the gate in which there is a line are disconnected (step 777), the processing of the termination gate (step 778) and the removal of the floating gate (step 781) have been performed.

FIG. 16 shows a detailed flowchart of the reduction processing B shown in step 739 of FIG. In step 791, it is checked whether or not all paths from the head signal line H to the output of the circuit are composed of an even number of gates (including input edges), and if they are, step 7
It branches to 92, and if not configured, it branches to step 793. In step 792, the output logical value of the head signal line H is set to 0 to perform forward implication. In step 793, it is checked whether or not all the paths from the head signal line H to the output of the circuit are composed of an odd number of gates (including input edges), and if they are structured, the process branches to step 794 to configure. If not, the process ends. In step 794, the logical value of the head signal line H is set to 1 to perform forward implication. In step 795, the connection of the signal line whose logical value is 0 or 1 is disconnected. In step 796, the logical value of the head signal line H is justified. Here, the justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the signal line. That is. In step 797, the number of outputs is 0 during processing.
Delete the floating gate that became. In step 798,
If the output logical value of the circuit is 0, the process branches to step 799.
If it is 1, the process branches to step 800, and if it is X, the process ends. In step 799, the target undetected failure is determined to be a theoretical undetected failure in the relevant area. In step 800, it is determined that the target undetected fault can generate a test pattern in the relevant area.

FIG. 17 shows an example of the reduction process B shown in step 739 of FIG. In FIG. 17A, 1
g, 2g, 3g, 4g, and 5g represent NOR gates, 6g and 7g represent input edges, and 8g represents signal lines. Here, the leading signal line H that is the target of the reduction processing B is the signal line 8g, and there are two paths from the signal line 8g to the output of the circuit, that is, the input edge 7g → the NOR gate 4g → the NOR gate 2g. → NOR gate 1g and input edge 7g → NOR gate 5g → NOR gate 3g →
Both NOR gates 1g are 4 including the input edge 7g.
It consists of individual gates. When the logical value of the head signal line 8g is set to 0, the output logical values of the NOR gates 4g and 2g tend to become 1 and 0, respectively, and the NOR gate 5
Since the output logical values of g and 3g tend to be 1 and 0, respectively, the logical value of the NOR gate 1g tends to be 1.
On the contrary, when the logical value of the signal line 8g is set to 1, the logical value of the NOR gate 1g tends to become 0. NOR gate 1g
If the output of the circuit obtained by fixing the logical value of the signal line 8g so that the output logical value of the above, that is, the output logical value of the circuit is 1, is always 0, the output of the original circuit also has the property of always 0. FIG. 17B shows a state in which the logical value of the signal line 8g is set to 0 and the forward implication is performed (step 792). FIG. 17C shows a state in which the connection of the signal line whose logical value is 0 or 1 in FIG. 17B is separated (step 795) and the floating gates (gates 2g and 4g) are deleted (step 797). Represent

FIG. 18 is a detailed flowchart of the reduction of the head signal line shown in step 706 of FIG. In step 811, it is checked whether or not the number of head signal lines is 1, and if it is 1, it is not necessary to carry out reduction, so that the process branches to step 825, and if it is not 1, the process branches to step 812. In step 812, one step of reduction of the first signal line is processed. Steps 813 to 829 shown in FIG. 18 are the reduction processing 704 shown in FIG.
Is the same as However, in step 819, reduction processing B
It is checked whether or not there is a head signal line H that can be processed. If it exists, the process branches to step 820, and if it does not exist, the process branches to step 811. Further, in step 824, it is checked whether or not there is a multi-input gate R capable of the reduction processing A. If it exists, the process branches to step 814, and if it does not exist, the process branches to step 811. In step 825, it is examined how the output value of the circuit is determined by the logical value of the head signal line H, and whether the target undetected fault is a theoretical undetected fault in the relevant area or a test pattern is generated. Is possible.

FIG. 19 is a detailed flowchart of the processing for one step of reduction of the head signal line shown in step 812 of FIG. (Of the unbounded signal lines, the one that is connected to the bounded signal line via a branch point or a gate is called the top signal line. The unbounded signal line is traced from any branch point in the circuit to the output side. However, the bound signal line is a signal line which can be reached by tracing from an appropriate branch point in the circuit to the output side.) In step 831, the reduction is performed. Check whether there is a possible leading signal line, and if there is, a step 8
If not, the process branches to step 834. Here, the reduction-capable head signal line means that the number of output stages on an arbitrary path from the head signal line to the output of the circuit is two or more, and all the gates included in the path are one-input gates. It is a certain head signal line.
In step 832, the head signal line H which can be reduced
Select one. In step 833, the reduction of the reduction-enabled head signal line H is performed. Step 83
At 4, one multi-input bound signal line L having two or more output stages is selected. In step 835, the vicinity of the multi-input bound signal line L is replaced with an equivalent expression using one input gate instead of the multi-input bound signal line L. Here, "neighborhood" means
In this embodiment, the first stage and the second stage on the input side of the gate of interest are
It is the range of the output side gate to the destination.

FIG. 20 shows an example of the reduction of the reduction-enabled head signal line shown in step 833 of FIG. In FIG. 20 (a), 1h, 2h, 3h, 4
h, 5h, 6h, 7h, 8h, 9h, 10h, and 11
h represents a NOR gate, and 12h represents an input edge. Here, the output gate of the circuit is the NOR gate 1h, the head signal line H targeted for reduction is the signal line 13h, and the outputs of the NOR gates 8h and 9h are the signal line 13h.
The output from the NOR gates 10h and 11h is an odd number among the paths from the signal line 13h to the output of the circuit. It merges with the one that consists of the gate. FIG. 20B shows a circuit in which the signal line 13h is reduced. Here, NOR gates 2h, 3h, 4
h, 5h, 6h, 7h, and the input edge 12h are deleted, and NOR gates 14h, 15h, 16h, and 17h are newly added. Further, in FIG. 20A, from the signal line 13h, two gates 8h and 9h, which were joined to a path including an even number of gates in the path from the signal line 13h to the output of the circuit, Of the paths leading to the output of the circuit, the two gates 10h and 11h, which were joined to the path including an odd number of gates therein, are paired one by one to form NOR gates 14h, 15h, 16h, and It is a fan-in destination gate for 17h.

FIG. 21 is an example of the one-input gate representation of the multi-input signal line L shown in step 835 of FIG. In FIG. 21 (a), 1l, 2l, 3l, 4l, 5l,
6l, 7l, and 8l represent NOR gates. here,
The output gate of the circuit is the NOR gate 11 and the gate L that is the target of the one-input gate expression is the NOR gate 3l. FIG. 21B shows a state in which the NOR gate 3l is converted into a one-input gate representation. 9l and 10l are NOR
A gate obtained by copying the gate 2l is represented, and 11l, 12l, and 13l are gates obtained by converting the NOR gate 3l into a one-input gate representation. The circuit of FIG. 21 (b) and FIG. 21 (a)
Is equivalent to the circuit. The NOR gate 3l which has been the target of the one-input gate expression is converted to the gate 11l,
Like 12l and 13l, they are all 1-input gates.

FIG. 22 is a detailed flowchart of the final determination shown in step 825 of FIG. Step 8
In 41, the logical value of the only first signal line H is y. In step 842, when the output of the circuit is represented by a function f (y) of y, what happens to f (y) is examined. If f (y) is 1 or ^ y (inversion of y), Step 843
If y, the process branches to step 844. If 0, the process branches to step 847. In step 843,
The logical value of the head signal line H is set to 0. In step 844, the logical value of the head signal line H is set to 1. Step 845
Then, the logical value of the head signal line H is justified. here,
Justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the signal line. .. In step 846, it is determined that the target undetected fault can generate a test pattern in the relevant area. In step 847, the target undetected fault is determined to be a theoretical undetected fault in the relevant area.

FIG. 23 is a detailed flowchart of the test pattern generation shown in step 1000 of FIG.
In step 1001, it is checked whether or not the reduction of the input edge is performed in the principle undetected failure determination processing in the relevant area of the target undetected failure. If yes, the process branches to step 1002, and if not, step 1
Branch to 009. In step 1002, the logical value is set to the input edge whose output logical value is set to 0 or 1 when the theoretical undetected failure determination processing is performed on the circuit that has been subjected to the reduction processing, and the implication is implied. Do the operation. In step 1003, the connection of the signal line whose logical value is 0 or 1 is disconnected. In step 1004, the floating gate whose output number becomes 0 during the process of step 1003 is deleted. In step 1005, the output logical value of the circuit is 1
Check if it becomes 1 and if it becomes 1, step 1
Branch to 009, and if it does not become 1, step 10
It branches to 06. In step 1006, the output logic value of the output gate of the circuit is set to 1 and the implication operation is performed. In step 1007, the unjustified signal lines generated during the implication of step 1006 are justified up to the head signal line. here,
The justification is to determine the logical value up to the leading signal line so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the signal line. In step 1008, the leading signal line having an output logical value of 0 or 1 is justified to the input edge. Here, the justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the signal line. That is. In step 1009, the test pattern in the relevant area of the generated target undetected fault is assigned to the input of the relevant area, and the output of the output gate of the relevant area is output to the input outside the relevant area in the entire logic circuit. A test pattern (already generated) in the entire circuit with 0 stuck-at fault or 1 stuck-at fault of the signal line is assigned and merged.

FIG. 24 is a detailed flowchart for editing the determination result shown in step 1100 of FIG. In step 1101, it is checked whether or not there is an undetected fault for which the determination result has not been edited. If it exists, the process branches to step 1102, and if it does not exist, the process ends. In step 1102, one undetected fault for which the determination result has not been edited is selected. Step 1103
Then, it is checked whether or not the undetected fault is determined to be a principle undetected fault in all relevant areas including the undetected fault selected in step 1102, and if it is determined, the process branches to step 1104 to make a determination. If not, the process branches to step 1105. In step 1104, the undetected fault selected in step 1102 is determined to be a theoretical undetected fault in the entire circuit. In step 1105, it is checked whether or not the test pattern of the undetected fault selected in step 1102 is generated. If it is generated, the process branches to step 1106, and if it is not generated, the process branches to step 1107. In step 1106, it is determined that the undetected fault selected in step 1102 has successfully generated the test pattern. In step 1107, it is determined that it has not been possible to determine whether the undetected failure selected in step 1102 is a principle undetected failure.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a flow chart showing the outline of the second embodiment of the principle undetected failure judgment processing and test pattern generation processing of the logic circuit according to the present invention, which is the same as the case of the first embodiment. .. However, in the second embodiment, as shown in FIG.
In step 400 included in the flowchart of
NAN of related area instead of performing NOR conversion of related area
Perform D conversion.

In the following, only the process changing unit associated with the NAND conversion will be described.

FIG. 3 is a detailed flowchart of the related area check shown in step 100 of FIG.

FIG. 25 is a conversion example of an equivalent expression used in the NAND conversion of the related area shown in step 400 of FIG. 2, in which AND, NAND, OR, and NOR gates are expressed by combinations of NAND gates. Is.

FIG. 6 is a detailed flow chart of the process shown in step 700 of FIG. 2 for determining whether the target undetected failure is the principle undetected failure in the relevant area. In step 701, the NAND gate converted related area is set so that the output becomes 0 for the test pattern in the related area of the target undetected fault and the output becomes 1 for other input patterns. Convert to a 1-output circuit.

FIG. 9 is a detailed flowchart for updating the head signal line shown in step 703 of FIG. (The unbound signal line that is adjacent to the bound signal line is called the top signal line. The unbound signal line is a signal that cannot be reached from any branch point in the circuit to the output side. A bound signal line is a signal line that can be reached by tracing from an appropriate branch point in the circuit to the output side.) FIG.
1 is a detailed flowchart of the reduction processing of the circuit shown in step 704 of FIG.

FIG. 12 is a detailed flowchart of the reduction process A1 shown in step 734 of FIG. However, in the second embodiment, in step 751, instead of setting the logical value of R to 1 and performing implication, the logical value of R is set to 0 and implication is performed.

FIG. 14 is a detailed flowchart of the reduction process A shown in step 735 of FIG. However, the second
In this embodiment, instead of setting the logical value of R to 1 and performing the backward implication in step 771, setting the logical value of R to 0 and performing the backward implication, and in step 779, R
Instead of setting the logical value of R to 0 to perform forward implication, set the logical value of R to 1 to perform forward implication. Further, step 7
In step 83, it is determined that a test pattern can be generated instead of determining that the target undetected fault is a principle undetected fault in the relevant area. In step 784, the target undetected fault is not generated. Instead of judging that it is possible, it is judged that it is a principle undetected failure.

FIG. 16 is a detailed flowchart of the reduction process B shown in step 739 of FIG. However, the second
In this embodiment, instead of setting the logical value of H to 0 and performing the forward implication in step 792, the logical value of H is set to 1 to perform the forward implication, and the logical value of H is set to 1 in step 794. Instead of setting and performing the forward implication, the logical value of H is set to 0 to perform the forward implication. Further, step 79
In step 9, it is determined that a test pattern can be generated instead of determining that the target undetected fault is a principle undetected fault in the relevant region, and in step 800, the target undetected fault is not generated. Instead of determining that it is possible, it is determined that there is a principle undetected failure in the relevant area.

FIG. 18 is a detailed flowchart of the reduction of the head signal line shown in step 706 of FIG.

FIG. 19 is a detailed flowchart of the processing for one step of reduction of the head signal line shown in step 812 of FIG.

FIG. 26 is a detailed flowchart of the final determination shown in step 825 of FIG. Step 85
In 1, the logical value of only the first signal line H is set to y.
In step 852, when the output of the circuit is represented by a function f (y) of y, it is examined what value f (y) has, and
If f (y) is equal to 0 or y, go to step 853.
If y (inversion of y), go to step 854 and identify 1
If so, the process branches to step 857. In step 853, the logical value of the head signal line H is set to 0. Step 8
At 54, the logical value of the head signal line H is set to 1. In step 855, the logical value of the head signal line H is justified. Here, justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the target signal line. In step 856, it is determined that the target undetected fault can generate a test pattern in the relevant area. In step 857, the target undetected failure is determined to be a theoretical undetected failure in the relevant area.

FIG. 23 is a detailed flowchart of the test pattern generation shown in step 1000 of FIG. However, in the second embodiment, in step 1006, the implication operation is performed by setting the output logic value of the circuit output gate to 0 instead of setting the output logic value of the circuit output gate to 1 and performing the implication operation.

FIG. 24 is a detailed flowchart for editing the judgment result shown in step 1100 of FIG.

A third embodiment of the present invention will be described with reference to the drawings.

FIG. 31 is a diagram showing an outline of the principle undetected failure judgment processing of a logic circuit including an uncertain input edge according to the present invention. Other than 21 is the same as that shown in FIG. For Problem 1, consider Problem 1 “Is the failure f a principle undetected failure in the circuit X?”. Reference numeral 2 represents a one-output combination circuit Y obtained by converting the combination circuit X, which is the target of 1, with respect to f. On the other hand, considering Problem 2 “Is the output of circuit Y always 0?”, Problem 1 and Problem 2 are equivalent.
Reference numeral 21 represents a 1-output combination circuit Y'which does not include any uncertain input edges obtained by converting the 2-output 1-output combination circuit. Considering the problem 3, “Is the output of the circuit Y ′ always 0?”, The problems 2 and 3 are equivalent.

On the other hand, considering problem 4, "Is the output of the final circuit always 0?" 1
Since they are individual, Problem 4 can be easily solved. Problem 4
If the answer is YES, the answers to questions 3, 2 and 1 are also Y
If ES and the answer to question 4 is NO, then question 3 and question 2
The answer to question 1 is also NO.

The flow of the principle undetected failure determination processing in the logic circuit is the same as the flow chart of FIG. 2 shown in the first embodiment.

FIG. 32 is a detailed flowchart of the principle undetected failure determination in the relevant area of the object undetected failure shown in step 700 of FIG. 32, the processes other than step 720 are the same as those in FIG. That is, in step 720, the circuit obtained in step 701 is converted into a circuit that does not include an uncertain input edge. The uncertain input edge refers to an input edge that cannot be determined as either 0 or 1, and is hereinafter referred to as a U input edge.

FIG. 33 is a detailed flowchart of the circuit conversion for removing the U input edge in step 720 of FIG. Two types of circuit conversion are performed to remove the U input edge. The output destination gate can be set to 0 or 1 regardless of the principle of undetected failure determination and the test pattern generation processing (that is, it is correct even if the principle of undetected failure determination is performed on a circuit in which 0 or 1 is set). Judgment result is obtained,
Even if the test pattern is generated, the correct test pattern can be obtained. ) A circuit conversion A2 is a circuit conversion for removing the U input edge. Further, a circuit conversion for removing these U input edges by synthesizing a circuit in which 0 is set in the U input edge and a circuit in which 1 is set for the U input edge that cannot be removed by the circuit conversion A2 Circuit conversion B
Set to 1. In step 721, it is determined whether or not there is a U input edge in the circuit to be handled.
If not, the process is terminated. (The presence / absence of a U input edge can be checked by examining the presence / absence of a gate in the logic circuit data shown in FIG. 30 such that the gate type 32b is an input edge and the output logical value 33a is an uncertain value. In step 722, it is checked whether or not there is a U input edge for which the circuit conversion A2 has not been executed. If yes, the process branches to step 723, and if not, the process branches to step 724. In step 723, the circuit conversion A2 of the U input edge is performed. In step 724, it is checked whether or not the U input edge exists, and if it exists, the process branches to step 725, and if it does not exist, the processing ends. In step 725, circuit conversion B1 of the U input edge is performed.

FIG. 34 is a detailed flowchart of the circuit conversion A2 shown in step 723 of FIG. In step 723a, it is checked whether or not there is any output gate of the target U input edge that has not been checked yet. If there is any output gate, the process branches to step 723b. In step 723b, one of the output gates of the U input edge which has not been examined is selected. In step 723c, U is applied to the input gate of the output gate selected in step 723b.
It is checked whether or not something other than the input edge exists, and if it exists, the process branches to step 723d, and if it does not exist, the process branches to step 723h. In step 723d, U is applied to the input gate of the output gate selected in step 723b.
Select one other than the input edge. Step 723
In e, it is checked whether the logic value of the input gate selected in step 723d is X and whether the input gate is an unbounded signal line or a leading signal line having no branch, and the condition is satisfied. If the condition is satisfied, the process branches to step 723f, and if the condition is not satisfied, the process branches to step 723c. In step 723f, a logical value is set in the input gate selected in step 723d. Step 723f
In, when the circuit is composed of the NOR gate and the input edge, the logical value is set to 1 and the circuit is set to NA.
When it is composed of an ND gate and an input edge, 0 is set as a logical value. In step 723g, the logical value set in the selected input gate is justified up to the input edge. Here, justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the target signal line. On the other hand, in step 723h, an implication operation is performed based on the logical value set in step 723f. In step 723i, the connection of the signal line whose logical value is set to 0 or 1 is disconnected. At step 723j, the gate whose output is floating is deleted.

FIG. 35 shows a specific example of the circuit conversion A2. In FIG. 35 (a), U1 represents a U input edge, and I1 and G1 represent a NOR gate. In FIG. 35 (a),
By setting the logical value of I1 to 1, the logical value of the output destination gate G1 of U1 can be controlled to 0. Furthermore, since I1 is an unbounded signal line, setting the logic value of I1 to 1 only controls the logic value of G1 to 0 and does not affect other circuit parts. 35 (b), in FIG. 35 (a), the logical value of I1 is set to 1 and a forward implication operation is performed to justify the logical value of I1 up to the input edge (step 723f, step 723g, step 723h). , 0
Alternatively, the connection of the signal line determined to have a value of 1 is cut off (step 723i), and the gate whose output is floating is deleted (step 723j) to represent the obtained circuit. In FIG. 35B, the U input edge U1 has been removed.

In FIG. 35 (c), a circuit conversion A2 cannot be performed U
A specific example of the input edge will be shown. In FIG. 35 (c), U
2 represents the U input edge, I2, G2, and G3 are NO
Represents an R gate. In FIG. 35C, by setting the logical value of I2 to 1, the logical value of the output destination gate G2 of U2 can be controlled to 0. However, if the logical value of I2 is set to 1, the logical value of the NOR gate G3 other than G2 is affected, so that the circuit conversion A2 for U2 is impossible.

FIG. 36 is a detailed flowchart of the circuit conversion B1 shown in step 725 of FIG. In step 725a, it is checked whether or not the U input edge exists, and if it exists, the process branches to step 725b, and if it does not exist, the processing ends. At step 725b, one U input edge is selected. In step 725c, the circuit on the output side as viewed from the target U input edge selected in step 725b is copied. The copy operation is performed as follows.
First, a copy gate is created for each of all the gates that can be traced from the target U input edge selected in step 725b and except for the output gate of the circuit. Further, as described below, the input signal line of each copy gate is connected. An input signal line is connected between the copy gate A ′ of the gate A and all the input gates of A or the copy gates of the input gates. here,
If A's input gate B has a copy gate (ie, B is reachable from the target U input edge), connect a signal line between B's copy gates B'and A ', where B is a copy gate. If (i.e., B is unreachable from the target U input edge), then connect the signal line between B and A '. Finally, a signal line is connected between the copy gate of the input gate connected to the output gate of the circuit and the output gate of the circuit. In step 725d, a logical value 0 is set in the target U input edge UE1 and a logical value 1 is set in the copy gate UE2 of UE1. Here, conversely, the logical value 1 may be set to UE1 and the logical value 0 may be set to UE2. In step 725e, an implication operation is performed. In step 725f, the connection of the signal line whose logical value is set to either 0 or 1 is disconnected. In step 725g, the gate whose output is floating is deleted.

FIG. 37 shows a specific example of the circuit conversion B1. In FIG. 37 (a), U3 represents a U input edge, and R3
1, R2, R3, R4, R5, R6, R7, and R8 represent NOR gates, and O1 represents the output NOR gate of the circuit. U3 is a U input edge for which circuit conversion A2 is not possible. FIG. 37B shows a circuit after copying the output side from U3 in the circuit shown in FIG. In FIG. 37 (b), U3 ′ represents a U input edge obtained by copying U3,
C4, C5, C7, and C8 are R4, R5, and R, respectively.
7 and R8 represent a NOR gate copied (step 725c). FIG. 37 (c) shows U shown in FIG. 37 (b).
3 is set to a logical value of 0 and U3 ′ is set to a logical value of 1 to perform an implication operation, and the signal line having a logical value of 0 or 1 is disconnected,
This is a circuit in which the gate with the output floating is deleted (step 725d, step 725e, step 725f,
Step 725g). In FIG. 37 (c), the target U input edge U3 is removed.

A fourth embodiment will be described in which after the reduction processing, an operation of assigning a logical value to a signal line is tried to determine whether or not there is an input pattern such that the output of the circuit becomes 1.

FIG. 38 is a detailed flowchart of the principle undetected failure determination in the relevant area of the object undetected failure shown in step 700 of FIG. Steps 701b to 705b shown in FIG. 38 correspond to step 7 shown in FIG.
The same as 01 to 705, step 706b is executed in FIG. 38 instead of step 706 in FIG. If the determination process is not completed up to step 705b, then in step 706b, various logic value assignments are made to the circuit that has been subjected to the reduction process 705b.
It is determined whether the target undetected failure is a theoretical undetected failure in the relevant area.

FIG. 39 is a detailed flowchart of the judgment by the logical value allocation trial shown in step 706b of FIG. In step 811a, step 7 in FIG.
The implication operation is performed by setting 1 to the output logical value of the circuit obtained in 04b. During the implication operation, it is checked each time whether the output signal line of each gate that is the target of the implication operation is an unjustified signal line, and if it is an unjustified signal line, the output signal line is registered. Here, the unjustified signal line is an output signal line of the gate whose operation result of the input logical value does not match the output logical value. At step 812a, the unjustified signal lines generated by the implication operation of step 811a are justified up to the head signal line, and if all the unjustified signal lines are justified, then the test pattern of the target undetected failure is present. to decide. On the other hand, if justification is not successful no matter how the logical value is assigned, it is determined that the target undetected fault is a theoretical undetected fault in the relevant area. Here, the justification is to determine the logical value up to the head signal line so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the target signal line.
In step 813a, if it is determined in step 812a that the test pattern exists, the process branches to step 814a, and if not determined, the process ends. In step 814a, the leading signal line whose logical value is set to either 0 or 1 is justified up to the input edge. here,
The justification is to sequentially determine the logical value while tracing to the input edge so that the logical operation result of the gate having the target signal line as the output signal line matches the logical value of the target signal line.

FIG. 40 is a detailed flowchart of justification for the unjustified signal line shown in step 812a of FIG. In step 821a, 0 is set to the contradiction flag. The contradiction flag indicates whether or not a contradiction (a situation in which two values of 0 and 1 are about to be set on the same signal line via different routes during the implication operation) in the implication operation of steps 826a and 830a. The contradiction flag is 0, which means that there is no contradiction, and the contradiction flag is 1, which means that the contradiction has occurred. In step 822a, if the contradiction flag is 0, the process branches to step 823a.
Branch to 8a. In step 823a, if there is an unjustified signal line in the circuit, the process branches to step 824a, and if not, the process branches to step 827a. At step 824a, one is selected from the registered unjustified signal lines. In step 825a, backward tracing is performed using the unjustified signal line selected in step 824a as a starting point. In the backward tracing, the signal line having the logical value X is traced from the signal line which is the starting point toward the input side,
Set a logical value for the signal line at the location where the tracking was terminated. In step 826a, an implication operation is performed based on the logical value set in step 825a. In step 827a, it is determined that there is a test pattern in the relevant area of the target undetected failure. In step 828a, backtracking for resolving the contradiction is performed. In step 829a, if it is determined in step 828a that the target undetected failure is a principle undetected failure, the process ends. If not, the process branches to step 830a. In step 830a, an implication operation is performed based on the logical value of the signal line changed in the process of the back track 828a.

FIG. 41 is a detailed flowchart of the backward tracking shown in step 825a of FIG. Step 8
At 31a, a gate whose output signal line is an unjustified signal line is set as a target gate UIOBJN for backward tracing, and a logical value of the unjustified signal line is set to a target value UIOBJL. In step 832a, if the output signal line of UIOBJN is the head signal line, the process branches to step 834a, and if it is not the head signal line, the process branches to step 833a. Step 833
In a, one gate that is an input gate for UIOBJN and has an output logic value of X is selected, the selected input gate is set as UIOBJN, and UIOBJN is updated. Also, invert the value of UIOBJL (0 → 1, 1 → 0)
By doing so, the value of UIOBJL is updated. At step 834a, the output logical value of UIOBJN is set to UI.
Set the value of OBJL. In step 835a, the UIOBJN I is added to a predetermined stack provided in the processing device 10.
Stack D.

FIG. 42 is a detailed flowchart of the backtrack shown in step 828a of FIG. In step 841a, it is checked whether or not the stack is empty. If the stack is empty, the process branches to step 847a, and if the stack is not empty, the process branches to step 842a. In step 842a,
It is checked whether or not the logic value of the gate corresponding to the ID on the top of the stack has been inverted. If it has been inverted, the process branches to step 843a.
Branch to 6a. In step 843a, the stack 1
The output logical value of the gate corresponding to the ID piled up at the top is X
Return to. In step 844a, an implication operation is performed. In step 845a, the gate is removed from the stack, i.e., the ID stacked on top of the stack is removed.
In step 846a, the I on top of the stack
Invert the output logic value of the gate corresponding to D (0 → 1, 1 →
0) In step 847a, it is determined that the target undetected failure in the relevant area is a principle undetected failure.

FIG. 43 shows a specific example of the determination process by the logical value allocation trial shown in step 706b of FIG.
In FIG. 43, 1r, 2r, 3r, 4r, 5r, 6
r and 7r each represent a NOR gate, 8r represents an input edge, and 9r, 10r, 11r, 12r, 13
Each of r, 14r, and 15r represents a signal line. Figure 4
3 (a) represents a circuit in which an implication operation is performed by setting 1 to the output logical value of the circuit obtained in the reduction processing 705b shown in FIG. 38 (step 811a). Here, since the output logical values of the NOR gates 2r and 3r whose output signal lines are the signal lines 9r and 10r are 1 and the input logical values are all X, the signal lines 9r and 10r are both unjustified. It is a signal line. FIG. 43 (b) is a diagram in which 9r is selected from the unjustified signal lines included in the circuit shown in FIG. 43 (a) to perform backward tracking (steps 824a and 82).
5a). Here, (target gate for rearward tracking, target value) is (2r, 0) → (4r, 1) → (6r, 0) → (8r,
1) is sequentially updated (step 833a). Figure 43
FIG. 7C is a diagram showing a result of performing the implication operation 826a by setting the final target value 1 in the final target gate 8r for backward tracking (step 834a). Here, the gate 8r for which the logical value is set is stacked on the stack (step 835).
a). Here, although the output logical value of the NOR gate 3r is 0, the NOR operation result of the input logical values 0 and 0 is 1, and thus the logical values are inconsistent. FIG. 43 (d) shows FIG.
FIG. 9C is a diagram showing a result of performing backtracking and implication operation on the circuit shown in FIG.
a, step 829a). The logical value of the gate 8r stacked on the top of the stack is inverted from 1 to 0 (step 8
46a), when the implication operation is performed, a contradiction occurs in the NOR gate 2r this time. FIG. 43 (e) is a diagram showing a result of backtracking further performed on the circuit of FIG. 43 (d). Since the gate 8r stacked on the top of the stack has already undergone the logic value inversion, the logic value is returned to X (step 843).
a) Perform an implication operation (step 844a) to search for a target gate for the next backtrack, but determine that the target undetected fault is a theoretical undetected fault in the relevant area because the stack is empty. (Step 847a).

FIG. 44 is a detailed flowchart of another embodiment of the backward tracking shown in step 825a of FIG. Steps 831b, 833b, 83 shown in FIG.
4b and 835b are step 831 shown in FIG.
a, 833a, 834a, and 835a. In the embodiment shown in FIG. 44, the target gate (UIO
BJN) and the target value (UIOBJL) are updated once, and the backward tracking is terminated.

[0091]

According to the present invention, only the necessary circuit area is cut out and the redundancy of the circuit is removed, whereby the principle of undetected failure can be efficiently judged. Moreover, the test pattern can be easily generated by using the result of the principle undetected failure determination.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of a principle undetected failure determination process of a logic circuit according to the present invention.

FIG. 2 is a flowchart of a principle undetected failure determination process and a test pattern generation process of a logic circuit according to the present invention.

FIG. 3 is a detailed flowchart of the examination of the relevant area of each undetected failure shown in step 100 of FIG.

FIG. 4 is a diagram illustrating an example of a related area.

FIG. 5 is a diagram illustrating a conversion example of AND, NAND, OR, and NOR gates.

6 is a detailed flowchart of the principle undetected failure determination of the target undetected failure shown in step 700 of FIG.

FIG. 7 is a diagram illustrating a circuit conversion example for a hypothetical fault.

FIG. 8 is a diagram illustrating a specific example of a process of collecting common logic.

9 is a detailed flowchart of updating the head signal line shown in step 703 of FIG. 6;

FIG. 10 is a diagram illustrating an example of updating a head signal line.

11 is a detailed flowchart of the reduction process shown in step 704 of FIG.

12 is a reduction process A shown in step 734 of FIG.
It is a detailed flowchart of 1.

FIG. 13 is a diagram illustrating an example of reduction processing A1.

14 is a reduction process A shown in step 735 of FIG.
2 is a detailed flowchart of FIG.

FIG. 15 is a diagram illustrating an example of reduction processing A.

16 is a reduction process B shown in step 739 of FIG.
2 is a detailed flowchart of FIG.

FIG. 17 is a diagram illustrating an example of reduction processing B.

FIG. 18 is a detailed flowchart of the reduction of the input edge shown in step 706 of FIG.

FIG. 19 is a detailed flowchart of the input edge reduction (1 step) shown in step 812 of FIG. 18;

FIG. 20 is a diagram illustrating an example of reduction of an input edge.

FIG. 21 is a diagram illustrating an example of standardization of a circuit.

22 is a detailed flowchart of the final determination shown in step 825 of FIG.

23 is a detailed flowchart of generation of the test pattern shown in step 1000 of FIG.

FIG. 24 is a detailed flowchart of editing the determination result shown in step 1100 of FIG.

FIG. 25 shows AND, NAND, O in the second embodiment.
It is a figure showing the example of a conversion of R and a NOR gate.

FIG. 26 is a step 82 in FIG. 18 according to the second embodiment.
6 is a detailed flowchart of the final determination shown in FIG.

FIG. 27 is a diagram illustrating a specific example of an extended implication operation.

FIG. 28 is a diagram illustrating a specific example of unique activation.

FIG. 29 is a configuration diagram of a computer system that implements the present invention.

FIG. 30 is a diagram showing a configuration of circuit data necessary for processing of the present invention.

FIG. 31 is a diagram showing an outline of a third embodiment of the present invention.

FIG. 32 is a detailed flowchart of the principle undetected failure determination of the target undetected failure shown in step 700 in the third embodiment.

FIG. 33 is a detailed flowchart of the circuit conversion for removing an uncertain input edge shown in step 720 of FIG. 32.

34 is a circuit conversion A shown in step 723 of FIG. 33. FIG.
2 is a detailed flowchart of 2.

FIG. 35 is the circuit conversion A shown in step 723 of FIG. 33.
It is a figure showing the specific example of 2.

FIG. 36 is the circuit conversion B shown in step 725 of FIG. 33.
It is a detailed flowchart of 1.

FIG. 37 is the circuit conversion B shown in step 725 of FIG. 33.
It is a figure which shows the specific example of 1.

FIG. 38 is a detailed flowchart of the principle undetected failure determination of the target undetected failure shown in step 700 in the fourth embodiment.

39 is a detailed flowchart of the determination by the logical value allocation trial shown in step 706b of FIG.

40 is a detailed flowchart of justification of an unjustified signal line shown in step 812a of FIG. 39. FIG.

41 is a detailed flowchart of backward tracking shown in step 825a of FIG. 40. FIG.

42 is a detailed flowchart of the backtrack shown in step 828a of FIG. 40. FIG.

FIG. 43 is a diagram showing a specific example of the determination by the logical value allocation trial shown in step 706b.

FIG. 44 is a detailed flowchart of another embodiment of the backward tracking shown in step 825a of FIG. 40.

FIG. 45 is a diagram showing configurations of fault data and test pattern data necessary for the processing of the present invention.

[Explanation of symbols]

1 ... Target combination circuit X and target undetected fault f, 2 ... 1 output circuit Y obtained by converting target combination circuit X regarding target undetected fault f, 3 ... Reduction processing, 4 ... Reduction of top signal line 5, final circuit (1 head signal line 1 output circuit).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location G06F 11/22 360 C 9072-5B (72) Inventor Iku Moriwaki 1 Horiyamashita, Hadano City, Kanagawa Stock Company Nitrate Works Kanagawa Plant (72) Inventor Shun Ishiyama 1 Horiyamashita, Hadano City, Kanagawa Hitachi Ltd. Kanagawa Plant (72) Inventor Takao Nishida 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central In the laboratory

Claims (1)

Claim: What is claimed is: 1. When data representing a logic circuit composed of a division circuit is input from an external storage device and a failure of the logic circuit is diagnosed using a computer, division is performed by flip-flops and input / output edges. A first step of extracting all the ones including the target undetected fault among the divided circuits composed of the combinational circuits obtained by the above, and a second step of converting the divided circuits into an equivalent circuit constituted by only one kind of basic gate And converting the equivalent circuit into a one-output circuit that outputs a true value for an input pattern that detects the undetected failure in the equivalent circuit and outputs a false value for other input patterns. 3 steps, a fourth step of determining whether or not there is an input pattern in which the output of the 1-output circuit is a true value, and the determination result in each division circuit is that the input pattern does not exist. And a fifth step of determining that the test pattern of the undetected fault is a fault that does not exist in the entire circuit. 2. The method according to claim 4, wherein the plurality of gates included in the one output circuit and representing the same logic are combined into one gate, and the first step is obtained. A set of gates in the circuit that can control the output value to either a true value or a false value independently of each other, and a branch point of the signal line exists in the circuit area on the input side of the gate set. The second step of updating the value of the signal line at the boundary between the circuit area reachable from the branch point and the circuit area unreachable from the branch point to the output side from the set of gates by detecting an object. And the second
The third to reduce the redundant logic in the circuit obtained in step 3
Step, a fourth step of converting the circuit obtained in the third step into one head signal line 1 output circuit, and whether or not there is an input pattern in which the output of the one head signal line 1 output circuit becomes a true value And a fifth step of determining a logic circuit. 3. In the fourth step of claim 1, a test pattern is generated from the deterministic logical value information of the input edge having a fixed value for the undetected fault determined to have the input pattern. A principle of undetected failure determination method of a logic circuit characterized by generating. 4. A first step of extracting all one-output division circuits including the undetected fault location in the first step of claim 1, and another one-output division circuit for each one-output division circuit. A circuit, an input edge of the 1-output division circuit, and an output signal line in which either the 0 stuck-at fault or the 1 stuck-at fault has already been detected in the 1-output divided circuit, and
Of the one-output circuits including the undetected fault location, the second step of detecting the circuit having the smallest circuit scale as the relevant region necessary for the principle undetected fault determination, and the effective relation by removing the overlapping related regions. A principle of undetected failure determination method for a logic circuit, comprising a third step of limiting a region. 5. The output logical value of the circuit becomes a true value for an input pattern in which a failure signal is set at the undetected failure location in the third step of the first aspect of the invention, and other inputs For the pattern, the first step of converting the equivalent circuit into a circuit in which the output logical value of the circuit is a false value, a failure signal is set to the undetected failure point, and the output signal is output from the undetected failure point. The output logical value of the circuit becomes a true value for the input pattern that propagates the fault signal to the branch point of the first signal line, and becomes the false value for the other input patterns. A second step of converting the circuit obtained in the first step into a circuit, and a failure signal is set at the undetected failure point, and a failure occurs from the undetected failure point to the output side toward the branch point of the first signal line. Propagate the signal and For the input pattern that propagates the fault signal to the output of the equivalent circuit, the output logical value of the circuit becomes a true value, and for the other input patterns, the output logical value of the circuit becomes a false value. And a third step of converting the circuit obtained in step 1. A principle undetected failure determination method for a logic circuit. 6. The first step of claim 5, wherein the undetected fault has a false value as its value, and
If it is a stuck-at fault, the undetected fault is connected by connecting a basic gate having an undetected fault signal line as an output signal line and a newly provided output basic gate with a 1-input basic gate for inverting the logic value. If the undetected fault has a true value as its value and the stuck-at fault is present, the basic gate having the undetected fault signal line as the output signal line and the newly provided output basic gate are disconnected. Connect a wire between them,
A principle undetected failure determination method of a logic circuit for disconnecting the connection of the undetected failure signal line. 7. In the second step obtained in claim 5, first from the undetected fault location in the circuit obtained in step 5 in claim 5 toward the output side. For each basic gate on the path to the branch point of the signal line, connect the newly provided output basic gate to the output of the basic gate that is an input basic gate for the basic gate and is not on the path, and A principle undetected failure determination method for a logic circuit for disconnecting a connection between a basic gate and all input basic gates to the basic gate. 8. In the third step of claim 5, the undetected failure is not included in the circuit area where the failure signal in the circuit obtained in the second step of claim 5 can propagate. A normal circuit and a fault circuit including the undetected fault are separated, and a two-input exclusive OR composed of a basic gate is newly provided, and the input of the two-input exclusive OR, the normal circuit and the fault circuit are respectively provided. And an output of the two-input exclusive OR, and a one-input basic gate for inverting the logical value between the output of the two-input exclusive OR and the output basic gate newly provided in the second step of the fifth aspect of the invention. A principle of undetected failure detection method for logic circuits that connect wires. 9. In the second step of the second aspect of the invention, a forward implication is set in which a logical value 0 or 1 is set in the head signal line having a branch and the signal values are successively determined toward the input side. By performing the first step of registering the basic gate in which the forward implication is impossible, and controlling the logical value of the leading signal line of the logical value X on the input side of the registered basic gate to 0 or 1. A second step of determining whether the output logical value of the registered basic gate can be independently controlled to 0 or 1, and the output logical value of the registered basic gate can be independently controlled to 0 or 1 in the second step. When it is determined that the logic value is 0 or 1 in the first step, the connection of the signal line is disconnected, and the value of the head signal line is updated from the registered basic gate toward the output side to generate a circuit. Theory with the third step Principle undetected failure determination method for the circuit. 10. A redundant partial circuit on the input side of a multi-input basic gate in the circuit obtained in the second step of claim 2 in the third step of claim 2. For the first signal line for which the first step of simplifying and the first signal line in which any path to the output basic gate included in the circuit obtained in the first step is composed of an even number of basic gates, Forward implication is performed with a logical value as a false value, the connection of the signal line whose logical value is determined to be 0 or 1 is disconnected, and any path to the output basic gate included in the circuit obtained in the first step has an odd number. For a head signal line configured by a basic gate, the logical value of the head signal line is set to a true value to perform a forward implication, and the connection of the signal line whose logical value is set to 0 or 1 is separated. Principle detection of logic circuit with Disability determination method. 11. In the first step of claim 10, a rear implication of setting a true value as a logical value to an input of the multi-input basic gate and successively determining signal values toward an output side. And a second step of registering the basic gate whose backward implication has become impossible, and a second step of removing an unnecessary logic circuit between the multi-input basic gate and the registered basic gate.
Step, and if the logical value of the registered basic gate is a false value, connect a wire between the registered basic gate and the multi-input basic gate, and if the logical value of the registered basic gate is a true value, the registered basic gate And a third step of connecting a wire by interposing a one-input basic gate that inverts a logical value between the multi-input basic gate and the multi-input basic gate. 12. In the fourth step of claim 2, one is selected from the circuits obtained in the third step of claim 2 and included in the selected circuit. The basic gates on the path from the leading signal line to the output basic gate of the selected circuit are set to logical values of all the basic gates other than the output basic gate and the input basic gate for the output basic gate. Of the basic gates in the path leading to the output basic gate of the equivalent circuit, which is the first signal line in the equivalent circuit by converting the 1-input basic gate A second step of removing the first signal line connected to the one-input basic gate that inverts the logical values of all the basic gates other than the input basic gate to the output basic gate. Principle undetected failure determination method for the circuit. 13. The input basic gate for the output basic gate of the equivalent circuit according to the second step of claim 12, wherein an even number of logics are provided between the input basic gate and the head signal line. Let {A1, ..., A be the set of all input basic gates that have one input basic gate whose value is inverted.
m}, and the entire set of input basic gates having a 1-input basic gate for inverting an odd number of logical values is {B1, ...
, Bn}, a new basic gate Cij (1 <
= I <= m, 1 <= j <= n), and connect wires between Cij and all input basic gates connected to Ai,
All input basic gates connected from Bj to Bj are connected by connecting wires between Cij and all input basic gates included in Bj, disconnecting all input basic gates and output basic gates connected from Ai to Ai. And the principle of undetected failure judgment method of logic circuit which separates output basic gate. 14. In the fourth step of claim 1, the uncertain input edge in the output circuit is removed to convert the one output circuit into a one output circuit that does not include the uncertain input edge. In the first step, a second step in which a plurality of gates representing the same logic included in one output circuit obtained in the first step are combined into one gate, and the circuit obtained in the second step is independent of each other. A circuit that can be reached from the branch point by detecting the gate group in which the branch point of the signal line exists on the input side from the gate group in the circuit whose output can be controlled to be a true value or a false value. Included in the circuit obtained in the third step, which is the third step of updating the value of the signal line at the boundary between the area and the circuit area which cannot be reached from the branch point to the output side from the set of the gate. Simplify redundant logic And a fifth step of converting the circuit obtained in the fourth step into one head signal line 1 output circuit, and an input pattern in which the output of the one head signal line 1 output circuit becomes a true value. And a sixth step of determining whether or not to do the principle. 15. In the first step of claim 14, regardless of the result of the principle undetected failure determination, the output value of the output destination is connected to an uncertain input edge which can be set to 0 or 1. The first step of removing the uncertain input edge by setting the output logical value of the output gate, and the circuit when the uncertain input edge for which the logical value cannot be set is input as 0 A method for determining a principle undetected failure of a logic circuit, comprising a second step of removing by combining circuits when 1 and 1 are input. 16. The method according to claim 4, wherein the plurality of gates included in the one output circuit and representing the same logic are combined into one gate, and the fourth step is obtained. In the circuit, a set of gates in the circuit that can set a true value or a false value as an output value independently of each other, and a gate point in which a branch point of the signal line exists in the circuit area on the input side of the gate set A second step of updating the value of the signal line at the boundary between the circuit area reachable from the branch point and the circuit area unreachable from the branch point to the output side from the gate set by detecting the set And a third step for reducing redundant logic included in the circuit obtained in the second step, and the circuit obtained in the third step, in which the logic value assignment of the signal line is tried, Output circuit Principle undetected failure determination method of a logic circuit forces and a fourth step of determining whether there is an input pattern to be a true value. 17. In the fourth step of claim 16, a true value is set to the output logical value of the circuit obtained in the third step of claim 15, and the true value is set toward the input side. A first step of performing an implication operation of successively determining logical values, an unjustified signal line generated in the first step is justified, and when the signal line can be justified, the output of the one output circuit is If it is determined that there is an input pattern that becomes a true value and it cannot be justified by assigning any logical value, then the 1
When it is determined that there is an input pattern in which the output of the output circuit has a true value and there is an input pattern in which the output of the one output circuit has a true value in the second step, And a third step of justifying a leading signal line whose logical value is set to 0 or 1 up to an input edge. 18. In the second step of claim 17, if there is no contradiction in the logical value due to the implication operation, the presence or absence of the unjustified signal line is checked, and if there is no unjustified signal line, the 1 It is determined that there is an input pattern in which the output of the output circuit becomes a true value, and if there is an unvalidated signal line, one unvalidated signal line is selected, and backward tracing and implication operation from the unvalidated signal line are selected. And a second step of performing back-tracking and implication operation when a contradiction of a logical value occurs due to implication operation. 19. In the first step of claim 18, the presence / absence of an unjustified signal line is checked, and if there is no unjustified signal line, an input pattern in which the output of the one output circuit is a true value is obtained. If there is an unjustified signal line, one unjustified signal line is selected, and a gate having the unjustified signal line as an output signal line is set as a backward tracking target gate. An input gate having a logical value of a line as a target value and a backward tracking target gate connected to another backward tracking target gate and having a logical value X until the backward tracking target gate becomes a gate whose output is the first signal line. And the target value is updated to the inversion logic value of the target value repeatedly to set the final target value to the output signal line of the final rear tracking target gate, and the logical undetection of the logic circuit that performs implication operation is detected. Failure determination method. 20. In the second step of claim 18, by the backward tracing of the first step of claim 17, all the signal lines having the logical values are already inverted. If it is, it is determined that there is no input pattern in which the output of the one output circuit becomes a true value, and if the logic value is not inverted, the last one of the signal lines whose logic value has not been inverted. Select a signal line having a logical value set to, return all the logical values of the signal lines having a logical value set after the selected signal line to X, and invert the logical value of the selected signal line, A principle of undetected failure detection method for logic circuit which performs implication. 21. In the first step of claim 18, the presence or absence of an unjustified signal line is checked, and if there is no unjustified signal line, an input pattern in which the output of the one output circuit becomes a true value is obtained. If there is an unjustified signal line, one unjustified signal line is selected, and a gate having the unjustified signal line as an output signal line is set as a backward tracking target gate. The target value is the logical value of the line, the rear tracking target gate is connected to another rear tracking target gate, and the target value is updated to the input gate having the logical value X, and the target value is updated to the inverted logical value of the target value. Then, a theoretical undetected failure judgment method of a logic circuit which sets a target value on an output signal line of a backward tracking target gate and performs an implication operation.