JPH0715406A - Circuit fault detector - Google Patents

Abstract

PURPOSE:To monitor correctly the occurrence of a fault in a data transmission path of a fault discrimination object including a logic circuit and a storage circuit without making signal processing and circuit configuration complicated. CONSTITUTION:A multiplexer circuit 11 multiplexes input data D11, D12...D1n in a predetermined order and a known signal DP from a known signal generating circuit 12, and a demultiplexer circuit 14 the multiplexed resulting data D15 into the known signal DP and output data D11a, D12a...D1na. The known signal DP demultiplexed this time is latched and output data D11a, D12a...D1na received through a data transmission path being a fault discrimination object are discriminated for a code error by comparing the known signal DP with that of a succeeding known signal DP while the time axis is matched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit failure detection device for use in a data transmission device or the like and for detecting a failure in a data transmission path including a logic circuit and a storage circuit.

[0002]

2. Description of the Related Art Conventionally, in a digital data transmission device, a working system in which a failure has occurred is switched to a standby system so that data can be normally transmitted. In this case, the data transmission path including a large-scale logic circuit and storage circuit is constantly monitored to detect the failure.

FIG. 3 is a block diagram showing the configuration of a conventional circuit failure detection device for performing such failure detection. Figure 3
In this circuit failure detection device, the input data D1,
It has a multiplexing circuit 1 for outputting a data signal D4 in which D2 ... Dn and a parity are multiplexed, and a parity counting circuit 2 for counting the parity of the input data D1, D2 ... Dn. Further, the signal processing circuit 3 for outputting the data signal D5 obtained by speed conversion of the data signal D4, and the data signal D5
Of the output data D1a, D2a ... Dna.

Further, this circuit failure detection device has a parity counting circuit 5 for counting the parity of output data D1a, D2a ... Dna, and this circuit failure detection device has output data D1.
a, D2a ... Dna are held this time, and the time axis of the parity count when the output data D1a, D2a ... It has a parity comparison determination circuit 6 for determination.

Further, this circuit failure detection device has a parity separation circuit 7 for outputting a parity count to the parity comparison / determination circuit 6. Further, the timing clock signal C is applied to the multiplexing circuit 1, the separation circuit 4, and the parity separation circuit 7.
1, a control circuit 8 for sending out C2 and output data D1a,
D2a ... Dna is sent, and an alarm 9 is provided to notify the occurrence of a failure in the data transmission path including the logic circuit and storage circuit to be monitored.

Next, the operation of this conventional configuration will be described. FIG. 4 is a diagram showing a data generation process in the monitoring operation of the configuration of FIG. In FIG. 4, in the parity counting circuit 2, the input data D1, D2 ...
Each parity P is counted, and the counting result is multiplexed by the multiplexing circuit 1 together with the input data D1, D2 ... Dn by the timing clock signal C1 from the control circuit 8 or the like and output as the data signal D4. .

The data signal D4 is subjected to speed conversion processing through the signal processing circuit 3, and is input to the separation circuit 4 and the parity separation circuit 7 which are processed by the timing clock signal C2 from the control circuit 8. The separation circuit 4 outputs the data signal D4 as output data D1a, D2a ... Dna.
And sends it to a data transmission path (not shown) for failure determination. Also, from the output data D1a, D2a ... Dna, each output data D1a, D2a ...
Count the parity P of na.

The parity comparison / determination circuit 6 compares the count of the parity P with the count result of the parity P sent next through the multiplexing circuit 1, the signal processing circuit 3, and the parity separation circuit 7, and determines the code error. I do. If they do not match in this comparison, it is determined that some failure has occurred in the circuit through which the output data D1a, D2a ... Dna have passed. In this way, the circuit failure is determined.

As a proposal of such a circuit failure detection device by the parity processing, there is a "circuit failure monitoring method" disclosed in Japanese Patent Application Laid-Open No. 2-61729. In the example of this publication,
The input section multiplexes the monitoring M-sequence signal before or after each time slot of the input main signal and sends the multiplexed signal, and then compares the output section with the code error.

[0010]

However, in the above-mentioned conventional circuit failure detecting device, the parity P of the input data D1, D2 ... Dn of the multiplexing circuit 1 is counted and multiplexed, and further the demultiplexing circuit 4 outputs the parity P. Output data D1a, D2
a ... Dna is compared with the parity P to make a determination, and the occurrence of a fault in the data transmission path subject to the fault determination is monitored.
Therefore, when the multiplex rule is changed, the counting range of the parity P must be changed, which causes a problem that the signal processing and the circuit configuration are complicated. Also in the example of the publication, since the monitoring M-sequence signal is multiplexed with the input main signal, the signal processing and the circuit configuration are complicated.

The present invention has been made in view of the above-mentioned circumstances, and accurately prevents a failure in a data transmission path of a failure determination target including a logic circuit and a storage circuit without complicating the signal processing and the circuit configuration. An object of the present invention is to provide a circuit failure detection device capable of monitoring occurrence.

[0012]

In order to achieve the above object, the circuit failure detection device of the present invention is for determining whether or not data transmission is normally performed on a data transmission path subject to failure determination. A known signal generating means for generating a predetermined known signal; a multiplexing means for selecting the known signal and channels in a plurality of data signal sequences and outputting a multiplexed data signal; Separation means that separates the known signal from multiple data signals and the separated known signal this time are held, and the time axis of the known signal when it is input through the data transmission path of the fault determination target is matched and compared. The configuration is provided with a known signal determination means for determining a code error, and a replacement control means for sequentially switching the multiplexing time slots of the known signal from the known signal generation means at a constant cycle.

In addition to this structure, there is provided a signal processing means for performing at least speed conversion processing on the multiplexed data signal from the multiplexing means.

Further, the known signal judging means is provided with an error displaying means for displaying when a code error is judged.

[0015]

According to the circuit fault detecting apparatus of the present invention having the above-mentioned configuration, the multiplexing time slots of known signals are sequentially replaced at a constant cycle, and the known signal of this time and the data transmission path of the fault judgment target are input. In this case, the time axis of the known signal is matched and compared to determine the code error. Therefore, it is not necessary to change the range of the parity counting by changing the multiplex rule as in the case of fixing the conventional parity, the signal processing and the circuit configuration are not complicated, and the fault determination including the logic circuit and the storage circuit is accurately performed. It becomes possible to monitor the occurrence of a failure in the target data transmission path.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the circuit failure detecting device of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a circuit failure detection device of the present invention. In FIG. 1, this circuit failure detection device includes a multiplexing circuit 11 that outputs multiplexed data D14 that is obtained by multiplexing input data D11, D12 ... D1n and a known signal DP with a timing clock signal C11 and the like. It has a known signal generating circuit 12 for generating a predetermined known signal DP for determining whether or not the data transmission through the data transmission path is normally performed.

Further, this circuit failure detecting device outputs a multiplexed data D15 obtained by speed-converting the multiplexed data D14, and the circuit failure detecting device outputs the multiplexed data D15 from the signal processing circuit 13. Multiplexed data D15
The known signal DP by the timing clock signal C12
And output data D11a, D12a ... D1na,
The separation circuit 14 outputs the separated known signal DP and outputs the output data D11a, D12a ... D1na to a data transmission path (not shown) for failure determination.

Further, this circuit failure detection device receives the known signal DP from the separation circuit 14, holds the current known signal DP, and outputs the output data D11a, D12a ... D.
1na has a known signal determination circuit 15 that aligns and compares the time axes of known signals DP when they are input through a data transmission path (not shown) that is a failure determination target.

Further, when the known signal determination circuit 15 determines that they do not match, that is, the output data D11a and D12.
a ... Alarm 16 for notifying the occurrence of a failure in the data transmission path (not shown) that has sent D1na and is a failure determination target
And a control circuit 17 for sending a timing clock signal C11 for multiplexing processing and a timing clock signal C12 for separation.

Next, the operation of the configuration of this embodiment will be described. FIG. 2 is a diagram showing a data generation process in a monitoring operation using a known signal. In FIG. 2, in the multiplexing circuit 11, the input data D1 in a predetermined order
1, D12 ... D1n and the known signal DP from the known signal generating circuit 12 are multiplexed by the timing clock signal C11 output from the control circuit 17 or the like to generate and output multiplexed data D14. Here, the known signal DP is inserted between the input data D11 and the input data D1n after the input data D12.

The known signal DP is a control signal input to the multiplexing circuit 11 together with the timing clock signal C11 from the multiplexing circuit 11 and is input data D11,
The positions are sequentially switched after D12 ... D1n. That is, in the monitoring operation by the conventional parity counting shown in FIG. 3, the position of the counting result to be multiplexed is fixed to the end of the data, but in the monitoring operation by the known signal DP, the multiplexing time slot of the known signal DP is fixed. Generates the multiplexed data D14 which is sequentially replaced at a constant cycle.

The multiplexed data D14 output from the multiplexing circuit 11 is subjected to processing such as speed conversion in the signal processing circuit 13, and the processed multiplexed data D15 is separated into the separation circuit 1
Output to 4. The separation circuit 14 separates the multiplexed data D15 into the known signal DP and the output data D11a, D12a ... D1na by the timing clock signal C12, outputs the separated known signal DP, and outputs the output data D1.
11a, D12a ... D1na are sent to the data transmission path (not shown) for failure determination.

In the known signal determination circuit 15, the separation circuit 14
The known signal DP from is input and holds the current known signal DP. Then, the held known signal DP and the output data D11a and D12a holding the known signal DP.
... D1na is matched with the next known signal DP when it is input through a data transmission path (not shown) to be subjected to failure determination, and is compared with the time axis to determine a code error.

If the known signal determination circuit 15 does not match, that is, the output data D11a, D12a ... D.
The alarm 16 notifies the occurrence of a failure in the data transmission path (not shown) that has sent 1na and is a failure determination target. In addition, a display is made together with this notification.

In this way, the data channels of the input data D11, D12 ... D1n in the sequential data signal are exchanged with the known signal DP, and the coincidence of the known signal DP through the data transmission path of the fault judgment target is discriminated and coded. An error is determined to determine a failure in the data transmission path subject to failure determination.

[0026]

As described above, according to the circuit failure detection apparatus of the present invention, the multiplexing time slot of the known signal is sequentially replaced at a constant cycle, and the held known signal of this time and the data transmission path of the fault judgment target are held. Since the time axis of the known signal when input through is matched and compared to determine the code error, the signal processing and the circuit configuration are not complicated,
This has the effect that it becomes possible to accurately monitor the occurrence of a failure in the data transmission path of the failure determination target including the logic circuit and the storage circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration in an embodiment of a circuit failure detection device of the present invention.

FIG. 2 is a diagram showing a data generation process in the monitoring operation of the embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional circuit failure detection device.

FIG. 4 is a diagram showing a data generation process in a monitoring operation of a conventional example.

[Explanation of symbols]

 11 Multiplexing circuit 12 Known signal generating circuit 13 Signal processing circuit 14 Separation circuit 15 Known signal determination circuit 16 Alarm 17 Control circuit

Claims (3)

[Claims] 1. A known signal generating means for generating a predetermined known signal for determining whether or not data transmission through a data transmission path subject to failure determination is normally performed, the known signal and a plurality of data. Multiplexing means for selecting a channel in a signal sequence and outputting a multiplexed data signal, multiplexing means for separating a known signal and a plurality of data signals from the multiplexed data signal, and the separating current time From the known signal generating means, the known signal determining means for holding the known signal of, and comparing and comparing the time axes of the known signals when input through the data transmission path of the failure determination to determine the code error, And a switching control means for sequentially switching the multiplexing time slots of the known signal at a constant cycle. 2. A circuit failure detection device comprising, in addition to the structure of claim 1, a signal processing means for performing at least speed conversion processing on a multiplexed data signal from the multiplexing means. 3. A circuit fault detecting apparatus, which is provided with an error display means for displaying when a known signal determination means determines a code error, in addition to the configuration according to claim 1. Description: