JPH06326679A - Method and device for inserting intra-device monitoring signal - Google Patents

Abstract

PURPOSE:To monitor the units of all systems without reducing a data area by deviding the area of intra-device monitoring signals into 1/m, allocating the areas of the monitoring signals divided respectively into 1/m to the intra- device monitoring signals provided in plural (m) pieces of signals and multiplexing and inserting the intra-device monitoring signals. CONSTITUTION:A valid pattern ('1000' for instance) is inserted in the first half of the FTS signal (FTS-1) 1 of the signal -1 and an optional pattern is inserted in a second half. On the other hand, the optional pattern is inserted in the first half of the FTS signal (FTS-2) 2 of the signal -2 and the valid pattern ('1000' for instance) is inserted in the second half. The valid patterns of the first half of the FTS-1 and the second half of the FTS-2 are inserted to the FTS-signal (FTS-3) 3 to be inserted to multiplex signals and the pattern becomes '10001000', When it is approved in a succeeding unit, the states of both systems of the signal 1 and the signal 2 can be approved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-device monitoring signal insertion method and an insertion device for monitoring a defect for each unit constituting a transmission device or for each signal system, and particularly, after multiplexing signals. Also relates to a method and apparatus for inserting an in-apparatus supervisory signal without omission in monitoring.

For example, a transmission device such as a cross-connect device of a high-speed leased line system is involved in online / real-time data transmission, and therefore, a defect may occur in each unit constituting the device or each signal system for maintaining quality of service. It constantly monitors and issues an alarm if a defect is detected. In addition to providing an alarm display for the entire device, it also provides information for immediately determining the failure status (there is a method for a person to make a decision or a method for making an automatic decision), thereby providing for quicker maintenance. .

Therefore, there is a demand for a method for inserting an intra-apparatus supervisory signal that efficiently provides a correct supervisory result and a technique for realizing the inserting apparatus.

[0004]

2. Description of the Related Art In the monitoring method, in a monitored unit, a specific signal pattern (hereinafter abbreviated as FTS signal) in a free time slot of a signal, and FTS-n is used to distinguish FTS signals. ) Is inserted, and when the signal is received, the inserted FTS signal is tested to determine whether the monitored unit is normal or not.

However, when a plurality of signals including the FTS signal are multiplexed into one signal and reach the receiving side unit,
If the same time domain is used for the FTS signals, the FTS signals except one FTS signal disappear at the time of multiplexing, resulting in a unit or system that cannot be monitored.

FIG. 12 is a diagram showing a conventional FTS signal insertion method. FIG. 12 illustrates a case where two signals are multiplexed. Signal-1 and signal-2 have a data area and an FTS signal area in one frame,
Both FTS signal areas have the same phase. In FIG. 12, a thick solid line represents a portion effective for the signal, and a thin solid line represents an invalid portion.

Signal-1 and signal-2 have FTS-1 and FTS-2 as FTS signals, respectively, but the signal after being multiplexed has one of the FTS-3 in the area of FTS-3.
It only has a TS signal. In FIG. 12, FTS-1
Is displayed as being inserted as FTS-3. Therefore, in the multiplexed signal, the signal having FTS-1
Only one system can be tested.

If the FTS signal areas can be provided with different phases for each signal, the above problem can be solved.
This method is not desirable because it reduces the amount of information that can be transmitted.

[0009]

SUMMARY OF THE INVENTION The present invention addresses such a problem and provides an in-apparatus supervisory signal inserting method and an inserting apparatus capable of supervising units of all systems without reducing the data area. With the goal.

[0010]

FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, the case where there are two signal systems is taken up, and only the FTS signal portion is shown. Reference numeral 1 is a signal-1 FTS signal (FTS-1), 2 is a signal-2 FTS signal (FTS-2), and 3 is a multiplexed signal FTS signal (FTS-3). In the example of FIG. 1, F
For TS-1, patterns that are effective in the first half (for example, "100
0 ") is inserted, and an arbitrary pattern is inserted in the latter half. On the other hand, in the FTS-2, an arbitrary pattern is inserted in the first half and a valid pattern (for example," 100 "is inserted in the latter half).
0 ") is inserted.

FIG. 2 is a diagram showing the second principle of the present invention. Also in FIG. 2, an example in which there are two signal systems is taken. Further, (g) is a frame signal, and (h) is a multiplexed signal format. Here, an example is shown in which FTS-1 is inserted into the FTS signal area continuously for two frames and FTS-2 is continuously inserted into the following two frames.

FIG. 3 is a diagram showing the third principle of the present invention. In the principle of FIG. 3, FTS-1 and FTS-2 are calculated bit by bit, and the result is FTS-3. FIG. 3 shows an example of performing an exclusive OR operation on each bit of FTS-1 and FTS-2.

FIG. 4 is a flow chart showing the fourth principle of the present invention. FIG. 4 shows a case where there are two signals, FTS-2 is tested before multiplexing, and if the result is correct, FTS-1 is inserted, and the subsequent unit tests the inserted FTS signal. If the test result of FTS-2 is incorrect, the pattern of the first half of FTS-1 is inserted in the first half, the FTS signal indicating a defect is inserted in the second half, and the inserted FTS signal is tested in the subsequent unit. To do.

[0014]

In FIG. 1, the FTS inserted in the multiplexed signal
-3, an effective pattern of the first half of FTS-1 and the latter half of FTS-2 is inserted, and the pattern is "100010.
00 ". If this is tested by the subsequent unit, the states of both the signal 1 system and the signal 2 system can be tested.

In FIG. 2, since FTS-1 and FTS-2 are inserted in different frames, signal 1 and signal 2
The condition can be monitored for both systems. In FIG. 3, FTS-3 is obtained by operating FTS-1 and FTS-2 bit by bit. If the pattern of FTS-3 is wrong, it can be understood that there is a problem in any system.

In FIG. 4, if the result of the FTS-2 test is correct, it is possible to determine whether the system of signal 1 is normal or not by the test of the inserted FTS signal, and the system of signal 2 is normal. Since it is known to exist, both grids can be monitored. Even if the result of the FTS-2 assay is incorrect, both lines can be monitored as well.

[0017]

FIG. 5 shows an embodiment of the present invention in which two signal systems are used. In FIG. 5, 11 is a selector and 21 is a logical sum circuit for generating a selection signal.

Signal-1 is formed by the data area and the area of FTS-1, and similarly signal-2 is formed by the data area and FT.
It is formed by the region of S-2. These signals-1
And signal-2 are guided to the selector and controlled by the output signal of the logical sum circuit to multiplex the data and the FTS signal.

FIG. 6 is a time chart of the configuration of FIG. In FIG. 6, (a) is a frame signal, (b) is a signal-1, (c) is a signal-2, (d) is a signal-1 data area designation signal, and (e) is a FTS-1 area designation. signal,
(F) is a multiplexed signal.

The data area designating signal (d) is at a high level in a phase corresponding to the data area of the signal 1, and the FTS (e) is
The signal area designation signal is at a high level in an effective area of the FTS signal area of the signal 1. Then, it is assumed that the signal -1 is selected when the selection signal is at the high level (this assumption does not lose generality). At this time,
(F) In the multiplexed signal, the effective data area of signal -1,
Signal-2 valid data area, FTS-1 valid area, F
The effective area of TS-2, the effective data area of signal-1 and the effective data area of signal-2 are sequentially selected by the selector and multiplexed.

Therefore, the subsequent unit can test the first half of the FTS signal to monitor the system status of the signal-1 and the latter half of the FTS signal to monitor the system status of the signal-2.

This system is expanded so that when the number of signals is three or more, the FTS signals are further finely decomposed and multiplexed, and the subsequent units are tested to monitor the status of each signal system. You can

FIG. 7 shows an embodiment of the present invention when there are three signals. In FIG. 7, 11a and 11b are selectors,
21a and 21b are OR circuits. The signal-1 and the signal-2 are input to the selector 11a, and the data area designating signal of the signal-1 and the FTS signal area designating signal of the FTS-1 are input to the OR circuit 21a, and the signal-1 and the signal- 2 is multiplexed. The selector 11b has the signal -3 and the selector 11
Of the signal, and the OR circuit 21b further receives the data area designation signal of signal-3 and the FTS signal area designation signal of FTS-3. Therefore, as described with reference to FIGS. 5 and 6, in the output of the selector 11b, the valid data area of the signal-1, the valid data area of the signal-2, and the valid data area of the signal-3 are included in one frame. , FTS-1
, The effective area of FTS-2, the effective area of FTS-3, the effective data area of signal-1, the effective data area of signal-2, and the effective data area of signal-3 appear in this order, and three signals are multiplexed. Be converted. When the number of signals is 4 or more, the circuit including the selector 11b and the OR circuit 21b may be connected in cascade.

The above method is a method in which the area of the FTS signal is divided into the number of signals and used. Similarly, the FTS signal area is divided and used, but a method of inserting the FTS signal of each signal for each frame without dividing one FTS signal area is also effective.

FIG. 8 shows FTS-1 and FT for every two frames.
It is a figure which shows the 2nd Example of this invention which inserts S-2 by dividing, and illustrates the case where there are two signals. Figure 8
, 11c is a selector, 21c and 21d are logical sum circuits, 22 is a counter, 23 and 23a are decoders, 26
Is an AND circuit. Signal-1 and signal-2 are selectors 1
Input to 1c. The two input signals are multiplexed as follows.

The frame signal is input to the counter and counted. One of the decoders connected to the counter output decodes and outputs "2", and the other decodes and outputs "3". Then, the outputs obtained by decoding "2" and "3" are input to the exclusive OR circuit, the outputs obtained by decoding "3" are returned to the counter, and the counter is synchronously reset. By doing so, the OR circuit 21
The output signal of d is a repetitive signal in which the level corresponding to two frames is high level and the level corresponding to the following two frames is low level. This repetitive signal and FTS-
When the logical product of the area designating signal of 1 is obtained, the same signal as the area designating signal of FTS-1 is obtained at the output of the logical product circuit 26 in the first two frames. Further, the data area designating signal of the signal -1 and the output signal of the logical product circuit 26 are input to the logical sum circuit 21c, and the output signal of the logical sum circuit 21c outputs data of a predetermined phase from the signal -1 and the signal-2, If the FTS signal is selected, FTS-1 and FTS-2 are set every two frames.
Is divided and inserted.

As described above, since the FTS-1 test can be performed in a certain frame and the FTS-2 test can be performed in the other frames, the system states of the signal 1 and the signal 2 can be monitored.

Although the case where the number of signal systems is two has been described here, it can be easily expanded to the case where the number of signal systems is three or more.
Is similar to that of FIG. FIG. 9 is a diagram showing a third embodiment of the present invention.

In FIG. 9, 11d and 11e are selectors, and 27 is an arithmetic circuit. The selector 11d has a signal-
The signal-1 and the signal-2 are selected and output by the control of the data area designation signal which is high level in the valid data area of No.1. The arithmetic circuit calculates the signal-1 and the signal-2 for each bit and outputs the calculation result. The output signal of the selector 11d and the output signal of the arithmetic circuit are input to the selector 11e, and one of the input signals is selected and output according to the signal designating the insertion phase of the FTS signal.

FIG. 10 is a time chart of the configuration of FIG. In FIG. 10, (ri) is a frame signal, and (nu)
Is a signal-1, (l) is a signal-2, (wo) is a data area designation signal of a signal-1, (w) is a signal obtained by multiplexing (n) and (l) with the selector 11d, (f). Is the output signal of the arithmetic circuit, (Y) is the insertion phase designation signal of the FTS signal,
(T) is a signal obtained by multiplexing (W) and (F) by the selector 11e. In the example of FIG. 10, the data of the valid data area of the signal-1 and the data of the other area of the signal-2 are multiplexed and output at the output of the selector 11d. Therefore, FTS
FTS-2 is inserted in the signal area. This signal and the output signal of the arithmetic circuit are input to the selector 11e,
When multiplexed by the insertion phase designation signal (Y), only the FTS signal area is replaced and FTS-3 included in the output signal of the arithmetic circuit is inserted.

In this case, by examining the inserted FTS-3, it can be seen that a defect occurs in either the signal-1 or signal-2 system. In other words, this method cannot identify either, but
If one of the FTS signals is tested before being multiplexed, it can be identified.

Although the case where there are two signals has been described here, it can be easily expanded to the case where there are three or more signals.
Is similar to that of FIG. FIG. 11 is a diagram showing a fourth embodiment of the present invention.

In FIG. 11, 11f and 11g are selectors, 21f is a logical sum circuit, 26b is a logical product circuit, 28 is an FTS-2 verification circuit, and 29 is an abnormal FTS signal generation circuit. The selector 11f and the OR circuit 21f operate in the same manner as the configuration of FIG. In the FTS-2 test circuit, the signal-
The FTS signal of 2 (FTS-2) is verified and a pulse is output when there is an error. Abnormal FTS signal generation circuit is FTS
-1 and FTS-2 output an FTS signal (FTS-3) having a different pattern. The output signal of the selector 11f and the FTS-3 are input to the selector 11g, and one of the input signals is selected and output by the output signal of the AND circuit 26b.

Since the same figure is repeated, the time chart is omitted in FIG. 11, but the operation is as follows. An insertion phase designation signal that designates the latter half phase of FTS-1 is applied to the AND circuit, and the logical product with the output signal of the FTS-2 test circuit is calculated and supplied to the selector 11g. Now, when the FTS-2 verification circuit does not output a detection signal and is at a low level, a low level signal is supplied from the AND circuit, and the selector 11g selects and outputs the output signal of the selector 11f. On the other hand, if the FTS-2 verification circuit outputs an error detection signal and becomes high level, FTS-1
A high level signal is supplied to the selector 11g only in the latter half of the phase, the FTS-3 is selected only in that phase, and the output signal of the selector 11f is selected and output in the other phases.

Therefore, in the subsequent unit, the first half of the FTS signal is verified to monitor the state of the system of the signal -1, and the FTF is checked.
The latter half of the signal can be verified to monitor the state of the signal-2 system. In this embodiment, the case where there are two signal systems has been described as an example, but in the case of n systems, the FTS signal is tested for the system of (n-1) before multiplexing, and after multiplexing based on the result. If the FTS signal indicating the state of the n system is multiplexed and transmitted to the FTS signal of 1, the system of the signal in which the defect occurs in the subsequent unit can be specified. This idea is the same as the principle and the embodiment which have already been described.

[0036]

As described above, the fixed phase is set to FTS.
Even when multiple signals are multiplexed while assigning to signals,
It becomes possible to realize an insertion method and an insertion device of an in-device monitoring signal that can specify a signal system in which a defect has occurred.

[Brief description of drawings]

FIG. 1 is a principle of the present invention.

FIG. 2 is the second principle of the present invention.

FIG. 3 is a third principle of the present invention.

FIG. 4 is a fourth principle of the present invention.

FIG. 5 is an embodiment of the present invention.

FIG. 6 is a time chart of the configuration of FIG.

FIG. 7 is an embodiment of the present invention when there are three signals.

FIG. 8 is a second embodiment of the present invention.

FIG. 9 is a third embodiment of the present invention.

10 is a time chart of the configuration of FIG.

FIG. 11 is a fourth embodiment of the present invention.

FIG. 12 is a conventional FTS signal insertion method.

[Explanation of symbols]

 1 FTS-1 2 FTS-2 3 FTS-3

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigetsuke Samukawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (7)

[Claims] 1. A method of inserting an intra-apparatus supervisory signal when multiplexing a plurality of m signals having an intra-apparatus supervisory signal in the same time domain, wherein the intra-apparatus supervisory signal area is divided into 1 / m. Then, a 1 / m-divided area of the supervisory signal is allocated to each intra-apparatus supervisory signal of a plurality of m signals (1, 2), and the intra-apparatus supervisory signal is multiplexed and inserted (3). A method for inserting a supervisory signal in a device characterized by the above. 2. A method of inserting an intra-apparatus supervisory signal when multiplexing a plurality of m signals having an intra-apparatus supervisory signal in the same time domain, wherein different signals are assigned to different areas of the intra-apparatus supervisory signal in different frames. A method for inserting an in-device supervisory signal, characterized by allocating to the in-device supervisory signal. 3. A method for inserting an intra-apparatus supervisory signal when multiplexing a plurality of m signals having intra-apparatus supervisory signals in the same time domain, in an intra-apparatus supervisory signal included in each signal, obtained by arithmetic processing. The inserted signal is inserted as an in-device monitoring signal of a multiplexed signal. 4. A method of inserting an intra-apparatus supervisory signal in multiplexing a plurality of m signals having the intra-apparatus supervisory signal in the same time domain, wherein the intra-apparatus supervisory signal area is divided into 1 / m. Then, a 1 / m-divided area of the supervisory signal is assigned to each in-apparatus supervisory signal of a plurality of m signals, and the in-apparatus supervisory signal of any one signal is assigned to the one signal. Inserted into the 1 / m divided area, and the in-apparatus supervisory signal of the other (m-1) signal is subjected to correctness test before being multiplexed, and for the signal in which an error is found, , 1 / assigned to the signal in which the error was found
A method for inserting an intra-apparatus supervisory signal, wherein a pattern different from a normal intra-apparatus supervisory signal is inserted into an area divided into m. 5. A device for inserting an in-device supervisory signal according to the method for inserting an in-device supervisory signal according to claim 1, wherein the r-th signal and the s-th signal are input to a selector, and the r-th signal is validated. A signal designating a data area and a signal designating an area of the in-device monitoring signal assigned to the r-th signal are input to a logical sum circuit, and the logical sum signal of the signals designating the two areas is used to Is provided with a first insertion circuit for selecting and outputting a signal input to the selector, and the output signal of the first insertion circuit and the t-th signal are input to the second selector to output the t-th signal. A signal for designating the valid data area and a signal for designating the area of the in-device monitoring signal assigned to the t-th signal are input to the second logical sum circuit, and the logical sum signal of the signals for designating the two areas. Received by the second selector by A second insertion circuit for selecting and outputting the provided since the insertion device of the second formed by the insertion circuit is connected to a cascade device monitoring signal. 6. A device for inserting an in-device supervisory signal according to the method for inserting an in-device supervisory signal according to claim 2, wherein the r-th signal and the s-th signal are input to a first selector to output a frame signal. A signal obtained as a result of counting the frame signals by inputting to the selection signal generator, a logical operation signal of a signal designating an effective area of the in-apparatus monitoring signal of the r-th signal, and an effective data area of the r-th signal A first insertion circuit that selects and outputs the signal input to the first selector according to the logical sum signal of the signals designating the second selector, and outputs the output signal of the first selector and the t-th signal to the second Input to the selector, the frame signal is input to the selection signal generator, the signal obtained as a result of counting the frame signal and the logical operation signal of the signal designating the area of the in-device monitoring signal assigned to the t-th signal , The above A second insertion circuit that selects and outputs the signal input to the second selector by the logical sum signal of the signals that specify the effective data areas of the second signals is provided.After that, the second insertion circuits are cascaded. Insertion device for monitoring signal inside the device. 7. An in-device supervisory signal inserting device according to the in-device supervisory signal inserting method according to claim 4, wherein the r-th signal and the s-th signal are input to a first selector, and The signal input to the selector is selected and output by the logical sum signal of the signal designating the effective data area of the signal and the signal designating the area of the in-device monitoring signal assigned to the r-th signal. Of the s-th signal, the output signal of the signal generation circuit of the signal indicating the abnormality is provided to the second selector. The in-apparatus monitoring signal is verified by the verification circuit, and the second signal is obtained by the logical product signal of the signal output by the verification circuit when the verification result is incorrect and the designated signal in the area of the in-apparatus monitoring signal assigned to the sth signal. Select the input signal of the selector A first insertion circuit for outputting is provided, the output signal of the first insertion circuit and the t-th signal are input to the third selector, and a signal specifying the effective data area of the t-th signal and a t-th signal are input. The signal input to the third selector is selected and output by the logical sum signal of the signals that specify the area of the in-device monitoring signal assigned to the signal, and the signal is input to the fourth selector. The signal output from the second generation circuit of the signal indicating abnormality is connected to the fourth selector, the in-device monitoring signal of the t-th signal is tested by the test circuit, and the signal output by the test circuit when the test result is incorrect. And a specified signal in the area of the in-apparatus supervisory signal assigned to the t-th signal is input to the fourth selection signal generation circuit to take a logical product,
An in-device supervisory signal insertion device in which a second insertion circuit that selects and outputs the input signal of the fourth selector according to the AND signal is provided, and thereafter the second insertion circuit is connected in cascade.