JPS6036667B2 - Synchronous arithmetic circuit diagnostic device - Google Patents

Description

[Detailed Description of the Invention] This invention constantly and automatically checks the normality of the operation of a synchronization calculation circuit for obtaining frame synchronization of each channel in a time division multiplex communication system, and automatically detects the occurrence of a failure. The present invention relates to a diagnostic device.

For diagnosis of the synchronous calculation circuit that multiplexes the synchronous calculations for each channel after multiplexing multiple channels, if the synchronization error continues for more than 1 second, or if the control information sent to the opposing transmission system equipment. If the response information is not received normally, it is determined that there is a failure in the synchronizer including the synchronization calculation circuit, and the maintenance personnel can manually switch the synchronizer or
Alternatively, a system has been adopted in which the system automatically switches after determining the above-mentioned failure.

Therefore, if a failure mode occurs in which the synchronizer causes a fixed failure and simulates a state in which synchronization is always established, there is no way to detect this, and in this case, the The only method available was to determine the failure of the synchronization device based on a failure report from a person.

Conventionally, there was no built-in hardware to constantly check for failures in the synchronizer, which caused problems in terms of maintainability. An object of the present invention is to automatically detect when a fixed failure occurs in the synchronizer as described above, easily derive switching conditions for the synchronizer, and improve maintainability.

According to the present invention, when a synchronization calculation circuit commonly used to establish synchronization of each channel frame of a time division multiplex line performs synchronization calculation processing on various frame patterns, normal and abnormal, at frame bit positions in a specific channel. Memorize the correct answer data in advance, and compare the calculation result when the above frame pattern is supplied to the synchronous calculation circuit with the memory contents of the above-mentioned memory for that frame pattern to check the quality of the synchronous calculation circuit. To check.

FIG. 1 shows an embodiment of the present invention, in which a channel-compatible synchronization memory 1 stores synchronization states for each channel in units of basic transport speed, for example, 6 b/s.

The F-bit storage unit 2 of this channel-compatible synchronization memo IJI stores the F-bit for frame synchronization through the terminal 3 from the transmission path and the F-bit read from the diagnostic memory 4 provided in the synchronizer. , is selected by the selector 5 and written. When the selector 5 is supplied with a signal indicating the timing of a specific channel, for example, the 24th channel, through the terminal 6, the F bit from the memory 4 is selected. The channel-compatible synchronous memory is accessed by an address counter 7 that increments in synchronization with each channel of the time division multiplexed signal on the transmission path, and can be read and written for each channel. In the diagnostic memory 4, various normal and abnormal frame synchronization patterns are stored in area F, and data indicating the correct result when performing synchronization calculations on each of these patterns, such as the synchronization state, the detection state of the synchronization pattern on the transmission path, and the backward The protection count value and the forward protection count value are stored in areas F80, FOK, OCT, and NGCT, respectively. As this diagnostic memory 4, a read-only memory can be used. Memory 4 is accessed by address counter 8. Each time the channel-compatible synchronous memory 1 is read, each data is supplied to the synchronous calculation circuit 9, which predicts and calculates the next F bit from the F bits stored for that channel, and inputs it from the selector 5. The backward protection count value GCT and the forward protection count value NGCT are set to 1 depending on whether or not they match with the F bit.
It increments, clears, and further sets data FS○ indicating the synchronization state and data FOK indicating the detection state of the synchronization pattern with the transmission line, and writes them into the corresponding channel word of the channel corresponding synchronization memory.

In the matching circuit 10, when a specific channel is selected by the selector 5, the calculation result of the synchronous calculation circuit 9 and the diagnostic memory 4 are stored.
The matching result is compared with the correct calculation result for the period pattern read out from the current period pattern, and the matching result is displayed on the display unit 11. The operation of the above circuit will be explained below.

As for the data on the multiplex transmission path, for example, as shown in Figure 2, assuming that 4Kb/s line data is multiplexed for 24 channels and treated as 1.544Mb/s line data, the synchronization pattern is - The F-channel provided within each channel is
Bits shall be used.

Any pattern can be considered as the F bit pattern to be used, but for example,
．． The following description uses a 50 F bit pattern. Figure 3 shows X. 50 F bit patterns are shown.
In this case, for example, of the 24 channels of a 64Kb/s line, the 24th channel is used for diagnosis within the station, and the synchronization pattern on the transmission path is not captured in the 24th channel, but is stored in the diagnostic memory. Assume that the F bit pattern stored in 4 is used. In the synchronous fishing circuit 9, for example, a competitive counting method is used for forward protection as a synchronous protection method. X. When using 50 frame patterns, one frame is composed of 20 bits, but due to the special nature of this pattern, when any consecutive 5 bits are extracted, the value of the following F bit can be predicted. Therefore, if the synchronous noise circuit 9 is operating normally, 5 consecutive bits of F
The bit pattern is determined, and the synchronization state at that time, FS
O is 1 when out of sync, 0 when in sync,
When all F-bit pattern matching is performed normally, that is, when synchronization patterns on the transmission path are always detected normally, FOK is 0, otherwise it is 1, and the F-bit pattern matching results do not match. If the number of times that the forward protection count value NOCT matches, the number of times that the F bit pattern matching results match, that is, the value of the backward protection count value GCT, are determined, and the next F bit is specified in advance. , the next synchronization state is also uniquely determined. This synchronization state is stored in advance in the diagnostic memory 4,
A verification circuit 10 determines whether the content actually matches the result of synchronous computation in the synchronous noise circuit 9;
The determination result is displayed by the failure display section 11. FIG. 4 shows a synchronization state transition diagram when the contention counting method is used as the synchronization protection method.

In the figure, the synchronization pattern mismatch value NOCT becomes n and the state shifts to an out-of-synchronization state, and the synchronization pattern match value GCT becomes m.
,,m2, respectively, and these n, m・,m
2 are respectively 4, 5, and 3, and the pattern shown in FIG. 5 is given as the F bit pattern. FS○, FOK, GCT, NGC
The transition process of the value of T is shown in the corresponding column of FIG. 5, respectively. The normality of the synchronous monkey miscellaneous circuit 9 in FIG. 1 is shown in FIG. 5 when, for example, the F bit pattern inserted in the 24th channel is determined as the value shown in the corresponding column in FIG. This can be confirmed by checking whether an output is calculated that exactly matches the values of FOS, FOK, GCT, and NGCT.

The synchronous processing circuit 9 is used multiplexed for calculating the synchronizing F bit pattern on each 64 Kb/s transmission path, and is
The F bit pattern inserted in the hth position does not disturb the synchronization of other channels.

In addition, in this invention, a configuration is adopted in which the synchronization F bit pattern is distributed in each channel, but the synchronization pattern is concentrated in a specific channel, and the synchronization method is a concentrated pattern. The present invention can be easily applied even when a detection method is used. As explained above, with the method of this invention, it is possible to constantly check the normality of the operation of the synchronous arithmetic circuit, which was conventionally configured with a large number of logic ICs, and it is possible to promptly notify maintenance personnel in the event of a failure. Become.

Therefore, latent failures in the synchronizer can be detected early.
Maintainability can be greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an example of the synchronous arithmetic circuit diagnostic method of the present invention, FIG. 2 is a multiplexing configuration diagram within a 1.544 Mb/s line, and FIG. FIG. 4 is a diagram showing a 50-frame pattern, FIG. 4 is a synchronization state transition diagram, and FIG. 5 is a diagram showing an example of data stored in the diagnostic memory. 1...Channel compatible synchronous memory, 4...
・Diagnostic memory, 5... Selector, 7... First address counter, 8... Second address counter, 9... Synchronous miscellaneous circuit, 10... Verification circuit, 11...・
Fault indication circuit. Our 2nd picture group? Figure 3 History Figure 4 Figure 5

Claims (1)

[Claims] 1. A channel-compatible synchronous memory in which frame patterns and synchronization calculation processing results are stored for each channel; and a channel-compatible synchronous memory that increments an address in synchronization with each channel of the time division multiplexed signal on the transmission path, and uses the address to A first address counter that accesses and reads the frame pattern, and then writes the synchronous operation processing result, and the data read from the channel-compatible synchronous memory are supplied, performs synchronous operation processing on the frame pattern, and writes the synchronous operation processing result to the above channel. A synchronous calculation circuit that supplies the corresponding synchronous memory, a diagnostic memory that stores various normal and abnormal frame patterns, and correct data obtained when the frame patterns are subjected to synchronous calculation processing, and a time division multiplexer on the above transmission path. A second address counter increments the address for each specific channel of the signal and uses the address to access and read out the diagnostic memory, and normally selects the frame bit of each channel of the time division multiplexed signal on the transmission path. , the specific channel has a selector that selects a specific bit of the frame pattern read from the diagnostic memory and supplies it to the synchronous memory corresponding to each channel for writing; A synchronous arithmetic circuit diagnostic device comprising a collation circuit that compares a result of synchronous arithmetic processing with a readout output from the diagnostic memory.