JPH0715334A - Parallel a/d converter and serial parallel a/d converter - Google Patents

Abstract

PURPOSE:To obtain an A/D converter from which a smooth nonlinear conversion characteristic is obtained with a simple configuration without addition of any special components. CONSTITUTION:The parallel A/D converter is made of a reference voltage generating circuit 11, a comparator circuit 12, a logic circuit 13 and an encoder 14. They are connected in cascade, and the resistance of resistors R1-R16 being components of the reference voltage generating circuit 11 is made different from each other and the resistance is selected in matching with a desired nonlinear conversion characteristic.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD converter having a non-linear conversion characteristic, and in particular, a parallel AD converter having a structure in which a reference voltage having a different voltage value and an analog input voltage are collectively compared and the voltage thereof. The present invention relates to a serial-parallel AD converter having a configuration in which comparison is divided into a plurality of stages.

[0002]

2. Description of the Related Art As an AD converter used when digitizing an analog video signal, a parallel AD converter having a structure in which a reference voltage having a different voltage value and an analog input voltage are collectively compared is used. . By the way, when a signal of a television camera is handled, gamma correction is added in order to obtain an output voltage proportional to a square root of an input voltage. Therefore, an AD converter having a non-linear conversion characteristic is used.

Conventionally, as an AD converter having this non-linear conversion characteristic, the one disclosed in JP-A-61-95621 is known. The circuit configuration is shown in FIG.
In FIG. 6, an analog input voltage is applied from the signal source 62 to one input end of each of the plurality of comparators COP of the comparison unit 61, while the same input end is applied to each of the other input ends of the plurality of comparators COP. A reference voltage obtained at each connection point of a resistor string 63 composed of a plurality of resistors R having a resistance value and connected in cascade is applied as a comparison voltage.
One end of each of the plurality of current sources I of the current source unit 64 is connected to each connection point of the resistor string 63. The other ends of the plurality of current sources I are grounded.

In the comparison section 61, each comparator COP compares the analog input voltage with the comparison voltage, so that the comparison outputs of the comparators higher than a certain comparator are all logic "1", and the comparators lower All are in the state of logical "0". The plurality of comparison outputs of the comparison unit 61 are supplied to the exclusive OR circuit 65, and the mismatch between the adjacent comparison outputs is detected. The logical output of the exclusive OR circuit 65 is encoded by the encoder 66 and output as a digital signal.

[0005]

In the conventional parallel type AD converter having the above-mentioned structure, a plurality of current sources I are connected to each connection point of the resistor string 63. Although a smooth non-linear conversion characteristic can be obtained by the above, since it is necessary to provide the current source I for each connection point, the circuit configuration becomes complicated, and in order to cancel the temperature characteristic, the current source I must be There was a problem that control was necessary. The present invention has been made in view of the above problems, and an object of the present invention is to provide a parallel configuration capable of obtaining a smooth nonlinear conversion characteristic with a simple configuration without adding a special component. A type AD converter and a serial-parallel type AD converter are provided.

[0006]

A parallel type A according to claim 1
The D converter includes a plurality of resistors each having a different resistance value and connected in cascade, and a reference voltage generation circuit that generates a plurality of reference voltages having different voltage values at each connection point,
A plurality of comparators to which an analog input signal is commonly applied to one input end and the plurality of reference voltages are applied to the other input end; and a logic circuit having the comparison outputs of the plurality of comparators as inputs. , And an encoder for encoding the output of this logic circuit.

A serial-parallel AD converter according to a second aspect of the present invention comprises a plurality of resistors each having a different resistance value and connected in series, and generates a plurality of reference voltages having different voltage values at each connection point. And a reference voltage generating circuit for first comparison in which an analog input signal is commonly applied to one input terminal and a reference voltage generated at a predetermined number of connection points in the plurality of resistors is applied to the other input terminal. Group, a logic circuit which inputs each comparison output of the first comparator group, an analog input signal is commonly applied to one input terminal, and the above predetermined number of connection points are connected to the other input terminal. A second comparator group to which the reference voltage generated at each connection point is applied according to the output of the logic circuit, and an encoder for encoding the output of the logic circuit and each comparison output of the second comparator group. It has a built-in configuration.

[0008]

A parallel type AD converter according to claim 1 or claim 2
In the serial-parallel AD converter described above, the resistance values of a plurality of resistors that are connected in cascade and generate reference voltages having different voltage values are different from each other. Then, if these resistance values are set in accordance with the desired non-linear conversion characteristic, a smooth non-linear conversion characteristic can be obtained. Further, the temperature characteristics are almost eliminated by using the resistors having the same temperature characteristics as the plurality of resistances.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention and shows a case where the present invention is applied to, for example, a 4-bit parallel AD converter. In FIG. 1, 16 connected in cascade
The reference voltage generating circuit 11 is composed of the resistors R1 to R16. The reference voltage Vref _B on the bottom side is applied to the open end of the lowermost resistor R1, and the uppermost resistor R1 is applied.
A reference voltage Vref _T on the top side is applied to the open end of 6.

In the reference voltage generating circuit 11, the resistance values of the resistors R1 to R16 are made different by the diffusion resistance, the polysilicon resistance, etc. in accordance with the desired nonlinear conversion characteristic. Thereby, the resistors R1 to R
At each of the 16 connection points, different reference voltages corresponding to the above non-linear conversion characteristics are obtained. Each reference voltage generated from the reference voltage generation circuit 11 is applied as a comparison voltage to each inverting (-) input terminal of the 15 comparators C1 to C15 of the comparison circuit 12. 15 comparators C1 to C
Reference numeral 15 collectively compares the analog input voltage Vin applied to each non-inverting (+) input terminal with each comparison voltage.

In the comparison circuit 12, the comparators C1 to C1 are connected.
C15 compares the analog input voltage Vin with each comparison voltage, so that the comparison outputs of the comparators higher than a certain comparator are all logic "0", and the lower comparators are all logic "1".
It will be in the state. The respective comparison outputs of the comparators C1 to C15 are supplied to the logic circuit 13. The logic circuit 13 receives two adjacent comparison outputs as two inputs, and generates a logic "1" output when the lower comparison output is a logical "1" and the upper comparison output is a logical "0". 14 gates A1 to A
14 and a gate A1 that receives only the highest comparison output
It is composed of 5 and.

Each logic output of the logic circuit 13 is an encoder 1.
4 is supplied. The encoder 14 encodes the output of the logic "1" from the logic circuit 13 and outputs it as 4-bit digital signals D0 to D3. As described above, in the parallel AD converter, the resistance values of the resistors R1 to R16 that are connected in cascade and configure the reference voltage generation circuit 11 are made different, and these resistance values are adjusted to a desired nonlinear conversion characteristic. By setting, a smooth non-linear conversion characteristic can be obtained with a simple configuration without adding a special component such as a current source. Further, the resistors R1 to R1
By using a resistor having the same temperature characteristic as R16, the temperature characteristic almost disappears.

FIG. 2 is a circuit diagram showing another embodiment of the present invention, showing a case where it is applied to, for example, a 4-bit serial-parallel AD converter. In FIG. 2, as in the case of the parallel AD converter, 16 resistors R1 to R1 connected in cascade are connected to each other.
The reference voltage generation circuit 21 is configured by R16. The bottom side reference voltage Vref _B is applied to the open end of the lowest resistance R1, and the top reference voltage Vref _T is applied to the open end of the highest resistance R16. In the reference voltage generating circuit 21, the resistance values of the resistors R1 to R16 are defined by diffusion resistors and polysilicon resistors.
It is created differently according to the desired nonlinear conversion characteristic. As a result, different reference voltages corresponding to the non-linear conversion characteristics are obtained at the connection points of the resistors R1 to R16.

The comparison circuit 22 includes three comparators HC1 to HC3 for upper bits which perform AD conversion of upper bits and three comparators LC1 to LC for lower bits which perform AD conversion of lower bits.
3 and 3. In this comparison circuit 22,
The analog input voltage Vin is commonly applied to the non-inverting (+) input terminals of the comparators HC1 to HC3 and the comparators LC1 to LC3. Each inverting comparator HC1~HC3 (-) input terminal, the reference voltage V ₄ generated every four connection points of the resistor string in the reference voltage generating circuit 21,
V _8, V ₁₂ is applied as the reference voltage. As a result, the analog input voltage Vin is 0 to V ₄ , V ₄ to
V _8, V ₈ ~V _12, can determine V ₁₂ has entered any range or more.

The respective comparison outputs of the comparators HC1 to HC3 are supplied to the logic circuit 23. This logic circuit 23 is adjacent to the gate HA1 that receives only the lowest comparison output and is adjacent to the gate HA1.
Two gates HA2 and HA3, each of which has two comparison outputs and outputs a logic "1" when the comparison output on the lower side is a logic "1" and the comparison output on the higher side is a logic "0".
And a gate HA4 that receives only the highest comparison output as an input. On the other hand, in order to perform the AD conversion of the lower bit, the block selection of the resistor string in the reference voltage generation circuit 21 is performed according to the result of the upper bit. That is, if the analog input voltage Vin is in the range of 0 to V ₄ , the switch group S 1 to S 3 is selected by the output C 1 of the gate HA 1 of the logic circuit 23, and each inversion of the lower comparators LC 1 to LC 3 (− ) Comparison voltage V ₁ ~
Give V ₃ .

Similarly, the analog input voltage Vin is V
₄ in the case of the range of ~V _8, the output C2 Select switches S4~S6 by comparing the voltage V ₅ ~ gate HA2
When V ₇ is supplied to the comparators LC3 to LC1 and the analog input voltage Vin is in the range of V _{8 to} V ₁₂ , the switch group S7 to S9 is selected by the output C3 of the gate HA3 and the comparison voltages V _{9 to} V ₁₁ are selected. To the comparators LC1 to LC3, and when the analog input voltage Vin is V ₁₂ or more, the gate HA4
Gives the comparison voltage V ₁₃ ~V ₁₅ Select switches S10~S12 the output C4 of the comparator LC3～LC1. The four outputs C1 to C4 of the logic circuit 23 are supplied to the 2-bit encoder 24a, and the low-order comparators LC1 to LC3 are supplied.
Each comparison output of is supplied to the 2-bit encoder 24b. The encoders 24a and 24b code these outputs and output them as 4-bit digital signals D0 to D3 via the output buffer 25.

As described above, in the serial-parallel AD converter, the resistance values of the resistors R1 to R16, which are connected in cascade and form the reference voltage generating circuit 11, are made different from each other, and these resistance values are converted into a desired non-linear conversion. By setting according to the characteristics, similar to the case of the parallel type AD converter, it is possible to obtain smooth non-linear conversion characteristics with a simple configuration without adding special constituent elements such as a current source. You can Further, the temperature characteristics are almost eliminated by using the resistors having the same temperature characteristics as the resistors R1 to R16.

In the case of the serial-parallel type AD converter, as shown in FIG. 3, the upper 2-bit AD conversion system 31 described above is used.
Further, a sample hold circuit 33 for keeping the analog input voltage Vin constant during the AD conversion period is provided in front of the lower 2-bit AD conversion system 32. Further, in the present embodiment, when the parallel comparison configuration is applied to a combination of two stages of upper side and lower side and the comparison with the analog input voltage Vin is applied in two stages, it is applied to a serial-parallel AD converter. However, the present invention can be similarly applied to a serial-parallel AD converter having a configuration in which three or more stages of parallel comparison configurations are combined and the comparison with the analog input voltage Vin is performed in three or more stages.

By the way, in the case of a bipolar AD converter,
Since there is a base input current of the differential transistor pair that constitutes each comparator, the resistor R that constitutes the reference voltage generation circuit 11
It is necessary to reduce the impedance of 1 to R16. Therefore, when forming the resistors R1 to R16, in practice, aluminum wiring is used instead of diffusion resistors or polysilicon resistors. In that case, as shown in FIG. 4, each resistance is created by changing the length and width of a film (such as aluminum) having a uniform sheet resistance. Further, as shown in FIGS. 5A and 5B, the films (aluminum or the like) having a uniform sheet resistance have the same width, and the respective resistances can be created by changing only the length.
According to this, it is possible to further reduce the influence of variations in etching in the semiconductor process.

[0020]

As described above, according to the present invention,
In a parallel AD converter or a serial-parallel AD converter, the resistance values of a plurality of resistors that are connected in cascade and generate reference voltages having different voltage values are different from each other, and these resistance values have desired nonlinear conversion characteristics. Since it is set according to the above, it is possible to obtain a smooth non-linear conversion characteristic with a simple structure without adding a special constituent element such as a current source.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention applied to a 4-bit parallel AD converter.

FIG. 2 is a circuit diagram showing another embodiment of the present invention applied to a 4-bit serial-parallel AD converter.

FIG. 3 is a block diagram showing an overall configuration of a 4-bit serial-parallel AD converter.

FIG. 4 is a first diagram showing an example of forming a plurality of resistors.

FIG. 5 is a diagram (No. 2) showing an example of forming a plurality of resistors.

FIG. 6 is a circuit diagram showing a conventional example of a parallel AD converter.

[Explanation of symbols]

 11, 21 Reference voltage generation circuit 12, 22 Comparison circuit 13, 23 Logic circuit 14 Encoder 24a, 24b 2-bit encoder C1 to C15 Comparator HC1 to HC3 Higher comparator LC1 to LC3 Lower comparator

Claims (3)

[Claims] 1. A reference voltage generating circuit having a plurality of resistors each having a different resistance value and cascaded to each other, and generating at each connection point a plurality of reference voltages having different voltage values, and one input terminal. A plurality of comparators to which an analog input signal is commonly applied and the plurality of reference voltages are applied to the other input terminal; a logic circuit that inputs each comparison output of the plurality of comparators; and the logic circuit And an encoder for encoding the output of the parallel AD converter. 2. A reference voltage generating circuit which comprises a plurality of resistors each having a different resistance value and which are connected in cascade, and which generates a plurality of reference voltages of different voltage values at each connection point, and one input terminal. A first comparator group to which an analog input signal is commonly applied, and a reference voltage generated at a predetermined number of connection points of the plurality of resistors is applied to the other input terminal, and the first comparator group. A logic circuit having each comparison output as an input, and the analog input signal is commonly applied to one input end and the other input end is connected to each connection point between the predetermined number of connection points in the plurality of resistors. A second comparator group to which the generated reference voltage is applied according to the output of the logic circuit; and an encoder for encoding the output of the logic circuit and each comparison output of the second comparator group. Series-parallel type characterized by D converter. 3. The parallel AD converter according to claim 1 or the serial-parallel AD converter according to claim 2, wherein the plurality of resistors are formed by changing a length of a film having a uniform sheet resistance. A parallel AD converter or a serial-parallel AD converter characterized in that