JPH07152630A - Digital signal processor - Google Patents

Abstract

PURPOSE:To provide the digital signal processor which can refresh an instruction RAM with simple constitution and improve the reliability of the instruction RAM. CONSTITUTION:The digital signal processor consists of a 1st selector 21 which distributes the output of a ROM 11 in two directions, 1st and 2nd instruction RAMs 22 and 23 where program instructions from the ROM 11 are written through the 1st selector 21 and also read out, a 2nd selector 24 which receives the outputs of those 1st and 2nd instruction RAMs 22 and 23 and selects one of them, an instruction execution part 3 which receives the output of the 2nd selector 24 and executes instructions, and a write/read control part 20 which controls the 1st and 2nd selectors 21 and 24 and 1st and 2nd instruction RAMs 22 and 23 and controls the writing of instructions to the instruction RAMs and their reading.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to digital signal processors (DSPs).

[0002]

2. Description of the Related Art FIG. 4 is a conceptual diagram of a conventional system. A portion surrounded by a broken line in the drawing is a digital signal processor (DSP) 10. An instruction RAM 1 is provided in the digital signal processor 10 to write an instruction program from the external ROM 11 and read the written program according to an address from the program counter 2. The read program is given to the instruction processing unit (decoder) 3 and executed. Here, as the instruction RAM 1, a dynamic RAM is used because it is necessary to increase the storage capacity.

An instruction program to be executed by the digital signal processor 10 is written in the external ROM 11, and a read address is given from the external address circuit 12. An address is also given to the instruction RAM 1 from the external address circuit 12, and the instruction RAM 1
The address when writing the program command to is given.

[0004]

In the above-mentioned conventional system, a dynamic RAM or a static RAM is used as a memory. The dynamic RAM may leak stored data over time, and requires a refresh operation for constantly maintaining the original data. Further, when used for communication, it is considered that data may change in the long term due to noise or the like even in the static RAM. RAM like this
However, the RAM cannot be applied to a communication device that is continuously used.

Even when it is not used continuously, R
Since it is necessary to refresh the AM, it is necessary to provide a refresh circuit as a peripheral circuit or perform a program process. However, even in that case, there are problems such as an increase in the number of firmware steps and a specific time required for rewriting the program.

The present invention has been made in view of the above problems, and provides a digital signal processor capable of realizing a refresh operation of an instruction RAM with a simple structure and improving the reliability of a DSP. It is an object.

[0007]

FIG. 1 is a block diagram showing the principle of the present invention. The same parts as those in FIG. 4 are designated by the same reference numerals. In the figure, reference numeral 21 is a first selector that distributes the output of the ROM 11 in two directions, and reference numerals 22 and 23 are first and second instructions from which the program instruction from the ROM 11 is written and read out through the first selector 21. RAM, 24 are the first and second instruction RAMs 22,
The second selector 3 receives the output of 23 and selects one of them, 3 is an instruction execution unit that receives the output of the second selector 24 and executes the instruction, and 20 is the first and second
Selectors 21 and 24 and first and second instruction RAMs 2
A write / read controller for controlling the writing and reading of instructions to and from the instruction RAM by controlling 2 and 23. The portion surrounded by the broken line in the figure is the digital signal processor 10
Is.

[0008]

By controlling the first and second selectors 21 and 24, the ROM 11 is alternately stored in the first and second instruction RAMs 22.
I tried to write the output of. That is, one instruction RAM
Is in write mode, the other instruction RAM
Gives a program instruction to the instruction execution unit 3 in the read mode. In this way, the first and second instruction RAMs 22,
Since the output of the ROM 11 is constantly written in 23,
Since the refresh operation is always performed, the instruction RA
The refresh operation of M is realized with a simple configuration, and
The reliability of the instruction RAM can be improved.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 is a configuration block diagram showing an embodiment of the present invention. The same parts as those in FIGS. 1 and 4 are designated by the same reference numerals. In the figure, 25 is a program counter 2
And a third selector 26 which receives the output of the external address circuit 12 and gives one of them as an address to the first instruction RAM 22, and 26 receives the output of the program counter 2 and the external address circuit 12 and outputs one of them. Is the fourth selector which gives to the second instruction RAM 23 as an address. These third and fourth selectors 25, 2
6, the writing / reading control unit 20 controls the switching. The program counter 2 is the instruction RAM 2
2, 23 read addresses are generated. On the other hand, the external address circuit 12 generates a read address of the ROM 11 and a write address of the instruction RAMs 22 and 23.

The first selector 21 receives the output of the ROM 11, and the output of the ROM 11 is controlled by the write / read controller 20 to provide the first and second instruction RAMs.
It is provided to either one of 22 and 23. A write / read mode setting signal is input from the write / read controller 20 to the first and second instruction RAMs 22 and 23.

The second selector 24 contains the outputs of the first and second instruction RAMs 22 and 23, and either one of them is selected by the switching control signal from the write / read controller 20 to issue an instruction. It is given to the execution unit 3. The instruction execution unit 3 decodes the instruction and operates the numerical operation unit and the data input / output circuit according to the instruction. Reference numeral 4 denotes a numerical operation unit, a data RAM, an input / output circuit, etc. connected to the instruction execution unit 3. The portion surrounded by the broken line is the digital signal processor 10. The operation of the system configured as described above will be described below.

The write / read controller 20 sets the second instruction RAM 23 in the write mode when the first instruction RAM 22 is set in the read mode. And the third
And a control signal to the fourth selectors 25 and 26 so that the output of the program counter 2 is given to the first instruction RAM 22 and the output of the external address circuit 12 is given to the second instruction RAM 23. To do.
In addition, the write / read controller 20 uses the first selector 2
A control signal is given to the first and second selectors 24, and the first selector 21 outputs the output of the ROM 11 to the second instruction RAM 2
3, the second selector 24 supplies the first instruction RAM 22
Is output to the instruction execution unit 3.

As a result, the instruction program read from the first instruction RAM 22 is given to the instruction executing section 3 via the second selector 24, and the instruction is executed. At the same time, the second instruction RAM 23 is in the write mode, and the ROM 1 provided via the first selector 21
The output of 1 is written in the second instruction RAM 23. At this time, the address to the second instruction RAM 23 is given from the external address circuit 12 via the fourth selector 26.

The case where the first instruction RAM 22 is in the read mode and the second instruction RAM 23 is in the write mode has been described above, but the first instruction RAM 22 is in the write mode and the second instruction RAM 23 is in the read mode. Exactly the same. As described above, in the present invention, by providing the two instruction RAMs, the firmware write execution processing can be simultaneously performed. Moreover, when the execution process is being performed, the other instruction RAM
The output of the ROM 11 is written in and the refresh operation is performed.

Here, the mode switching of the two instruction RAMs 22 and 23 can be switched from the interrupt terminal 27 at any time. The switching command (interrupt command) entered from the interrupt terminal 27 is notified to the write / read controller 20. The write / read control unit 20 that has received this switching command, the selector 21,
A control signal is given to 24, 25, 26 and the instruction RAMs 22, 23 to switch the mode so far.

For one machine cycle immediately after the voltage applied to the interrupt terminal 27 changes from "0" to "1", normal DSP processing is stopped and the instruction RAMs 22 and 23 are processed.
It is advisable to set the cycle in which the first selector 21 for exchanging is operated.

Here, the process of switching between the two instruction RAMs 22 and 23 is normally performed by the digital signal processor 1.
In order not to interfere with the processing of 0, the priority of the interrupt instruction for switching the instruction RAM may be set lower than that of other interrupt instructions. RA
It does not matter even if it takes some time to replace M. For example, when an interrupt for voice input is added at the same time, switching of the instruction RAM is waited until the voice input processing is completed. Therefore, an output terminal is required to notify the outside that the switching of the instruction RAM has been completed. That is the terminal 28 of FIG. The transfer of the ROM data may be started after confirming that the code from the output terminal 28 has changed.

As described above, according to the present invention, since the refresh operation of the instruction RAM can be realized with a simple structure, the reliability of the DSP can be improved. FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention. Figure 1,
The same parts as those in FIG. 4 are designated by the same reference numerals. In the figure, 30 is a program register which has the same number of bits as the program counter 2 and generates an address when the ROM 11 is read. Reference numeral 31 is an instruction storage register for temporarily storing the program instruction read from the ROM 11, and 32 is a comparison unit for comparing the output of the program counter 2 and the output of the program register 30 and detecting the coincidence.

33 is an instruction RAM, 34 is the instruction RAM 3
3 is a selector that switches the output of the instruction storage unit 31 and the output of the instruction storage register 31 and gives the instruction execution unit 3. 20 is a comparison unit 3
The output of 2 is received as an interrupt signal, and the instruction RAM 33
It is a write / read control unit that performs mode switching of the above and switching control of the selector 34. The output of the instruction storage register 31 is given to the instruction RAM 33 and the selector 34. The operation of the system configured as described above will be described below.

According to the present invention, the number of instruction RAMs for instruction storage is one and the refresh operation is devised. The present invention rewrites the instruction RAM 33 step by step in one cycle (the number of program steps), and rewrites the contents of the instruction RAM 33 step by step in each cycle.

First, the write / read control unit 20 issues an instruction R.
The AM 33 is set in the read mode, the contents of the instruction RAM 33 are read out, and the instruction execution section 3 is made to execute the contents. At this time, the selector 34 is selecting the instruction RAM 33 side. On the other hand, the program register 30 gives a read address to the ROM 11, but this program register 3
0 counts up once per cycle. Then, when the counted-up value and the output of the program counter 2 match, the comparison section 32 gives an internal interrupt signal to the write / read control section 20.

Upon receiving this internal interrupt signal, the write / read controller 20 sets the instruction RAM 33 to the write mode, and at the same time sets the selector 34 to the instruction storage register 31.
Switch to the side. As a result, the program instruction stored in the instruction register 31 is written in the instruction RAM 33. At the same time, the program instruction stored in the instruction storage register 31 is transmitted via the selector 34 to the instruction execution unit 3
Given to. As a result, the instruction execution unit 3 can execute consecutive instructions. According to this embodiment, 1 per cycle
The contents of the instruction RAM 33 are updated step by step, and the refresh operation is performed. This level is sufficient as the refresh cycle of the instruction RAM 33.

In this embodiment as well, as in the embodiment shown in FIG. 2, the priority of the internal interrupt generated in the comparison unit 32 is
Keep it lower than other interrupt instructions. Also in this embodiment, since the refresh operation of the instruction RAM can be realized with a simple structure, the reliability of the DSP can be improved.

[0024]

As described above in detail, according to the present invention, it is possible to provide a digital signal processor which can realize the refresh operation of the instruction RAM with a simple structure and can improve the reliability of the DSP. it can.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a configuration block diagram showing an embodiment of the present invention.

FIG. 3 is a configuration block diagram showing another embodiment of the present invention.

FIG. 4 is a conceptual diagram of a conventional system.

[Explanation of symbols]

 3 Instruction Execution Unit 10 Digital Signal Processor (DSP) 11 ROM 20 Write / Read Control Unit 21 First Selector 22 First Instruction RAM 23 Second Instruction RAM 24 Second Selector

Claims (7)

[Claims] 1. A first selector (21) that distributes an output of a ROM (11) in two directions, and a program command from the ROM (11) is written and read through the first selector (21). First and second instruction RAMs (22) and (23), and a second selector that receives the outputs of the first and second instruction RAMs (22) and (23) and selects one of them (24), an instruction execution unit (3) for executing an instruction by receiving an output of the second selector (24), the first and second selectors (21), (24) and the first and second A digital signal processor including a write / read controller (20) for controlling second instruction RAMs (22) and (23) to control writing and reading of instructions to and from the instruction RAM. 2. The write / read control unit (20) comprises:
When the first instruction RAM (22) is in the write mode, the second instruction RAM (23) is in the read mode, and when the first instruction RAM (22) is in the read mode, the second instruction RAM (23) is In the write mode, the first instruction RAM (22) and the second instruction RAM (2
3. The digital signal processor according to claim 1, wherein an instruction from the ROM (11) is written in 3) to refresh the RAM. 3. An external interrupt terminal is provided, and the first and second instruction RAMs (22) are externally provided at arbitrary times.
2. The digital signal processor according to claim 1, wherein the switching of (23) is made possible. 4. The digital signal processor according to claim 3, wherein the priority of the external interrupt instruction is set lower than that of other interrupt instructions. 5. An instruction RAM (33) in which program instructions from the ROM (11) are written and read out.
An instruction storage register (31) for storing an output instruction of the ROM (11), a program register (30) for giving a read address of the ROM (11), and outputs of the program register (30) and the program counter (2) A comparing unit (32) for comparing the instruction storage register (31) and the instruction RAM (33)
Of the selector (34) that receives the output of the selector (34) and selects one of them, an instruction execution unit (3) that receives the output of the selector (34) and executes the input instruction, and a comparator (32). A digital signal processor comprising a write / read controller (20) which receives a coincidence output as an interrupt signal to control writing and reading of the instruction RAM (33) and controls switching of the selector (34). 6. The write / read controller (20) comprises:
Normally, when the output of the instruction RAM (33) is given to the instruction execution unit (3) and the coincidence output of the comparison unit (32) is received as an interrupt, the selector (34) is controlled to store the instruction in the instruction execution unit (3). 6. The digital signal processor according to claim 5, wherein the output of the register (31) is given and the same instruction is written in the instruction RAM (33). 7. The digital signal processor according to claim 6, wherein the priority of the internal interrupt is set lower than that of other interrupt instructions.