JPS6258340A - Register updating mechanism - Google Patents

Abstract

PURPOSE:To reduce the firmware capacity and to shorten the exception processing time by providing a switching means which can change the indication of direction for increase or decrease updating with the register updating informationheld by a holding means by an exception signal between the holding means and a constant generating means. CONSTITUTION:A register updating mechanism consists of a register qualifying means 1, a register part 2, a register selecting circuit 3, a holding means 4, a constant generating means 5, an adder 6 and a switching means 7. The means 7 supplies an exception signal 10 through an exception detecting circuit to show the presence or absence of an exception. The circuit 3 selects a register out of the part 2 and connect it to the adder 6 via a bus when the signal 10 applied via an OR circuit 12 or a register replacement signal 11 is active.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mechanism for updating index registers and the like necessary for calculating memory addresses in information processing xZf.

[Conventional technology]

In an information processing device that executes instructions using a pipeline control method, the steps of reading, decoding, and executing instructions are performed in a reading section, a decoding section, and an execution section, respectively. in this case,
The effective address of an instruction is found in the decoder, but the index register is updated in the case of index modification in the execution part. Therefore, it is necessary to transfer update information of the index register from the decoding section to the execution section.

FIG. 2 is a block diagram of a conventional register update mechanism.
When data is set in the register modifying means 1 and the holding means 4 from the instruction decoding section, the execution section operates to update the registers using this data immediately before executing the instruction. That is, the register modification means I is set with designation information of the register to be updated by the instruction decoding section, and the register selection circuit 3 selects one register from among the plurality of registers in the register section 2 based on the designation information. , the contents of the selected register are added to one input of the adder 6. On the other hand, the register update information is sent to the holding means 4 from the instruction decoding section, and the constant generating means 5 generates a positive or negative constant according to the direction instruction of increase update/decrease update and the update number information in the register update information. generated and added to the other power of adder 6.

The adder 6 adds the input again, and the addition result is written back to the register of the register section 2 selected by the register selection circuit 3, completing the predetermined register update.

[Problem that the invention seeks to solve]

By the way, when an exception occurs while executing an instruction in the execution section, such as an exception related to memory management of virtual memory, and the currently executing instruction fails (aborts), the register used as the index register remains updated. If you do so, you will not be able to restart the command correctly when you try to restart it. In order to correctly restart the failed instruction, it is necessary to cancel the update of the index register.

Cancellation of such an index register update is
In the conventional configuration shown in FIG. 2, when an exception occurs, the firmware creates data necessary for reverse updating of the register in response to an exception signal indicating the occurrence, and sends the data to the register modification means 1 and the holding means 4 via the bus. This was done by sending the data as a cent. Therefore, there are problems in that the capacity of the firmware increases and the time required for exception processing increases.

The present invention solves these conventional problems, and its purpose is to make it possible to cancel register updates without significantly increasing firmware capacity, and to shorten exception processing time. be.

[Means for solving problems]

In order to achieve the above object, the present invention includes a register new information holding means and a constant generating means for generating a constant according to the register update information held in the holding means in order to execute a register modification addressing instruction. a register modification means that holds designation information of a register to be updated; a register section including a plurality of registers; and a register designated by the designation information held in the register modification means from among the plurality of registers in the register section. In a register updating mechanism in an information processing device, the register updating mechanism includes a register selection circuit that selects a register selection circuit, and an adder that adds the contents of the register selected by the register selection circuit and a constant output from the constant generation means, A configuration is adopted in which a switching means is provided between the holding means and the constant generating means for switching the direction instruction of increasing update/decreasing update included in the register update information from to the opposite direction by an exception signal.

[Effect]

When an exception is not detected, the switching means adds the register update information of the holding means to the adder while leaving the direction instruction of increase update/decrease update included in the register update information held in the holding means unchanged, so that the instruction is not decoded. The register is updated according to the contents given from the section. On the other hand, when an exception is detected, the switching means switches the register update information held in the holding means to the increment update/decrease update direction in the reverse direction and adds it to the adder. If the update information instructs an increase update, a decrease update is performed; conversely, if the update information instructs a decrease update, an increase update is performed, and the register update is canceled.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the invention.

The register update mechanism of this embodiment is the register modification means 1.
, a register section 2 , a register selection circuit 3 , a holding means 4 , a constant generation means 5 , an adder 6 , and a switching means 7 . The switching means 7 receives an exception signal 10 indicating whether an exception has occurred from an exception detection circuit (not shown), and the register selection circuit 3 receives either the exception signal 10 applied via the OR circuit 12 or the register update signal 11. When activated, one register is selected from the register section 2, and the selected register is connected to the adder 6 through a lotus. Register update (No. 8 11 is controlled by a register update sequencer (not shown) to execute register update immediately before executing an instruction in the execution section.

Now, let us consider the case where no exception occurs and a normal register update is executed. The register modification means 1 is composed of, for example, a register with a capacity of 6 bits.
Assume that a binary value (B at the end indicates a binary number) is stored from the instruction decoder. The holding means 4 is composed of a register with a 4-bit capacity, for example, and it is determined whether the most significant bit of the 4-bit register update information set by the instruction decoder is "1" or "0".
Or it shows “no update” and the next focus is “1” or “0”
The number indicates "decreasing update" or "increasing update", and the lower two bits determine the number of updates 1.2.4.8. For example, when a binary value of 100IB is stored in the holding means 4, this indicates a +2 update.

Assuming that 0OOOOIB is stored in the register modification means l and 100IB is stored in the holding means 4, when the exception signal does not indicate that an exception has occurred, the contents of the holding means 4 are 1001
B is transmitted as it is to the constant generating means 5. Constant generation means 5
Now, a value of 0O02H (the H at the end indicates a hexadecimal number) is output to the adder 6 for the human-powered 100IB. On the other hand, according to the content 000001B of the register modification means 1, the register selection circuit 3 selects the register R from the register section 2.
1 is selected, and when the register update signal 11 becomes active indicating that there is an update, the contents of the register R1 are output to the adder 6.

The adder 6 adds the above two pieces of data, and the resulting data is written back to the register R1 selected by the register selection circuit 3. In this way, register R1 is updated and execution of the instruction is started in the execution section.

Now, if an exception occurs during this execution, the exception signal 10 becomes active indicating that an exception has occurred, so
The switching means 7 outputs 1101B indicating reverse update with respect to the input 100IB. In response to this output, the constant generating means 5 outputs FFFEI(, and the adder 6 outputs an exception signal l
At O, the contents of register R1 successively read out from register section 2 are added by "-2" and written back to register R1, so the contents of register R1 (7) return to the state before the execution of the instruction in which this exception occurred. Instructions can be resumed immediately.

[Effects of the Invention] As explained above, the present invention is capable of changing the direction of increment update/decrease update in the register update information held in the holding means by an exception signal between the holding means and the constant generation means. By providing a possible switching means, it is possible to reversely update the register when an exception occurs, or cancel the update, without the firmware being aware of it, which has the effect of reducing the firmware capacity and shortening the exception processing time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional register update mechanism. In the figures, 1 is a register modification means, 2 is a register section,
3 is a register selection circuit, 4 is an update information holding means, 5 is a constant generation means, 6 is an adder, 7 is a switching means, 10 is an exception signal, 11 is a register update signal, and 12 is an OR circuit. \-1, the real sister of the present invention 1] Block diagram 1. Regrets in deciphering foggy commands Blog field of conventional example of command MH verb 2. Prisoners

Claims (1)

[Claims] In order to execute a register modification addressing instruction, a means for holding register update information, a constant generating means for generating a constant according to the register update information held in the holding means, and information specifying the register to be updated are held. a register modification means, a register section including a plurality of registers, a register selection circuit for selecting a register specified by specification information held in the register modification means from among the plurality of registers of the register section, and the register selection circuit. In a register update mechanism in an information processing device having an adder that adds contents of a register selected by a circuit and a constant output from the constant generating means, an incremental update included in the register update information from the holding means is performed. 1. A register update mechanism, characterized in that a switching means for switching the direction of decrement update to the opposite direction in response to an exception signal is provided between the holding means and the constant generating means.