JPH0715249Y2 - Automatic white balance adjustment circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to an automatic white balance adjustment circuit which is preferably implemented in an image pickup device called a color video camera or the like.

2. Related Art Light illuminating a subject has various shades such as reddish light and bluish light. This depends on the weather, location, time, type of lighting, etc., and this shade of light is usually indicated by color temperature.

In a color camera, in order to accurately reproduce the color of a subject, it is necessary to adjust so that a white subject is reproduced as white under the illumination condition of each color temperature. Adjusting the color camera in this way is called "adjusting the white balance".

Automatic white balance adjustment used in a color video camera is roughly classified into a type using a color temperature sensor and a type using a video signal. Here, a type using a video signal will be described.

In general, the imaged subject includes various colors. Therefore, it is expected that when these colors are all overlaid, the color becomes almost white. On the other hand, when a white subject is imaged, the level of the color difference signal is zero level. Therefore, if the average value of the levels of the color difference signals over a certain period of time is zero, it is expected that the white balance is correct.

FIG. 3 shows a conventional automatic white balance adjusting circuit 1.
3 is a block diagram showing the electrical configuration of FIG. Color signals R and B corresponding to red and blue in a signal processing circuit (not shown)
And the color difference signals RY and BY generated from the luminance signal Y
Are input to the clump circuits 2 and 3, respectively. The clamp pulse and the reference voltage V _REF are further applied to each of the clamp circuits 2 and 3, and the DC voltage V _REF is added to each of the color difference signals RY and BY. In this way
The color difference signals R-Y and B-Y to which the DC voltage V _REF is added are given to the integrator circuits 4 and 5 to be smoothed, and their average value levels are input to the non-inverting input terminals of the comparators 6 and 7, respectively. To be done. The integrating circuit 4 includes a resistor R1 and a capacitor C1, and the integrating circuit 5 includes a resistor R2 and a capacitor C2. The reference voltage V _REF is applied to the inverting input terminals of the comparators 6 and 7, and their output signals are input to the counter drive circuit 10.

A clock signal is given to the counter drive circuit 10,
The output signals of the comparators 6 and 7 are read in synchronization with the clock signal, and the counters 13 and 1 are read based on the respective output signals.
Outputs a signal for adding or subtracting the operations of 4. The counting operation of the counters 13 and 14 is carried out by the counter drive circuit 10 in synchronization with a clock signal provided in parallel with an output signal defining its operation. The counters 13 and 14 are realized by 8-bit counters, for example, and the count value is represented by 8-bit binary data.

The count values of the counters 13 and 14 are provided in parallel to 8-bit digital / analog (hereinafter abbreviated as D / A) converters 15 and 16 and converted into analog signals. As the D / A converters 15 and 16, generally, ladder resistor circuits using two types of resistors having a resistance value R and a resistance value 2R are used.

The output signals of the D / A converters 15 and 16 are given to an interface 19 including resistors R5, R6, R7, R8 and buffers 17 and 18, and the level thereof is adjusted to produce a white balance control signal. , RY control signal and BY control signal are output. These RY control signal and BY control signal are respectively applied to the signal processing circuit, and the color difference signals RY and B- are supplied.
The average value level of Y is changed.

The comparator 6 is a DC voltage applied from the integrating circuit 4.
When the average value level of the color difference signal R-Y to which V _REF is added is higher than the reference voltage V _REF , a high level signal voltage is output, and when it is low, a low level signal voltage is output.

When a high-level signal voltage is applied to the counter drive circuit 10, the counter drive circuit 10 supplies a signal to the counter 13 to add the calculation, the counter 13 increments the count value by 1, and the low-level signal voltage is increased. Given, counter 13
Is subtracted, and the count value is decremented by one.

Comparing the signal levels in the comparator 6 eventually means comparing the average value level of the color difference signal RY and the zero level, and therefore the count value of the counter 13 becomes a value according to the color temperature. The level of the RY control signal also becomes a level corresponding to this, and the count value of the counter 13 corresponds to the color temperature by leading the average value level of the color difference signal RY to zero by this RY control signal. Converge to a value.

The same applies to the color difference signal BY, and the white balance is adjusted in this way.

The automatic white balance adjustment circuit 1 as described above is premised on that the imaged subject contains various colors. Therefore, it may not be possible to properly adjust the white balance for a subject whose color is biased. As a countermeasure against this, in the automatic white balance adjusting circuit 1, the capacitances of the capacitors C1 and C2 and the resistance values of the resistors R1 and R2 included in the integrating circuits 4,5 are adjusted,
Further, the cycle of the clock signal supplied to the counter drive circuit 10 is made relatively long to delay the response and suppress the deviation of the white balance.

Problems to be Solved by the Invention As described above, in the automatic white balance adjusting circuit 1 having a slow response, the rise thereof is poor at the time of power-on,
Immediately after the power is turned on, the white balance is largely deviated in the image pickup state.

It is an object of the present invention to provide an automatic white balance adjustment circuit in which the white balance is correctly adjusted immediately after the power is turned on, and therefore good image pickup is possible.

Means for Solving the Problems The present invention relates to a power-on detection means for detecting a power-on state, a clock generation means whose oscillation frequency changes according to an output of the power-on detection means, and the clock generation means. An automatic white balance adjusting circuit, which includes a signal generating means for generating a white balance control signal at an operation speed corresponding to the clock signal from the.

In the present invention, the operating speed of the signal generating means for generating the white balance control signal is set to the operating speed corresponding to the clock signal from the clock generating means, and the oscillation frequency of the clock generating means is the output of the power-on detecting means. Change according to. As a result, an automatic white balance adjustment circuit with good transient response immediately after power-on is realized.

Embodiment 1 FIG. 1 is a block diagram showing an electrical configuration of an automatic white balance adjusting circuit 21 which is an embodiment of the present invention. Color difference signals RY and BY are given to an automatic white balance adjusting circuit 21 from a signal processing circuit (not shown) and inputted to clamp circuits 22 and 23, respectively. Each of the clamp circuits 22 and 23 is further provided with a clamp pulse and a reference voltage V
_Ref is given, and the DC voltage V _ref is added to each of the color difference signals RY and BY. The clamp pulse is given, for example, in the horizontal blanking period of the image scanning period.

The color difference signals R-Y and B-Y to which the DC voltage _Vref is added are next input to the integrating circuits 24 and 25 and smoothed, and their average value levels are input to the non-inverting input terminals of the comparators 26 and 27, respectively. Given. The integrating circuit 24 includes a resistor R11 and a capacitor C11, and the integrating circuit 25 includes a resistor R12 and a capacitor C12.
It is configured to include and.

The reference voltage V _ref is applied to the inverting input terminals of the comparators 26 and 27, respectively. The comparator 26 is, for example, a DC voltage input from the integrating circuit 24 to its non-inverting input terminal.
When the average value level of the color difference signal RY to which V _ref is added is higher than the reference voltage V _ref , a high level signal voltage is output, and when it is low, a low level signal voltage is output. Therefore, as a result, the comparator 26 determines that the color difference signal RY
Corresponding to the positive and negative of the average value level of, respectively high level,
A low level signal voltage will be output. The comparator 27 performs the same operation for the color difference signal BY.

The output signals of the comparators 26 and 27 are given to the counter drive circuit 30. A clock signal is also applied to the counter drive circuit 30, the signal voltages output from the comparators 26 and 27 are read in synchronization with this, and signals corresponding to the respective voltage levels are applied to the counters 33 and 34. Counter 33,34
A clock signal is applied to each of the above in parallel with the aforementioned signal from the counter drive circuit 30, and the counting operation is performed in synchronization with this clock signal.

The counter drive circuit 30, for example, gives a signal to the counter 33 such that the operation of the counter 33 is added when the output signal voltage of the comparator 26 is at a high level, and subtracts the operation when the output signal voltage is at a low level. give. This also applies to the counter 34, and the signal corresponding to the output signal voltage of the comparator 27 is
Given to 34. The counters 33 and 34 may be 8-bit counters, for example.

The count values of the counters 33 and 34 are stored in the D / A converters 35 and 36, respectively.
It is given in bit parallel and converted into an analog signal.
For example, the D / A converters 35 and 36 have a resistance value R and a resistance value 2R.
It may be a ladder resistance circuit using various types of resistance. D /
The analog signal output from the A converters 35 and 36 is the resistor R15,
The signal processing circuit is supplied to an interface 39 including R16, R17, R18 and buffers 37, 38, and the level thereof is adjusted to serve as an RY control signal and a BY control signal which are white balance control signals. To the color difference signal RY,
The BY average value level is changed.

The integration circuits 24 and 25, the comparators 26 and 27, the counter drive circuit 30, the counters 33 and 34, the D / A converters 35 and 36, and the like constitute signal generation means for generating a white balance control signal.

The clock signal supplied to the counter drive circuit 30 is supplied from the frequency divider 40. A pulse VD having a period of, for example, one vertical scanning period is given to the frequency divider 40, and the frequency of 4
The division ratio is determined by the voltage levels applied to the two terminals b0 to b3, and the clock signal is output. Divider 40 terminals
b0~b3 each, the voltage of a high level or low level is applied, thus setting in operation state of 2 ⁴ ways. This is realized by applying 4-bit data in parallel to the terminals b0 to b3. For example, if the high level is represented by "1" and the low level is represented by "0", the terminal b0 is the least significant bit.
When the terminal b3 corresponds to the most significant bit, the operation state of the frequency divider 40 is defined by the following 4-bit data string 0000, 0001, 0010, ..., 1111 (0) (1) (2) (15). . The numbers in the parentheses above are the corresponding decimal representations of the binary numbers.

For example, if a low level voltage is applied to terminals b0 and b2 and a high level voltage is applied to terminals b1 and b3, the operating state of frequency divider 40 at this time is (1
010) ₂ = 10 and in this case the divider 40 divides the input signal by 1/10. However, the subscript 2 indicates that it is a binary number.

DC voltage _Vcc is applied to terminal b0 of frequency divider 40, and terminal b0
Is at a high level while the power is on. A clock generating means is configured including the frequency divider 40.

The terminals b1, b2, b3 of the frequency divider 40 are connected to the output terminal of the comparator 42 via the line 41. The reference voltage V _c is applied to the inverting input terminal of the comparator 42. The non-inverting input terminal, the resistor R20, the capacitor C13, and the anode of the diode D1 are connected at the connection point 44. The other end of the capacitor C13 is grounded, the cathode of the other end and the diode D1 in the resistor R20, is given a DC voltage V _cc during the period that power is on. The diode D1 is provided to speed up the discharge of the capacitor C13 when the power is cut off. The power-on detecting means is configured by including the comparator 42, the resistor R20, the capacitor C13 and the like.

The comparator 42 outputs a high level signal voltage when the voltage level applied to the non-inverting input terminal is higher than the reference voltage V _c , and outputs a low level signal voltage when the voltage level is low. Therefore, terminals b1, b2, b3 of divider 40
Is supplied with a high level voltage and a low level voltage corresponding to the high level and low level of the output signal voltage level of the comparator 42.

When low level voltage is applied to the terminals b1, b2, b3, the operating state of the frequency divider 40 is defined by (0001) ₂ = 1.
(1111) ₂ = 1 when high level voltage is applied
The frequency division ratios are defined by 5 and are 1/1 and 1/15, respectively, and the cycle of the clock signal provided to the counter drive circuit 30 is the cycle of the pulse VD and the cycle of 15 times the cycle of the pulse VD, respectively.

FIG. 2 is a waveform diagram showing changes in the voltage levels of the respective parts when the power is turned on. FIG. 2 (1) shows the changes in the power supply voltage and FIG. 2 (2) shows the voltage applied to the non-inverting input terminal of the comparator 42. The change in the level is shown in (3) of the figure which shows the output signal of the comparator 42, and (4) in the figure shows the pulse which is given to the frequency divider 40.
VD and (5) in the figure show the clock signal output from the frequency divider 40. When the power is turned on at time t1, the capacitor
The DC voltage _Vcc is applied to C13 via the resistor R20, and charging is started. As the capacitor C13 is charged, the potential difference between both ends of the resistor R20 gradually decreases, and the potential of the connection point 44, that is, the voltage level applied to the non-inverting input terminal of the comparator 42, increases, until the DC voltage V _cc. Go up.

At time t2, when the voltage level applied to the non-inverting input terminal of the comparator 42 exceeds the reference voltage V _c , the output signal voltage of the comparator 42 becomes high level. Note that time t1
A low-level signal voltage is output during the period ΔT1 from t2. At this time, the operating state of the frequency divider 40 is defined by (0001) ₂ = 1 in the period ΔT1, and the period ΔT after the time t2
2 is defined as (1111) ₂ = 15. Therefore, the period of the clock signal as shown in (5) of the figure becomes the same period as the pulse VD shown in (4) of the figure in the period ΔT1,
In the period ΔT2, the period is 15 times the period of the pulse VD.

Therefore, during the period ΔT1, the counting operation of the counters 33 and 34 is performed at a speed 15 times faster than the period ΔT2 based on the signal voltage output from the comparators 26 and 27, and the white balance is adjusted very quickly. It becomes possible to improve the transient response immediately after the power is turned on.

Effects As described above, according to the present invention, an automatic white balance adjustment circuit that realizes a quick transient response when the power is turned on and that enables stable white balance adjustment is realized, and good imaging can be performed. Become.

In particular, according to the present invention, it is possible to ensure the followability of the full auto white balance after the power is turned on by increasing the response speed for several seconds after the power is turned on.

[Brief description of drawings]

FIG. 1 is a block diagram showing the electrical configuration of an automatic white balance adjusting circuit 21 which is an embodiment of the present invention, FIG. 2 is a waveform diagram showing changes in the voltage level of each part when the power is turned on, and FIG. It is a block diagram which shows the electric constitution of the automatic white balance adjustment circuit 1 of a prior art. 21 ... Automatic white balance adjusting circuit, 24, 25 ... Integrating circuit, 26, 27, 42 ... Comparator, 30 ... Counter driving circuit,
33,34… Counter, 35,36… D / A converter, 40… divider

Claims (1)

[Scope of utility model registration request] 1. A power-on detection unit that detects a power-on state, a clock generation unit that changes an oscillation frequency according to an output of the power-on detection unit, and a clock signal from the clock generation unit. An automatic white balance adjusting circuit comprising: a signal generating means for generating a white balance control signal at an operating speed.