JPH07146668A - Driving circuit for liquid crystal display device - Google Patents

Abstract

PURPOSE:To enable displaying the video signal of a non-interlace driving on a display device performing an interlace driving. CONSTITUTION:In this circuit. the video signal of the non-interlace driving is discriminated based on a field signal O/E outputted from a field discriminating circuit 22 and indicating even numbered fields and odd numbered fields and a vertical synchronizing signal V and the output FC of a field inverting signal generating circuit 31 is supplied to a splitting circuit 32 in stead of the field signal O/E according to a discrimination output DET by a switching circuit 29. Therefore, even in the case of the non-interlace driving, the video signal is displayed on a display electrode connected to an odd numbered gate line and a display electrode connected to an even numbered gate line because the start pulse STV-O of an odd numbered gate line driver and the start pulse STV-E of an even numbered gate line driver are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for interlace driving a liquid crystal display device having an odd line gate driver and an even line gate driver.

[0002]

2. Description of the Related Art Generally, a liquid crystal display device for TV has a T
The active matrix type using FT is mainly used. In the case of the NTSC system, the number of effective scanning lines is about 480 among the 525 horizontal interlaced scanning lines. Therefore, in a liquid crystal display device for TV,
Eighty gate lines are provided, of which 240 odd lines and 240 even lines are driven in an odd field and an even field, respectively.

FIG. 3 is a schematic view of the above-mentioned liquid crystal display device. The liquid crystal panel 1 is provided with 480 gate lines 2 and a large number of drain lines 3 intersecting the gate lines 2, and the gate lines 2 and the drains are provided. TFTs and pixel electrodes (not shown) are provided at the intersections of the lines 3, respectively. The odd line and the even line of the gate line 2 are taken out separately from each other on the left and right sides, and are taken out by the odd gate line driver 4 respectively.
And even-numbered gate line driver 5 are connected. The drain line 3 is also separated from the upper and lower sides and taken out, and connected to the drain drivers 6 and 7, respectively.

The odd gate line driver 4 has an odd number of gate lines.
The start pulse STV-O applied in the field
Therefore, the operation is started according to the horizontal sync signal of the odd field.
Expected line clock f_HODrive odd lines in sequence
Move. The even gate line driver 5 has an even feel.
The start pulse STV-E applied at
To start the operation and synchronize with the horizontal sync signal of the even field
Line clock f _HEDrive even lines sequentially
To do. The drain drivers 6 and 7 each have a 90 degree phase difference.
With dot clocks DCK-A and DCK-B with
Drive each drain line to
R, G, B video signal voltages are selectively supplied.

In the liquid crystal display device shown in FIG.
The drive circuit for displaying an image is configured as shown in FIG. In FIG. 4, the sync separation circuit 8 is a well-known circuit that extracts the vertical sync signal V and the horizontal sync signal H included in the video signal VIDEO. The field discriminating circuit 9 discriminates between an odd feed and an even field based on the vertical synchronizing signal V and the horizontal synchronizing signal H. For example, a field which becomes "H" level in an odd field and "L" level in an even field. The signal O / E is output to the distribution circuit 10.

On the other hand, VCO (voltage controlled oscillator) 11, H
(Horizontal) counter 12, H (horizontal) decoder 13, phase
The comparison circuit 14 constitutes a PLL circuit, and has a V
For example, 920f oscillated by CO11_H(Horizontal same
Output of 920 times the frequency of the target signal)
12 counts, and the count value becomes 1 field.
The H decoder 13 detects that
The H counter 12 is reset by the loose H-CLR.
Further, the phase comparison pulse PDF obtained from the H decoder 13
Comparing H and the horizontal synchronizing signal H by the phase comparison circuit 14.
By 920f _HThe accurate oscillation output of is obtained. Furthermore,
2f obtained by H decoder_HV for counting the pulses of
The counter 15 and the V (vertical) decoder 16 are used to
Generate a pulse pulse STV. The line clock f_HO
And f_HEDrive timing signals for various liquid crystal display devices
Is output from the H decoder 12. Where V counter
2f for 15 clock inputs_HIs an odd feel
And the horizontal sync signal is shifted by 0.5H in the even field.
It is.

In the drive circuit of FIG. 4, when the field discriminating circuit 9 detects an odd field, the field signal O / E becomes "H" level. When the start pulse STV is output in this state, the start pulse STV
Is the start pulse ST of the odd gate line driver 4
It is output as V-O. Therefore, at this time, the odd gate line driver 4 is driven by the line clock f _HO , and an image of the odd field is displayed on the display electrode connected to the odd gate line. When the field discrimination circuit 9 detects an even field, the field signal O
/ E becomes "L" level, and the start pulse STV is the start pulse STV-E of the even gate line driver 5.
Is output as. Therefore, at this time, the even gate line driver 5 is driven by the line clock f _HE ,
Images of even fields are displayed on the display electrodes connected to the even gate lines.

By repeating the above operation, interlaced driving is performed.

[0009]

In the above-mentioned liquid crystal drive circuit, when a non-interlaced drive video signal is applied, the field discrimination circuit 9 can only discriminate between an odd field and an even field. For example, if it is determined that all the fields of the video signal are odd fields, the field signal O / E is always fixed to the "H" level, so the distribution circuit 10 always outputs the start pulse STV to STV-O. become. Therefore, in this case, the odd gate line driver 4 is driven in each field, and the image is displayed on the display electrodes connected to the odd gate lines and displayed on the display electrodes connected to the even gate lines. It will not be done.
Therefore, white lines or black lines are displayed every other line, which makes it difficult to view the image.

Therefore, the liquid crystal display device having the above-mentioned liquid crystal drive circuit cannot be used for a device that generates a non-interlaced drive video signal, for example, a display device such as a monitor of a personal computer terminal. On the other hand, in order to display the interlaced drive video signal and the non-interlaced drive video signal on the same display device, the odd gate lines and the adjacent even gate lines are simultaneously driven, and the odd gate line display electrodes and the even gate lines are A two-line simultaneous driving method for displaying the same on the display electrodes is conceivable. This method may be used for black and white display, but color display is not possible with a single panel. That is, in the case of a mosaic arrangement in which the color filters of the odd-numbered gate lines and the even-numbered gate lines are arranged differently, if two lines are driven at the same time, there arises a problem that the video signals of the respective colors are not applied to the display electrodes of the corresponding colors.

[0011]

The present invention has been made in view of the above-mentioned points, and discriminates between an odd field and an even field based on a video signal and outputs a signal indicating the even field and the odd field. And a start pulse distributing means for supplying a start pulse to the odd gate line driver in the odd field and a start pulse to the even gate line driver in the even field according to the output of the field judging means, and the video signal. Field inversion signal generating means for generating a field inversion signal which is inverted for each field based on the above, non-interlace judging means for judging that the video signal is non-interlaced based on the video signal, and the non-interlace judging means is non-interlace To the signal that A switching means for supplying the field inversion signal to the distributing means in place of the output signal of the field discriminating means, and alternately supplying a start pulse to the odd gate line driver and the even gate line driver even during non-interlacing. A drive circuit for a liquid crystal display device is provided.

[0012]

According to the above means, when a video signal for non-interlaced driving is supplied, even if the field discriminating means does not discriminate between an odd field and an even field, each field is generated by the field inversion signal generating means. A field inversion signal that is inverted every time is created. On the other hand, when the non-interlace discriminating means discriminates the non-interlace, the discriminating output causes the switching means to supply the field inversion signal to the distribution circuit instead of the output of the field discriminating means. As a result, the distribution circuit alternately supplies the start pulse to the odd-numbered gate line driver and the even-numbered gate line driver based on the field inversion signal. Therefore, even if the video signal is a non-interlaced drive, the video of each field is The display electrodes connected to the odd gate lines and the display electrodes connected to the even gate lines are alternately displayed.

[0013]

FIG. 1 is a block diagram showing an embodiment of the present invention. As in the conventional case, the sync separation circuit 21 controls the video signal V
Vertical sync signal V and horizontal sync signal H included in IDEO
Is a well-known circuit for taking out. Field discrimination circuit 22
Discriminates an odd feed from an even field based on the vertical synchronizing signal V and the horizontal synchronizing signal H. For example, a field signal O / E which becomes "H" level in an odd field and "L" level in an even field. Is output.

On the other hand, VCO (voltage controlled oscillator) 23, H
(Horizontal) counter 24, H (horizontal) decoder 25, phase
The comparison circuit 26 constitutes a PLL circuit, and has a V
For example, 920f oscillated by CO23_H(Horizontal same
Output of 920 times the frequency of the target signal)
24, and the counted value becomes 1 field.
The H decoder 25 detects that
The H counter 24 is reset by the loose H-CLR.
The phase comparison pulse PDF obtained from the H decoder 25
Comparing H and the horizontal synchronizing signal H by the phase comparison circuit 26.
By 920f _HThe accurate oscillation output of is obtained. Furthermore,
2f obtained by H decoder 25_HV for counting pulses
(Vertical) counter 31 and V (vertical) decoder 32
A start pulse STV is generated. Line clock
f_HOAnd f_HEDriving timing of various liquid crystal display devices
The signal is output from the H decoder 25. Where V Cow
The clock input of_HIs an odd number
Horizontal sync signal is shifted by 0.5H between field and even field
This is because

The field signal O / E of the field discriminating circuit 22 is supplied to the switching circuit 27 and also to the non-interlace discriminating circuit 28. The non-interlace discriminating circuit 28 is a circuit for discriminating whether the video signal VIDEO is interlaced drive or non-interlaced drive based on the vertical synchronizing signal V and the field signal O / E, and its discriminant output DET is the switching operation of the switching circuit 27. Is applied to the switching circuit 27 to control

On the other hand, the field inversion signal generation circuit 29
Generates a signal FC that is inverted for each field based on the vertical synchronizing signal V and applies it to the switching circuit 27. The switching circuit 27 selectively outputs the field signal O / E in the case of interlace drive and the field inversion signal FC in the case of non-interlace drive according to the discrimination output DET, and the selected signal is the distribution circuit. Thirty
Is supplied to. The distribution circuit 30 distributes the start pulse STV to the start pulse STV-O of the odd gate line driver 4 and the start pulse STV-E of the even gate line driver 5 according to the signal supplied from the switching circuit 27, and outputs the start pulse STV-E.

The non-interlace discrimination circuit 28 described above,
Specific circuits of the field inversion signal generation circuit 29, the switching circuit 27, and the distribution circuit 30 are shown in FIG. As shown in FIG. 2, the non-interlace discrimination circuit 28 includes two counters 28-1 and 28- for counting the vertical synchronization signal V.
2, each counter 28-1 and 28-2 is reset by the field signal O / E and its inverted signal * O / E. Each of the counters 28-1 and 28-2 is composed of 2 bits, and the carry output is output as the discriminant output DET via the OR gate 28-3.
That is, when the field discriminating circuit 22 discriminates between an odd field and an even field, the field signal O / E repeats the "H" level and the "L" level for each field, so that each counter 28-1 28-2 are reset and carry does not occur, but when the field discriminating circuit 22 does not discriminate between the odd field and the even field, that is, in the case of non-interlaced driving, the field signal O / E is
Since it is fixed to the “H” or “L” level, one of the counters 28-1 and 28-2 counts the vertical synchronizing signal V, and when the vertical synchronizing signal V of four fields is counted, it carries “H”. Occurs. This carry enables discrimination of non-interlaced drive. When a carry occurs, the counter 28-1
And the vertical synchronizing signal V supplied to 28-2 is applied to the gate 28.
-4, so that the counters 28-1 and 28-2
The counting of 8-2 is stopped and the carry "H" is held.

The field inversion signal generation circuit 29 has a T-FF 29-to which the vertical synchronizing signal V is applied to the clock input.
The output Q of the T-FF is a signal FC that is inverted for each field, like the field signal.
The switching circuit 27 includes AND gates 27-1 and 27-2.
And an inverter 27-3 and an OR gate 27-4, the discriminating output DET is "L".
AND signal 2 when the field signal O / E is level
The field inversion signal FC is output via the AND gate 27-2 when the discrimination output is at the "H" level.

The distribution circuit 30 is composed of AND gates 30-1 and 30-2 and an inverter 30-3, and when the output of the switching circuit 27 is at "H" level, the AND gate 30.
-1 outputs the start pulse STV as STV-O, and when the output of the switching circuit 27 is at "L" level, AN
The start pulse STV from the D gate 30-2 is STV-
It is output as E.

Therefore, in the interlace drive, when the field signal O / E of the field discriminating circuit 22 becomes "H" level in the odd field and "L" level in the even field, the discriminant output DET of the non-interlace discriminating circuit 28 is , L level, the switching circuit 27 outputs the field signal O / E to the distribution circuit 30. In this case, the start pulse STV becomes the start pulse STV-O of the odd gate line driver 4 in the odd field where the field signal O / E is “H” level. On the other hand, in the case of non-interlaced driving, the field signal O / E of the field discrimination circuit 22 is, for example, "H".
When fixed to the level, the non-interlace discrimination circuit 2
The counter 28-2 of 8 counts the vertical synchronizing signal V, and the carry becomes “H” level, so that the switching circuit 27 outputs the field inversion signal FC to the distribution circuit 30. In this case, the start pulse STV-O is output when the field inversion signal FC is at "H" level, and the start pulse S is output when the field inversion signal FC is at "L" level.
TV-E is output.

As described above, even when the non-interlaced drive video signal VIDEO is input, the field inversion signal FC created instead of the field signal O / E is supplied to the distribution circuit 30, so that The video signal of the field is the same as in the case of interlaced drive.
The pixel electrodes on the odd gate lines and the pixel electrodes on the even gate lines are alternately displayed for each field.

[0022]

As described above, according to the present invention, in the liquid crystal display device corresponding to the interlace drive and the drive circuit thereof, the non-interlace drive is automatically discriminated and the pseudo field inversion signal is generated to generate the odd gate. Since the start pulse for driving the line driver and the even-numbered gate line driver is alternately generated, in the case of non-interlaced driving, no line which is not displayed is not generated, and deterioration of display quality can be prevented. Further, even a single panel having a mosaic pattern color filter array can perform non-interlaced drive display.

Therefore, it is possible to realize a display device capable of displaying a TV image and a monitor such as a personal computer.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a specific circuit diagram of a part of the block shown in FIG.

FIG. 3 is a schematic diagram of a liquid crystal display device.

FIG. 4 is a block diagram showing a conventional technique.

[Explanation of symbols]

 21 Sync Separation Circuit 22 Field Discrimination Circuit 23 VCO 24 H Counter 25 H Decoder 26 Phase Comparison Circuit 27 Switching Circuit 28 Non-Interlace Discrimination Circuit 29 Field Signal Generation Circuit 30 Distribution Circuit 31 V Counter 32 V Decoder

Claims (2)

[Claims] 1. A drive circuit for driving a liquid crystal display device having an odd number gate line driver and an even number gate line driver, distinguishes an odd field and an even field based on a video signal, and outputs a signal indicating the even field and the odd field. Field discriminating means for outputting, and start pulse distributing means for supplying a start pulse to the odd gate line driver in an odd field and a start pulse to the even gate line driver in an even field according to the output of the field discriminating means, Field inversion signal generation means for generating a field inversion signal for each field based on the video signal, non-interlace determination means for determining that the video signal is non-interlaced based on the video signal, and the non-interlace determination Switching means for supplying the field inversion signal to the distributing means by changing the output signal of the field discriminating means according to the signal discriminating non-interlace, and the odd gate line driver and the even gate line even at the time of non-interlacing. A drive circuit for a liquid crystal display device, characterized in that a start pulse is alternately supplied to a driver. 2. The non-interlace discriminating means comprises a first counter and a second counter for counting a vertical synchronizing signal, the first counter being reset by an output signal of the field discriminating means, and a second counter. 2. The liquid crystal according to claim 1, wherein the counter is reset by an inverted signal of the output signal of the field discriminating means, and the output of the predetermined count value of the first counter or the second counter becomes a non-interlace discriminating output. Drive circuit of display device.