JPH07141453A - Multiplier - Google Patents

Abstract

PURPOSE:To widen an input voltage range by driving a cross-connection emitter coupling pair by the differential output current of a cross-connection source coupling pair where linearity is improved. CONSTITUTION:This multiplier has a cross-connection emitter coupling pair 10 making first input voltage V1 an input, a cross-connection source coupling pair 20 making second input voltage V2 the input, and first and second current sources I01 and I02. The cross-connection emitter coupling pair 10 is driven by the differential output current DELTAI of the cross-connection source coupling pair 20. The ratio of the driving current (I01/I02) and the gate width/length ratio {(W/L)1/(W/L)2} of two pairs of source coupling pairs M5 and M6, and M7 and M8 composing the cross-connection source coupling pair 20 are set so as to satisfy a prescribed relation. As a result, the linearity of the MOS differential pair (cross-connection source coupling pair) 20 can be improved and the input voltage range for the second input voltage V2 can be widened. The gate widths/lengths of two pairs of the source M5 and M6, and M7 and M8 can be equalized.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to multipliers,
In particular, the present invention relates to a multiplier formed on a Bi-MOS semiconductor integrated circuit and having a wide input voltage range.

[0002]

2. Description of the Related Art As a conventional Bi-MOS multiplier, a circuit shown in FIG. 8 is known. In FIG.
Bi-MOS multiplier includes a cross connect emitter-coupled pair 10, a first input the input voltage V _1, and a source-coupled pair 20 'to a second input the input voltage V _2, the current source I
and a _o, cross connected emitter-coupled pair 10 is driven by the differential output current ΔI of the source-coupled pair 20 '.

More specifically, the cross-coupled emitter-coupled pair 10 outputs the differential output current ΔI _OUT with the first input terminal pair (11, 12) to which the first input voltage V ₁ is supplied. Output terminal pair (16, 17). The cross-connected emitter coupling pair 10 is a first npn transistor pair (Q ₁ , Q ₂ ) whose emitters are connected to each other.
And a second npn transistor pair (Q ₃ , Q ₄ ). The bases of the npn transistors Q ₁ and Q _{4 and} the bases of the npn transistors Q ₂ and Q ₃ are connected to each other, and the input terminals 11 and 1 are respectively connected.
Connected to 2. In addition, the collectors of the npn transistors Q ₁ and Q ₃ and the npn transistors Q ₂ and Q 3
_{The four} collectors are connected to each other and to the output terminals 16 and 17, respectively.

Source-coupled pair 20 'has a second input voltage V ₂
Is supplied to the second input terminal pair (21, 22). Source-coupled pair 20 'has n-channel MOS transistor pair having a source are connected to each other (M _5, M _6). The gates of n-channel MOS transistors M ₅ and M ₆ are connected to input terminals 21 and 22, respectively. n-channel MOS transistors M ₅ and M ₆
Drains of the first npn transistor pair (Q
₁ and Q ₂ ) and the emitter of the second npn transistor pair (Q ₃ , Q ₄ ). The source of the n-channel MOS transistor pair (M ₅ , M ₆ ) is connected to the current source I _o . With this configuration,
The cross-coupled emitter-coupled pair 10 is driven by the differential output current ΔI of the source-coupled pair 20 '.

The differential output current ΔI _OUT of the Bi-MOS multiplier having such a structure is expressed by the following mathematical formula 3.

[0006]

[Equation 3]

Where V _T is a thermal voltage and V _T = kT
/ Q. Here, k is the Boltzmann constant, T is the absolute temperature, and q is the unit electronic charge. Further, α _Fn is the current amplification factor of the npn transistor. Also, β = μ (C _ox /
2) (W / L) is a transconductance parameter, μ is an effective mobility of carriers, C _ox is a gate oxide film capacitance per unit area, and W and L are a gate width and a gate length, respectively.

From Equation 3 above, in the cross-coupled emitter-coupled pair 10, the non-linearity shows that the first input voltage V ₁ is V ₁
= 2V _T , the value becomes −7.6%, and the first input voltage V ₁
The input voltage range for is limited to | V ₁ | <2V _T. On the other hand, the input voltage range for the second input voltage V ₂ of the source coupling pair 20 ′ is determined by the quotient of the value of the drive current I _o and the transconductance parameter β, and the input voltage range for the second input voltage V ₂ is , | V ₂ | <0.5√
At ((2I _o ) / β), the non-linearity is 7% or less.

Further, the following are known as prior art. Japanese Unexamined Patent Publication (Kokai) No. 60-146371 (hereinafter referred to as "prior art 1") discloses a "CMOS analog multiplication circuit" having a wide dynamic range by using a MOSFET. In the disclosed CMOS analog multiplication circuit, two MOSFETs in which MOSFETs are connected in a differential type are used.
T is connected in parallel to the gate electrode in two stages. For the commonly connected sources of each differential pair,
It has the same number or a single constant current suction circuit. On the drain side of the differential pair, other MOSFETs whose gate electrodes are not connected in common are connected to each other, and two loads are provided between the MOSFET and the power supply. Further, the base potentials of the MOSFETs connected in the differential type are connected to each other and taken out for each differential type MOSFET, and the base potential and the above-mentioned gate electrode are not used as a signal input and the differential type M is used.
The drain of the OSFET is used as the output.

The following prior art is known to be similar to the present invention. Japanese Unexamined Patent Publication No. 61-105912 (hereinafter referred to as "prior art 2") realizes an integrated circuit by providing a differential amplifier circuit that amplifies an input signal and differentially inputs it to a double-balanced multiplication circuit. As well as making it easier
A "mixer circuit" that can obtain a sufficient conversion gain even when the amplitude of an input signal is small is disclosed. Also,
JP-A-3-4615 (hereinafter referred to as prior art 3)
By inserting an emitter resistor into the transistors of the first and second differential amplifier circuits of the two differential amplifier circuits constituting the circuit, the linear portion of the input-to-output characteristic is expanded. A "multiplier circuit" for improving the extraction efficiency of clock frequency components is disclosed. JP-A-3-75977
Japanese Patent Publication (hereinafter referred to as “prior art 4”) discloses that two differential amplifier circuits having the same current value of a constant current source are provided at the input stage of a multiplication circuit, and the respective load resistance outputs are multiplied through an emitter follower. , A "multiplication circuit" capable of efficiently obtaining a squared output even if a difference occurs in the DC bias between the positive phase input and the negative phase input.

[0011]

As described above, in the conventional Bi-MOS multiplier, it is necessary to increase the drive current in order to widen the input voltage range.

An object of the present invention is to provide a Bi-MOS multiplier having an expanded input voltage range.

The above-mentioned prior art 1 is a CMOS analog multiplication circuit composed of MOSFETs, and its object is different from the Bi-MOS multiplier relating to the combination of the bipolar transistor and the MOS transistor as in the present invention. . Further, each of the prior arts 2 to 4 only discloses a circuit constituted by only bipolar transistors, which is different from the Bi-MOS multiplier which is the object of the present invention.

[0014]

In the Bi-MOS multiplier of the present invention, the cross-coupled emitter coupled pair is driven by the differential output current of the cross-coupled source coupled pair with improved linearity.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, a Bi-MOS multiplier according to a first embodiment of the present invention includes a cross-connected emitter-coupled pair 10 having a _first input voltage V ₁ as an input and a second.
Cross-coupled source-coupled pair 20 with input voltage V ₂ of
And a first and second current source I _o1 and I _o2 , the cross-coupled emitter coupled pair 10 being a cross-coupled source coupled pair 20.
Driven by the differential output current ΔI of

Since the cross-connected emitter coupling pair 10 has the same structure as that shown in FIG. 8, its description will be omitted.

The cross-connect source-coupled pairs 20 are respectively
A first n-channel MOS transistor pair (M ₅ , M ₆ ) having sources connected to each other and a second n-channel MOS transistor
A transistor pair (M ₇ , M ₈ ). The gates of n-channel MOS transistors M ₅ and M ₇ and n
The gates of the channel MOS transistors M ₆ and M ₈ are connected to each other, and the input terminals 2
1 and 22. Also, n channel M
The drains of the OS transistors M ₅ and M _{8 and} the drains of the n-channel MOS transistors M ₆ and M ₇ are connected to each other, and each has a first np
n-transistor pair (Q ₁ , Q ₂ ) emitter and second
Is connected to the emitters of the npn transistor pair (Q ₃ , Q ₄ ). The source of the first n-channel MOS transistor pair (M ₅ , M ₆ ) is connected to the first current source I _o1 , and the second n-channel MOS transistor pair (M ₇ ,
The source of M ₈ ) is connected to the second current source I _o2 .
With such a configuration, the cross-coupled emitter coupled pair 10 is driven by the differential output current ΔI of the cross-coupled source coupled pair 20.

The differential output current ΔI of the cross-connection source-coupled pair 20 is expressed by the following equation 4 if the input voltage range for the second input voltage V ₂ is limited.

[0020]

[Equation 4]

Here, β ₁ and β ₂ are the first and second n-channel MOS transistor pairs (M
₅ , M ₆ ) and (M ₇ , M ₈ ) transconductance parameters. The above formula 4 is approximated by the following formula 5.

[0022]

[Equation 5]

In order for the differential output current ΔI of the cross-coupled source coupling pair 20 to be a straight line with respect to the second input voltage V _{2 according} to the approximate expression shown in the above equation 5, the following equation 6 is obviously used. It is necessary to be satisfied.

[0024]

[Equation 6]

That is, the above equation 6 can be rewritten as the following equation 7.

[0026]

[Equation 7]

Here, (W / L) ₁ and (W / L) ₂
Are gate width / length ratios of the first and second n-channel MOS transistor pairs (M ₅ , M ₆ ) and (M ₇ , M ₈ ), respectively. It should be noted that the approximation formula shown in Formula 5 above is a very good approximation formula of Formula 4 with little approximation error.

FIG. 2 shows the input / output characteristics of the MOS differential pair (cross connection source coupling pair) 20 thus realized. Therefore, the gate width / length ratio (I _o1 / I _o2 ) of the drive currents of the two source coupled pairs (M ₅ , M ₆ ) and (M ₇ , M ₈ ) forming the cross-connected source coupled pair 20 and the gate width / length ratio. {(W /
L) ₁ / (W / L) ₂ } is set so as to satisfy the above formula 7, the MOS differential pair (cross connection source coupling pair) 2
The linearity of 0 can be improved, and the input voltage range for the second input voltage V ₂ can be expanded.

Further, two pairs of source coupling pairs (M ₅ , M ₆ ) and (M ₇ , M which constitute the cross connection source coupling pair 20 are formed.
It is also possible to make the gate width / length (W / L) ₁ and (W / L) ₂ of ₈ ) equal.

Referring to FIG. 3, in the Bi-MOS multiplier according to the second embodiment of the present invention, instead of the cross-connection source coupling pair 20, a resistance-divided cross-connection source coupling pair 20a is used as described later. It has the same configuration as that shown in FIG. 1 except that it is used. Therefore, FIG.
Elements having the same functions as those of the constituent elements in 1 are assigned the same reference numerals, and only different points will be described below.

The cross-connection source coupling pair 20a is divided by resistance to form two source coupling pairs (M ₅ ,
M ₆₎ and is changing the input voltage to the (M _7, M _8). More specifically, a resistor R is provided between the gates of the n-channel MOS transistors M ₅ and M ₇ and between the gates of the n-channel MOS transistors M ₆ and M _8.
1 and R ₁ are connected. Also, n channel M
A resistor R ₂ is connected between the gates of the OS transistors M ₇ and M ₈ . Here, when the resistance voltage dividing ratio is set as c, it is obtained by the following formula 8.

[0032]

[Equation 8]

The differential output current ΔI of the cross-coupled source coupling pair 20a at this time is expressed by the following formula 9 if the input voltage range for the second input voltage V ₂ is limited.

[0034]

[Equation 9]

The above equation 9 is approximated by the following equation 10.

[0036]

[Equation 10]

Therefore, the differential output current ΔI of the cross-coupled source coupling pair 20a can be calculated by the approximate expression shown in the above mathematical expression 10.
In order to be linear with respect to the second input voltage V ₂ , it is obviously necessary to satisfy the following formula 11.

[0038]

[Equation 11]

That is, the resistance division ratio c is the first value shown in FIG.
₂ and the transconductance parameter ratio (β ₁ / β ₂ ) in the above embodiment, the second embodiment shown in FIG. 3 is the same as the first embodiment shown in FIG. Are equivalent.

[0040]

[Equation 12]

The present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications / variations can be made without departing from the gist of the present invention. For example, in the above embodiment, the cross-coupled emitter coupled pair 10 is composed of npn transistors Q ₁ , Q ₂ , Q ₃ and Q ₄ , and the cross-coupled source coupled pair 20.
And 20a are n-channel MOS transistors M ₅ ,
Although it is composed of M ₆ , M ₇ , and M ₈ , as shown in FIGS. 4 and 5, the cross-connected emitter coupled pair 10A is a pnp transistor Q _1a , Q _2a , Q _3a , Q _4a , and a cross-connected source. Similar characteristics can be obtained even if the coupling pair 20A and 20Aa is constituted by p-channel MOS transistors M _5a , M _6a , M _7a and M _8a . Also, as shown in FIG. 6 or 7,
Equivalent characteristics can be obtained even if only the cross-coupled source-coupled pair is replaced with the p-channel MOS transistor from the n-channel MOS transistor. In this case, low voltage operation is possible, but the circuit current is tripled. Further, although not shown, only the cross-coupled emitter coupled pair may be replaced with the pnp transistor from the npn transistor.

[0042]

As described above, the Bi-M of the present invention is used.
The OS multiplier has the effect of expanding the input voltage range.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a Bi-MOS multiplier according to a first embodiment of the present invention.

FIG. 2 is an input / output characteristic diagram of a cross-coupled source pair forming the Bi-MOS multiplier shown in FIG.

FIG. 3 is a circuit diagram showing a Bi-MOS multiplier according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a modified example of the Bi-MOS multiplier according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a modified example of the Bi-MOS multiplier according to the second embodiment of the present invention.

FIG. 6 is a circuit diagram showing another modification of the Bi-MOS multiplier according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing another modification of the Bi-MOS multiplier according to the second embodiment of the present invention.

FIG. 8 is a circuit diagram showing a conventional Bi-MOS multiplier.

[Explanation of symbols]

10,10A Cross-connected emitter coupled pair 20,20a, 20A, 20Aa Cross-connected source coupled pair

Claims (2)

[Claims] 1. A multiplier in which a cross-connected emitter-coupled pair having a first input signal as an input is driven by a differential output current of a cross-connected source-coupled pair having a second input signal as an input. The drive currents I _o1 and I _{o2 of the} two source-coupled pairs forming the connected source-coupled pair and the gate width / length ratio (W /
L) ₁ and (W / L) ₂ are approximately the following formula 1 Multiplier characterized by being represented by. 2. A multiplier in which a cross-connected emitter-coupled pair having a first input signal as an input is driven by a differential output current of a cross-connected source-coupled pair having a second input signal as an input. One of the two source-coupled pairs forming the connected source-coupled pair is divided and applied, and the two drive currents I
The relationship between _o1 and I _o2 and the partial pressure ratio c is approximately the following Equation 2 Multiplier characterized by being represented by.