JPH07135312A - Semiconductor device and its fabrication - Google Patents

Abstract

PURPOSE:To provide a semiconductor device, and its fabrication having such structure as the drain is provided with an offset part in which the offset part can be controlled in any way and the current capacity is enhanced while allowing fine patterning by allowing easy control of pinch-off voltage at the offset part. CONSTITUTION:(1). The semiconductor device having such structure as the drain 2a provided with an offset part 3a is provided with a potential applying part (a metal electrode formed simultaneously with a poly-Si electrode 4 or an upper layer metallization) for controlling at least the drain side offset part. (2). The method for fabricating the semiconductor device comprises a step for covering at least the drain side offset part 3a and the gate electrode 5 with a material for forming the potential applying part, and a step for patterning the material to provide a potential applying part 4 for controlling at least the drain side offset part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. In particular, the present invention relates to a semiconductor device having a drain with an offset portion and a method for manufacturing the same. INDUSTRIAL APPLICABILITY The present invention can be used, for example, as a technique related to an LDD offset type high breakdown voltage transistor.

[0002]

2. Description of the Related Art A conventional transistor structure of this type is shown in FIG.
Shown in. A gate electrode 5 is formed on a substrate 1, low-concentration impurity diffusion regions forming offset portions 3a and 3b are formed below the gate electrode 5, and high-concentration impurity diffusion regions forming source / drain regions 2b and 2a. Are formed. Reference numeral 6 is a gate insulating film, and 7 is a LOC for element isolation.
This is the OS area.

The conventional semiconductor device having such a structure in which the drain has an offset portion has the following problems.

Generally, in the conventional high breakdown voltage transistor, the gate insulating film 6 is formed by the voltage applied from the drain.
Since a high electric field is applied to the gate insulating film 6, the gate insulating film 6 is thickened and the concentration of the offset portion 3a is lowered to sacrifice the current capability.

In the prior art, the extension of the depletion layer of the offset portion 3a (extension from the well) is controlled similarly to the gate voltage. According to this, when used as an open drain (for example, when used as a switching transistor), the extension of the depletion layer in the offset portion at the time of turning off can be controlled, but since the gate insulating film 6 is thick as described above, the controllability is reduced. Is not that high. Further, in the case of using a normal usage method other than the open drain, this control method could not be used because the gate voltage and the portion (generally a polysilicon portion) for controlling the offset portion are the same.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and enables a semiconductor device having a structure in which the drain has an offset portion to control the offset portion irrespective of the usage and pinch off the offset portion. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the semiconductor device, which can easily control the voltage to improve the current capability and can be miniaturized.

[0007]

According to the invention of claim 1 of the present application, in a semiconductor device having a structure in which a drain is provided with an offset portion, at least a potential applying portion for controlling a drain side offset portion is provided. It is a device.

According to this invention, the potential applying section is provided,
For example, the gate electrode and the offset part are covered with a polysilicon electrode, or a metal electrode is provided on the offset part, and this electrode is used as a potential applying part. For example, a bias is applied to this potential applying part by turning on or off a transistor. Alternatively, the pinch-off voltage of the offset portion can be controlled by not applying or applying the voltage. This makes it possible to improve the current capacity.

According to the present invention, the current capability is improved by making it easier to pinch off the offset portion,
A high-performance transistor can be formed without increasing the width and the thickness, and the cell size of the semiconductor device can be reduced.

The invention according to claim 2 of the present invention is the semiconductor device according to claim 1, wherein the potential applying portion is a poly-Si electrode formed of poly-Si.

According to the present invention, the above-mentioned potential application control can be realized by poly-Si which is excellent as a conductive material for control, by the usual general method by the poly-Si processing technique similar to that used for forming the gate electrode. .

A third aspect of the present invention is the semiconductor device according to the first aspect, wherein the potential applying portion is a metal electrode formed at the same time as the upper metal wiring.

According to the present invention, the potential applying portion can be formed at the same time when the metal wiring such as the Al wiring is formed in the upper layer.

According to a fourth aspect of the present invention, in a method of manufacturing a semiconductor device having a structure in which a drain is provided with an offset portion, a potential applying portion forming material is provided so as to cover at least the drain side offset portion and the gate electrode, and the potential is applied. It is a method of manufacturing a semiconductor device, in which a material for forming an applied portion is patterned to obtain a semiconductor device having at least a potential applying portion for controlling a drain side offset portion.

According to the present invention, the semiconductor device of the present invention can be efficiently manufactured.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a source / drain and each having an offset portion, wherein a potential applying portion forming material is formed on the gate electrode and each offset portion. The method of manufacturing a semiconductor device according to claim 4, wherein the source / drain is formed by using this as a mask.

According to the present invention, the source / drain can be formed in self-alignment by using the potential applying portion as a mask.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. However, as a matter of course, the present invention is not limited to the following examples.

Example 1 In this example, the present invention is embodied in a finely integrated CCD high withstand voltage CMOS.

The transistor structure of this embodiment is shown in FIG. As shown in the figure, in this embodiment, in the semiconductor device having the structure in which the drain 2a is provided with the offset portion 3a, at least the potential applying portion 4 for controlling the drain side offset portion 3a is used.
Is a semiconductor device provided with.

In this embodiment, the source 2b and the drain 2
The potential applying section 4 is formed so as to extend over both the offset sections 3b and 3a, which are the low-concentration impurity diffusion regions on the a side. This potential applying section 4 acts on the drain side offset section 3a, but the source / drain may be reversed depending on the circuit.

In this embodiment, the potential applying section 4 is made of poly-Si.
It is composed of a poly-Si electrode formed by.

In FIG. 1, reference numeral 1 is a substrate (Si substrate), 5 is a gate electrode (poly Si gate electrode), 6 is a gate insulating film (SiO ₂ which is a gate oxide film), and 6a is an insulating film (Si).
O ₂ film) Thin film, 7 is a LOCOS region for element isolation (SiO 2
₂ )

In the structure of the present embodiment, poly-Si is applied from the offset portion 3b on the source 2b side to the gate electrode 5 portion and further to the offset portion 3b on the drain side to form the potential applying portion 4, and the potential applying portion 4 is used for the transistor operation. Accordingly, by applying a bias, the voltage applied to the end of the gate electrode 5 can be controlled to a low level, so that the gate insulating film 6 can be thinned and pinch off even when the concentration of the offset portions 3a and 3b is relatively high. Therefore, as a result of these, it is possible to improve the current capability when the transistor is turned on.

Further, also in the case of using other than the open drain in which a voltage is applied to the drain to serve as a switching transistor, the poly-Si potential applying section 4 is used for the terminal so that the depletion layer of the offset is hard to extend when the gate is turned on. It can be controlled, which leads to improvement of current capacity.

The transistor of this example was manufactured by the following manufacturing process. As a result, the source / drain are formed in self-alignment. 2 to 5
Refer to.

That is, in this embodiment, at least the drain-side offset portion 3a is provided with a potential-application portion forming material, and the potential-application portion forming material is patterned.
The potential applying section 4 for controlling a is provided to obtain a semiconductor device.

Hereinafter, this step will be described in detail. As shown in FIG. 2, the SiO ₂ insulating film 6 is formed on the Si substrate 1.
b is formed, the element isolation region 7 is formed, and poly-Si is patterned to form the gate electrode 5.

After the element isolation region 7 and the gate electrode 5 are formed, offset ion implantation I is performed (FIG. 3).

Next, after forming sidewalls by forming a film of SiO ₂ or the like and etching back, an insulating film 9 is formed on the gate electrode 5. Here, oxide film-nitride film-oxide film (Si
This insulating film 9 is formed by a so-called ONO film having a laminated structure of O ₂ / SiN / SiO ₂ ) or by a CVD oxide film.
Was formed.

After that, the oxide film on the offset portions 3a and 3b is made thinner than the gate insulating film 5 to form a SiO ₂ thin film 6a by utilizing the over-etched portion at the time of forming the sidewalls, and then a polycrystal is used as a material for forming a potential applying portion. A film of Si is formed and is patterned as shown in FIG. At this time, Poly S
The edge of i (potential application unit 4) covers the JFET (corresponding to the gate) used as the electric field relaxation layer (FIG. 4).

Next, using this poly-Si (potential applying portion 4) as a mask, source / drain ion implantation II is performed by self-alignment as shown in FIG.

After that, source / drain oxidation is performed,
The transistor structure shown in FIG. 1 is completed.

The poly-Si covering the gate electrode 5 (gate poly-Si) is used as the potential applying portion 4 based on the usage of an open drain or other high breakdown voltage transistor.
Biasing is performed according to N and OFF. For example, the usage is such that when the transistor is OFF, the offset unit 3a
In order to relax the electric field applied to the gate electrode 5 by extending the depletion layer, the potential applying section 4 is biased to 0 V to facilitate pinch-off. On the other hand, when the transistor is ON, the potential applying section 4 is biased to 5 V, for example, to make it difficult to pinch off and reduce the source / drain resistance.

Conventionally, only the control from the well side was possible and the controllability was limited. However, according to this embodiment, the pinch-off voltage can be controlled well in various cases.

Example 2 This example is shown in FIG. In this embodiment, the potential applying section 4
A is a metal electrode formed at the same time as the upper layer metal wiring. Here, when the Al wiring was formed on the interlayer film 8, the metal electrode 4A was formed of Al.

According to this embodiment, the same controllability as that of the transistor of the first embodiment can be obtained. Further, the potential applying portion 4 can be formed simultaneously with the formation of the metal wiring, which is advantageous in the process.

[0038]

According to the present invention, in a semiconductor device having a structure in which a drain has an offset portion, the offset portion can be controlled irrespective of usage, and the pinch-off voltage of the offset portion can be easily controlled to obtain a current capability. It has been possible to provide a semiconductor device and a method for manufacturing a semiconductor device, which are capable of improving the above-mentioned characteristics and also capable of achieving miniaturization.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the structure of Example 1.

2A to 2C are sectional views showing steps of Example 1 in order (1).

3A to 3C are sectional views showing the steps of Example 1 in order (2).

4A to 4C are sectional views showing the steps of Example 1 in order (3).

5A to 5C are sectional views showing steps of Example 1 in order (4).

FIG. 6 is a cross-sectional view showing the structure of Example 2.

FIG. 7 is a cross-sectional view showing a conventional technique.

[Explanation of symbols]

 1 Substrate 2a Drain 2b Source 3a Drain side offset part 3b Source side offset part 4 Potential applying part (poly Si) 4A Potential applying part (metal electrode) 5 Gate electrode 6 Gate insulating film

Claims (5)

[Claims] 1. A semiconductor device having a structure in which a drain is provided with an offset portion, wherein at least a potential applying portion for controlling a drain side offset portion is provided. 2. The semiconductor device according to claim 1, wherein the potential applying section is a poly-Si electrode formed of poly-Si. 3. The semiconductor device according to claim 1, wherein the potential applying section is a metal electrode formed simultaneously with the upper layer metal wiring. 4. A method of manufacturing a semiconductor device having a structure in which a drain is provided with an offset portion, wherein a potential applying portion forming material is provided so as to cover at least the drain side offset portion and the gate electrode, and the potential applying portion forming material is patterned. A method for manufacturing a semiconductor device, wherein a semiconductor device having at least a potential applying portion for controlling a drain side offset portion is provided. 5. A method of manufacturing a semiconductor device having a source / drain, each having an offset portion, wherein a material for forming a potential applying portion is formed on a gate electrode and each offset portion, and a source / drain is used as a mask. The method for manufacturing a semiconductor device according to claim 4, wherein a drain is formed.