JPH1154759A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce parasitic capacitance of a source and drain diffusion layers with a body or gate sharply, and to improve the switching characteristic of a circuit, by forming the pattern of the gate electrode in lin. SOLUTION: On a semiconductor substrate 1, a silicon layer insulated and separated by a silicon oxide film 2 and an element separating insulating film 3 exists, and on the silicon layer a gate electrode 5 is formed with a gate insulating film 4 between. Besides, in the silicon layer, a source and a drain diffusion layers 6 and a strap contact 8 to a body and the gate are formed. In this way, a gate-body short-circuited SOI-MOSFET with a body contact is constituted. And a gate electrode 5 is formed linearly so that the width in the direction of its channel width may be approximately equal, i.e., formed into an I shape. Consequently, it becomes possible to ignore parasitic capacitance of the course and drain layers with the silicon layer principally, and to improve the switching characteristic of a circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a MOS field effect transistor using an SOI (Silicon On Insulator) and a method of manufacturing the same.

[0002]

2. Description of the Related Art A MOS field effect transistor (hereinafter referred to as "SO") having a channel as a surface of a semiconductor thin film made of silicon or the like formed on silicon oxide or the like as an insulator.
An I-MOSFET is more resistant to short-channel effects and has a smaller parasitic junction capacitance (sometimes simply referred to as “parasitic capacitance”) than a bulk MOSFET having a silicon substrate surface as a channel. There are advantages such as a higher switching speed. However, in general, a body (in a thin-film SOI-MOSFET, an element region in which individual channels are formed is separated, and this is called a “body”). However, in this case, there is a disadvantage that the majority carriers generated by impact ionization of the carriers in the channel at the drain end accumulate in the body and the body potential fluctuates. As a result, the characteristics of the SOI-MOSFET fluctuate.

On the other hand, in a SOI-MOSFET with a body contact in which an electrode for applying a potential to a body is formed, majority carriers are pulled out from the body electrode and the potential of the body is stabilized, so that a problem of the so-called substrate floating effect occurs. Absent. In addition, the body potential is dynamically controlled by a structure in which the body electrode is short-circuited with the gate electrode (hereinafter, referred to as “gate-body short-circuit type”), so that the threshold value at the time of ON is lowered and the drain voltage is reduced. Since the leakage current can be reduced by increasing the current and increasing the off-state threshold value, the switching characteristics can be significantly improved as compared with the conventional case.

FIG. 9 shows a typical SO with body contact.
It is a figure which shows an I-MOSFET (in the case of n-type MOS), (a) is a top view, (b)-(e) respectively,
(A) 9B-9B sectional view, 9C-9C sectional view, 9D-
It is a 9D sectional view and a 9E-9E sectional view. In FIG. 9, the contact to the source / drain 6 is omitted, and FIG. 9 shows a state where the contact 8 'on the gate 5 and the body 3 is opened. For example, thereafter, by short-circuiting both contact portions with the same wiring, a gate-body short-circuit type is obtained.

However, in an SOI-MOSFET with a body contact as shown in FIG. 9, the gate electrode is made H-type to separate the source / drain region from the body extraction region from the channel portion. Therefore, in the region indicated by the dotted line in the plane pattern, the parasitic capacitance 1 such as the junction capacitance between the source / drain and the body region or the overlap capacitance between the source / drain region and the gate is increased. Sufficient performance can be obtained by increasing the gate capacitance by the increase in the area of the gate electrode, or by the parasitic resistance from the body region under the channel to the contact formation region to the body region, etc. I could not do it.

[0006]

As described above, conventionally, the performance of the transistor cannot be sufficiently brought out due to an increase in the parasitic capacitance between the source / drain region and the gate. The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device in which switching characteristics are improved and deterioration in element characteristics due to potential drop or potential delay is reduced. .

[0007]

According to the present invention, the following means have been taken in order to solve the above-mentioned problems. In the present invention,
This is for reducing the parasitic capacitance and the parasitic resistance of the SOI-MOSFET with a body contact, and is characterized by the following points. (1) The pattern of the gate electrode is linear I-shaped. In this way, by making the gate electrode straight,
In principle, the parasitic capacitance 1 between the source / drain diffusion layer and the body or gate is eliminated, the parasitic capacitance is greatly reduced, and the switching characteristics of the circuit are improved. (2) The thickness of the gate insulating film in the body lead-out region for forming the body contact is made larger than the thickness of the gate insulating film in the body region that functions as a channel.
As described above, by increasing the thickness of the gate insulating film in the body lead-out region, the gate capacitance is reduced, and the switching characteristics of the circuit are improved. (3) The sheet resistance of the body in the body extraction region is made lower than the sheet resistance of the body in the body region that functions as a channel. As described above, by selectively lowering the sheet resistance by increasing the impurity concentration of the body lead-out region body and improving the controllability of the body potential, deterioration of element characteristics due to potential drop and potential delay can be prevented. Can be reduced.

[0008]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an n-channel type, particularly a MOAT type S, as a semiconductor device according to a first embodiment of the present invention.
It is a figure which shows an OI-MOSFET, (a) is a top view, (b)-(e) is 1B-1B sectional drawing, 1C-1C sectional drawing, 1D-1D sectional drawing and 1E of (a) which are respectively. −
It is 1E sectional drawing.

On a semiconductor substrate (underlying silicon wafer) 1, there is provided a silicon layer 3 '(hereinafter also referred to as "body region") which is insulated and separated by a silicon oxide film 2 and an isolation insulating film 3. A gate electrode 5 is formed on 3 'with a gate insulating film 4 interposed therebetween. In the silicon layer 3 ', a source / drain diffusion layer 6 and a strap contact 8 to a body and a gate are formed. Thus, an SOI-MOSFET (n-type MOS) with a gate-body short-circuit type body contact is configured.

In the present embodiment, the gate electrode 5 has a linear shape (that is, a linear shape so that the width in the channel width direction is substantially constant).
I-type). Conventionally, since the shape of the gate electrode was H-type, parasitic capacitance was a problem as shown in FIG. 9, but as in the present embodiment, the shape of the gate electrode 5 was changed to I-type. Source / drain diffusion layer 6
And the parasitic capacitance between the silicon layer 3 'and the silicon layer 3' can be ignored in principle.

Although the method of manufacturing the semiconductor device according to the present embodiment may be the same as the conventional method, the method of manufacturing the semiconductor device according to the present embodiment will be briefly described below. For example, first, individual element regions for forming elements are formed by the LOCOS method, the STI method, or the like. Then, if necessary,
Boron is introduced into the silicon layer 3 'as a channel impurity for controlling the threshold value of the transistor by ion implantation or the like. Subsequently, a gate insulating film 4 is formed on the silicon layer 3 'by oxidation or the like, and an I-type gate electrode 5 made of n-type polycrystalline silicon or a composite film thereof is formed thereon. Then, using this gate electrode 5 as a mask,
The source / drain diffusion layer 6 is formed in the silicon layer 3 'by ion implantation or the like, and a p + diffusion layer is formed in the body contact formation portion as necessary. In this case, the source / drain diffusion layer 6 and the p ⁺ diffusion layer are the same as those in FIG.
As can be seen from (a), it is desirable to form them separately via an eddy impurity concentration (p layer in the figure) so as not to form a direct junction. Finally, the interlayer insulating film 7, the body contact 8, and the wiring (not shown) are formed to complete the main part of the device.

In the above embodiment, the body contact 8 is a strap contact. By forming the contact in this manner, the contact with the body region can be reduced to a minimum pattern (minimum design rule).
Can be formed. In FIG. 1, two body contacts 8 are provided. However, if the delay of the body potential is not a problem, this is not necessary and only one contact may be used.

FIGS. 2A and 2B are diagrams showing an n-channel SOI-MOSFET as a semiconductor device according to a second embodiment of the present invention, wherein FIG. 2A is a plan view, and FIGS. 2A-2B sectional view, 2C-2C sectional view, 2D-2D sectional view, and 2E-2E sectional view of (a). In the present embodiment, in the first embodiment, the gate insulating film 4 'in the body potential extraction region is formed thicker than the gate insulating film 4 in the channel portion. As in the present embodiment, making the gate insulating film 4 ′ in the body potential extracting region thicker than the gate insulating film 4 in the channel portion is performed after selectively depositing, oxidizing, or forming a groove in this portion in advance. This can be easily realized by forming a thick insulating film such as a silicon oxide film by burying. in this way,
By making the gate insulating film 4 'in the body potential extracting region thicker than the gate insulating film 4 in the channel portion, the parasitic capacitance in the body potential extracting region can be reduced. FIG.
In the above, the shape of the gate electrode 5 is the I-type as in the first embodiment, but the parasitic capacitance can be reduced even if the shape is the H-type as in the related art.

Referring to FIG. 3, a description will be given of a method of forming a gate tip as a method of manufacturing the semiconductor device of FIG. First, a silicon oxide film layer formed by volume or oxidation is selectively left by a photoresist. MOAT method, STI method for forming a groove and burying a silicon oxide film, LOCOS method
A thick silicon oxide film 4 'is formed by a method or the like (FIG. 3
(A)). Next, ions are implanted into the lower portion of the silicon oxide film 4 'and the channel portion to lower the resistance of the body potential extraction region, adjust the threshold value of the channel portion, and the like. Subsequently, a gate oxide film 4 is formed, and a gate electrode 5 is formed thereon (FIG. 3B). Above the gate electrode,
A structure in which silicon dust and silicon oxide films are stacked. In this manner, the gate electrode can be protected from dry etching of silicon used in processing the element region in a later step. Subsequently, as shown in FIG. 3C, after the source / drain diffusion layer 6 is formed, the element is completed by performing mesa-type element isolation. In this case, after forming the gate electrode, first LDDn ^- after the formation of the diffusion layer, and a silicon oxide film or a silicon nitride film is formed so as to leave the sidewalls of the gate electrode of the gate electrode, n ⁺ diffusion layer of the source and drain formation I do. As a method for forming the LDDn ⁻ diffusion layer and the source / drain n ⁺ diffusion layer, conventional ion implantation is performed using a photoresist having a pattern that at least surrounds a region to be an element region later.

Thereafter, dry etching for selectively etching silicon is performed in a state where the surface of the silicon substrate other than the gate electrode 5 and the thick silicon oxide film 4 'is exposed, thereby forming an element region. I do. At this time,
The pattern of the photoresist for forming the element region is, for example, as shown by oblique lines in FIG. 3D and 3E are 3D-3 in FIG. 3C, respectively.
D, 3E-3E sectional drawing. As a result, the gate electrode 5 whose periphery is covered with a silicon oxide film or a silicon nitride film is formed.
The silicon substrate other than the region where the OR of the silicon oxide film 4 'and the pattern of the present photoresist is ORed is etched, and the element region shown by the bold line in FIG. In this case, in FIG. 2, the body contact 8 is formed.
You don't have to. Further, in FIG. 3B, the gate is straight, but the gate is not limited to a straight shape, and may be any shape. That is, the present invention can be applied to an SOI element of a type using a normal body in a floating state.

As described above, according to the gate forming method in which the gate electrode is formed before the element isolation, the problem of deteriorating the element characteristics of the mesa isolation which is the simplest conventional isolation method can be solved. And simple and high-performance element isolation can be achieved. Specifically, FIG. 4 (FIGS. 4 (b) and 4 (c) show 4B-4B and 4C of FIG.
Conventionally, as shown in FIG. 4C, the problem of gate breakdown at the upper corner portion of the silicon layer edge, the problem of leakage of the parasitic transistor, the problem of remaining gate material due to the step in the silicon layer, and the like are conventionally produced. According to the method, since the silicon layer serving as the element region is processed after the gate is formed, the above-mentioned problems relating to corners and steps of the silicon layer and the gate electrode do not occur at all. In particular, MOAT
In the mold, since the thickness of the lower silicon layer can be ensured, the transmission of the body potential is improved, and stable element characteristics can be obtained.

Further, by applying this manufacturing method, a transistor with a capacitor can be easily manufactured. Particularly effective in this case is that the capacitor region can be formed in a self-alignment manner with respect to the gate electrode, and thus it can be said that this is an effective process for miniaturization of elements. Conventionally, an element region serving as a capacitor is formed in advance, and the region is covered with a gate electrode having a large pattern that overlaps the element region.
Miniaturization was difficult. FIG. 5A shows a plan view thereof, and FIG. 5B shows an equalizing circuit thereof. The method for manufacturing the element shown in FIG. 5 is the same as that shown in FIG. 3, and thus a detailed description is omitted. 6 (FIGS. 6 (b) and 6 (c) show 6B-6B and 6C of FIG. 6 (a), respectively, as a normal SOI-MOSFET without forming a contact to the body.
As shown in (-6C cross-sectional view), a thick gate insulating film formed first is not always necessary. After channel ion implantation, that is, a gate electrode is formed immediately, and the device region is etched using the gate electrode and a photoresist (shaded line) as shown in the figure as a mask. When isotropic dry etching is used as the etching method at this time, when the gate length is small, the silicon layer used as the gate electrode in a region deviated from the photoresist pattern is also removed by etching, so that extra parasitic capacitance can be reduced.

As a method of reducing the resistance of the body region of the body potential extracting region, the present invention (see FIG. 2)
The structure of the thick gate insulating film 4 'as described above is effective. The reason is as follows. Since the threshold value of the channel portion increases, the impurity concentration especially near the surface cannot be increased. Therefore, when the impurity is ion-implanted, it is necessary to make the peak concentration deep near the interface with the silicon oxide film 2. At this time, since the gate insulating film 4 'in the body lead-out region is thick, the peak depth of this portion can be set shallow near the center of the thin silicon layer. In this case, in the deep channel portion, many impurities are trapped in the underlying silicon oxide film, whereas
In the case of the body potential extraction region, since most of the region is introduced into the body region, the concentration becomes high and the sheet resistance can be reduced. In this case, when the thickness of the gate insulating film 4 'is large, as shown in FIG. 7A, almost all ions are implanted into the body potential extracting region into the gate insulating film 4'. In such a case, as shown in FIG. 7B, by separately performing ion implantation at a depth to be implanted into the silicon layer below the gate insulating film 4 ', the channel portion passes through this time, and the threshold is passed. The body resistance can be reduced without affecting the value.

FIGS. 8A and 8B are views showing a semiconductor device according to a third embodiment of the present invention, wherein FIG. 8A is a plan view, and FIGS.
(E) is a 3B-3B sectional view of (a), and 3C-
It is 3C sectional drawing, 3D-3D sectional drawing, and 3E-3E sectional drawing. In the present embodiment, the gate electrode is constituted by a composite film of a first gate electrode 5-1 made of, for example, n-type polycrystalline silicon and a second gate electrode 5-2 made of WSi,
The first gate electrode 5-1 in the body potential extraction region is removed by etching. After that, the interlayer insulating film 7 and the like are
The gate insulating films 4, 4 'in this portion become thicker, for example, by being deposited between the second gate electrode 5-2 and the silicon film. Alternatively, a cavity may be formed due to insufficient coverage of the interlayer insulating film 7 and the like. In this case, a gas having a relative dielectric constant close to 1 becomes a part of the gate insulating film 4 ', so that the capacity reduction effect is further increased. Alternatively, in a further modification, in the embodiment of FIGS.
The gas may be selectively removed by wet etching of F or the like, and a gas may be sealed instead of the gate insulating film. The present invention is not limited to the above embodiments of the present invention, and it is needless to say that various modifications can be made without departing from the spirit of the present invention.

[0020]

According to the present invention, the following effects can be obtained. Since the gate electrode is linear, the parasitic capacitance between the source / drain diffusion layer and the body or the gate is eliminated in principle, the parasitic capacitance is greatly reduced, and the switching characteristics of the circuit are improved.

By increasing the thickness of the gate insulating film in the body lead region, the gate capacitance is reduced, and the switching characteristics of the circuit are improved. By selectively lowering the sheet resistance by, for example, increasing the impurity concentration of the body lead-out region body, and improving the controllability of the body potential, deterioration of element characteristics due to potential drop or potential delay can be reduced.

[Brief description of the drawings]

FIG. 1 is a view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a diagram showing a conventional method for manufacturing a semiconductor device.

FIG. 5 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 9: Typical SOI-MOS with body contact
FIG. 4 is a diagram showing an FET (in the case of an n-type MOS).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate (base silicon wafer) 2 ... Silicon oxide film 3 ... Element isolation insulating film 3 '... Silicon layer (body region) 4, 4' ... Gate insulating film 5 ... Gate electrode 6 ... Source / drain diffusion layer 7 ... Interlayer insulating film 8 ... Strap contact 8 '... Contact to body

Claims (4)

[Claims] A semiconductor substrate; an insulating film formed on the semiconductor substrate; a semiconductor thin film formed on the insulating film; a source diffusion layer and a drain diffusion layer formed in the semiconductor thin film; A semiconductor device, comprising: a field effect transistor including a gate insulating film formed on the semiconductor thin film via an insulating layer; and at least one electrode connected to the gate electrode and applying a potential to the semiconductor thin film; The electrode is elongated on the semiconductor thin film between the source diffusion layer and the drain diffusion layer in a direction perpendicular to the channel length, and is formed so that its width is substantially constant. Semiconductor device. 2. A semiconductor substrate, an insulating film formed on the semiconductor substrate, a semiconductor thin film formed on the insulating film, a source diffusion layer and a drain diffusion layer formed in the semiconductor thin film, A semiconductor device comprising: a field effect transistor including a gate insulating film formed on the semiconductor thin film via an insulating layer; and at least one electrode connected to the gate electrode and applying a potential to the semiconductor thin film, A semiconductor device, wherein the thickness of the gate insulating film in a portion from which the gate insulating film is extracted is larger than the thickness of the gate insulating film in the channel region. 3. A semiconductor substrate, an insulating film formed on the semiconductor substrate, a semiconductor thin film formed on the insulating film, a source diffusion layer and a drain diffusion layer formed in the semiconductor thin film, A semiconductor device comprising: a field effect transistor including a gate insulating film formed on the semiconductor thin film via an insulating layer; and at least one electrode connected to the gate electrode and applying a potential to the semiconductor thin film, A sheet resistance of a body region below the gate in a portion from which the gate is extracted is lower than a sheet resistance of the body region below the gate in the channel region. 4. A method of manufacturing a semiconductor device on a semiconductor thin film substrate formed on an insulating film, wherein a gate electrode is formed on the semiconductor thin film substrate with a gate insulating film interposed therebetween and the periphery thereof covered with the insulating film. And forming a device region by etching and removing the semiconductor thin film using the photoresist pattern defining the gate electrode and the source / drain channel region as a mask. Manufacturing method.