JPH0713195A - Liquid crystal display substrate - Google Patents

Abstract

PURPOSE:To provide the constitution to simplify the man-hours for production. CONSTITUTION:This liquid crystal display substrate has pixel electrodes 80 to which voltages are impressed via thin-film semiconductor elements on gate bus lines 12. The extension parts of the pixel electrodes 80 are superposed on the extension parts of the other gate bus lines 12 adjacent to the gate bus lines 12, by which capacitors Cadd are constituted. The substrate has also protective films PAS formed by exposing the effective pixel regions of at least the pixel electrodes 80. The gate bus lines 12 consist of the successive laminates of conductive layers, insulating films and semiconductor layers of the same patterns. The semiconductor layers of the gate bus lines 12 are selectively removed with the protective films PAS as a mask between the respective thin- film semiconductor elements and capacitors Cadd.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display substrate,
In particular, it relates to an active matrix type liquid crystal display substrate.

[0002]

2. Description of the Related Art A so-called active matrix type liquid crystal display substrate is provided with a non-linear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal in each pixel is theoretically always driven (duty ratio 1.0), the active system has better contrast than the so-called simple matrix system, which employs the time-division driving system. It is becoming an indispensable technology for display boards. A typical example of the switching element is a thin film transistor (TFT).

This thin film transistor (TFT)
On the transparent substrate surface on which the pixel electrode is formed, the gate, the gate insulating film, and the amorphous Si (a-S).
i) or a Si layer made of poly-Si (p-Si) is sequentially formed, and the drain electrode and the source electrode formed on the surface of the Si layer are integrated with a wiring layer for supplying a voltage and a pixel electrode, respectively. Is formed in.

An active matrix type liquid crystal display substrate using a thin film transistor (TFT) is
For example, Japanese Unexamined Patent Publication No. 63-309921 and "12.5 type active matrix type color liquid crystal display employing a redundant configuration", Nikkei Electronics, pages 193 to 210, December 15, 1986, published by Nikkei McGraw-Hill, Is known for.

[0005]

However, the thin film transistor (TF) of the liquid crystal display substrate having such a configuration is used.
In T), the gate, the gate insulating film, and the Si layer are separately formed in a predetermined pattern by using a well-known photoetching technique, and the number of manufacturing steps is increased, which is a problem. It was.

Therefore, the present invention has been made under such circumstances, and an object of the present invention is to provide a liquid crystal display substrate capable of significantly reducing the number of manufacturing steps.

[0007]

In order to achieve such an object, the liquid crystal display substrate according to the present invention basically comprises:
A pixel electrode to which a voltage is applied via a thin film semiconductor element on a gate bus line is provided, and an extension portion of this pixel electrode is superposed on an extension portion of another gate bus line adjacent to the gate bus line to form a capacitor. And a protective film formed by exposing at least the effective pixel region of the pixel electrode, wherein the gate bus line includes a conductive layer, an insulating film, and a semiconductor layer of the same pattern. The semiconductor layers of the gate bus line are sequentially laminated, and selectively removed by using the protective film as a mask between the thin film semiconductor element and the capacitor.

Further, in the invention as described above, the semiconductor layer and the insulating film in the terminal portion of the gate bus line are selectively removed by using the protective film or the liquid crystal substrate as a mask.

Further, the present invention is characterized in that a portion of the gate bus line other than the terminal portion, which is not covered with a protective film and the gate line is exposed, is inactivated by an anodizing method.

[0010]

In the liquid crystal display substrate thus constructed, the gate bus line is formed, the signal bus line for applying a voltage to the pixel electrode through the thin film semiconductor element and the pixel electrode are formed, and the protective film (PAS). Is completed by the formation of.

It is sufficient to use the photoetching technique once for each formation.

That is, the gate bus line is formed of a conductive layer, an insulating film,
A semiconductor layer is sequentially laminated, and a thin film semiconductor element can be formed at a predetermined position on the upper surface thereof.

Furthermore, the signal bus lines and pixel electrodes can be formed by the following photo-etching technique. In this case, both the signal bus line and the pixel electrode may be formed of an ITO film, but in order to reduce the resistance, a low resistance conductive layer having the same pattern as that of the ITO film is laminated on the upper surface of the ITO film. Good.

In this case, the capacitors can be simultaneously formed by setting the patterns so that a part of the gate bus line and a part of the pixel electrode are overlapped with each other.

Then, a protective film (PAS) having a hole can be formed in a portion corresponding to an effective pixel region of the pixel electrode by the photo etching technique.

At the same time, the protective film (PAS) is perforated in a portion corresponding to a region between the thin film semiconductor element and the capacitor.

After that, when the pixel electrode is formed of a laminated body of an ITO film and a conductive layer, the protective film (PA
By using S) as a mask as it is, the conductive layer in the effective pixel region is removed to expose the underlying ITO film.

Further, the semiconductor layer of the gate bus line corresponding to the region between the thin film semiconductor element and the capacitor is removed by using the protective film (PAS) as a mask to electrically insulate the thin film semiconductor element and the capacitor. Will be able to

Also in the formation of the gate terminal of the gate bus line, similarly, a hole is formed in the protective film (PAS) in a region corresponding to the region, and the protective film (PAS) is used as a mask as it is as a semiconductor layer, Remove the insulating layer in sequence,
The underlying conductive layer can be exposed.

[0020]

FIG. 5 is a connection diagram showing an embodiment of an equivalent circuit of a liquid crystal display substrate and its peripheral circuit according to the present invention.

Although the figure is a circuit diagram, it is drawn corresponding to the actual geometrical arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged, and corresponds to an equivalent circuit of a liquid crystal display substrate.

In the figure, X is a video signal line (signal bus line)
It means DL, and subscripts G, B, and R are added corresponding to green, blue, and red pixels, respectively. Y means a scanning signal line (gate bus line) GL, and the subscripts 1, 2, 3,
..., end are added according to the order of the scanning timing.

The signal bus lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

The gate bus line Y (subscript omitted) is connected to the vertical scanning circuit V.

The SUP is a TFT liquid crystal display device that displays information for a CRT (cathode ray tube) from a power supply circuit or a host (upper processor) to obtain a stabilized voltage source obtained by dividing a plurality of voltages from one voltage source. It is a circuit including a circuit for exchanging information for use.

FIG. 1 is a plan view showing an embodiment of a liquid crystal display substrate according to the present invention.

FIG. 1 is a constitutional view showing the main surface of one glass substrate on the liquid crystal side of the glass substrates arranged to face each other with a liquid crystal interposed therebetween, showing one pixel electrode and its periphery. Is. 2 is a sectional view taken along line II-II of FIG. 1, FIG. 3 is a sectional view taken along line III-III of FIG. 1, and FIG. 4 is a sectional view taken along line IV-IV of FIG.

In FIG. 1, a gate bus line 12 is first formed on the main surface of a glass substrate 10. The gate bus lines 12 are formed so as to extend in the X direction in the drawing, and are arranged in parallel in the Y direction at equal intervals.

Signal bus lines 23, which will be described later, intersect these gate bus lines 12 and are arranged in parallel in the X direction in the figure at equal intervals. Form a pixel region.

As shown in FIG. 2, the gate bus line 12 is a laminate having the same pattern in which an Al layer 13, an SiN film 4 as an insulating layer, and an a-Si layer 15 are sequentially laminated from the glass substrate 10 side. It consists of An a-Si layer 16 and a Cr layer 17 further doped with a high concentration of n-type impurities are laminated on the portion of the gate bus line 12 where the signal bus line 23 intersects.

A wide portion is formed in a part of the gate bus line 12 so as to extend to the pixel region, and the extended portion 12A has one electrode and one electrode of a capacitor (Cadd shown in FIG. 2). It is adapted to form a dielectric layer.

Further, one end of the gate bus line 12 is
The gate terminal 12B is configured, and the gate terminal 12B will be described in detail later.

A signal bus line 23 is formed so as to intersect the gate bus line 12 thus formed. The signal bus lines 23 are formed so as to extend in the Y direction in the figure and are arranged in parallel in the X direction at equal intervals.

As shown in FIG. 3, the signal bus line 23 is composed of a laminated body of the same pattern in which an ITO film 24 and an Al layer 25 are sequentially laminated from the glass substrate 10 side. The Al layer 25 is laminated on the ITO film 2
This is to reduce the resistance of 4 itself.

In this case, as shown in FIG. 4, in order to prevent an electrical short circuit from occurring between the signal bus line 23 and the gate bus line 12 intersecting the signal bus line 23 via the Al layer 13. Al layer 1 of the gate bus line 12
An Al ₂ O ₃ layer 13A is formed on both sides of No. ₃ . This Al ₂ O ₃ layer 13A has, for example, S layered on its upper surface.
It is formed by the anodization method using the iN layer 14 and the a-Si layer 15 as a mask.

Further, one end of the signal bus line 23 constitutes a signal terminal 23A.

On the other hand, a source electrode 30 which is arranged in parallel with the signal bus line 23 in parallel and which intersects the gate bus line 12 and extends in the pixel region, and a pixel formed integrally with the source electrode 30. The electrode 80 is formed. Like the signal bus line 23, the source electrode 30 and the pixel electrode 80 are ITO from the glass substrate 10 side.
The film 24 and the Al layer 25 are sequentially laminated to form a laminate having the same pattern.

The source electrode 30 serves as the source electrode of the TFT 50. That is, the TFT 50
Has its drain electrode corresponding to the signal bus line 23,
When a voltage is applied to the gate bus line 12, a channel layer is formed in the a-Si layer 15 via the SiN layer 14 that is an upper layer of the gate bus line 12 to form a switching element that turns on between the source electrode 30 and the drain electrode. There is.

Further, the pixel electrode 80 is further extended and is formed so as to sufficiently cover the extended portion 12A of the gate bus line 12 on the adjacent pixel region side. This allows
A capacitor (Cad shown in FIG.
d).

Further, a protective film (PAS) 70 made of, for example, a SiN film is formed on the entire surface of the glass substrate 10 thus processed, and the protective film (PAS) 70 is formed.
Includes the effective pixel area of the pixel electrode 80 and the gate terminal 12B.
Are formed in the area corresponding to the area where the signal terminals 23B are formed.

The Al layer 25 on the surface of the pixel electrode 80 exposed from the hole of the protective film (PAS) 70 is removed by using the protective film (PAS) 70 as a mask, and the ITO film 24 as the lower layer thereof is removed. Is exposed.

Similarly, the gate terminal 12B exposed from the hole of the protective film (PAS) 70 is covered with the protective film (PA).
S) 70 as a mask, the a-Si layer 15 on the surface,
The underlying SiN film 14 is exposed. Terminal part S
After the liquid crystal cell is assembled, the iN film 14 is removed by etching using the substrate facing the TFT substrate as a mask to expose the Al terminal 13.

Further, in this embodiment, in particular, a hole 40 is provided in the protective film (PAS) 70 in the region where the gate bus line is formed on both sides of the capacitor, and the hole 40 is provided in the gate bus line. It is formed so that the lines are sufficiently crossed.

The a-Si layer 15 on the gate bus line 12 exposed from the hole 40 is the protective film (PA).
S) 70 is used as a mask to remove the SiN film 14 underneath with a suitable removing liquid to expose the underlying SiN film 14.

In the liquid crystal display substrate thus constructed, the gate bus line 12 is formed, the signal bus line 23 for applying a voltage to the pixel electrode 80 via the TFT 50 and the pixel electrode 80 are formed, and the protective film ( PAS) 70 is completed.

It is sufficient to use the photoetching technique once for each formation.

That is, the gate bus line 12 is formed of the Al layer 13 of the same pattern by the photoetching technique.
A sequential laminated body of the SiN film 14 and the a-Si layer 15 is formed, and a TFT can be formed at a predetermined position on the upper surface thereof.

Further, the signal bus line 23 and the pixel electrode 80 can be formed by the following photo-etching technique. In this case, the signal bus line 23 and the pixel electrode 80 may be formed of only the ITO film 24, but in order to reduce the resistance thereof, a low resistance Al having the same pattern as that of the ITO film 24 is formed on the upper surface of the ITO film 24.
The layers 25 are laminated.

In this case, the capacitors Ca are set by setting those patterns so that a part of the gate bus line 12 and a part of the pixel electrode 80 are overlapped with each other.
dd can be formed at the same time.

Then, a protective film (PAS) 70 having a hole can be formed in the portion corresponding to the effective pixel region of the pixel electrode 80 by the photo etching technique.

The protective film (PAS) 70 has
At the same time, the portion corresponding to the region between the TFT 50 and the capacitor Cadd is also perforated by the hole 40.

After that, the protective film (PAS) 70 is directly used as a mask to remove the Al layer 25 in the effective pixel region and expose the ITO film 24 thereunder.

Further, a-Si of the gate bus line 12 corresponding to the area between the TFT 50 and the capacitor Cadd.
By removing the layer 15 using the protective film (PAS) 70 as a mask, the TFT 50 and the capacitor Cadd can be electrically insulated.

In forming the gate terminal 12B of the gate bus line 12, similarly, a hole is formed in the protective film (PAS) 70 in a region corresponding to the region, and the protective film (PAS) 70 is directly masked. As an a-Si layer 15
Can be removed to expose the underlying SiN film 14. The SiN film 14 is TF after the liquid crystal is assembled.
The substrate facing the T substrate can be removed as a mask to expose the underlying Al layer 13.

Next, one embodiment of the method of manufacturing the liquid crystal display substrate having the above-described structure will be described with reference to FIGS.
This will be described with reference to FIGS.

Here, FIGS. 8 to 12 are the same as those in FIG.
FIG. 13 is a sectional view taken along line II-II, and FIGS. 13 to 17 are sectional views taken along line III-III in FIG. 1.

Step 1. (FIGS. 8 and 13) First, the glass substrate 10 is prepared, and the Al layer 13, the SiN film 14, and the a-Si are formed on the entire main surface of the glass substrate 10.
Layer 15, a-S doped with high concentration n-type impurities
The i layer 16 and the Cr layer 17 are sequentially formed.

Here, for example, the Al layer 13 is 100 n
m, the SiN layer 14 is 400 nm, and the a-Si layer 15 is 20 nm.
0 nm, a-S doped with high concentration n-type impurity
The i layer 16 has a thickness of 40 nm, and the Cr layer 17 has a thickness of 60 nm.

After that, the gate bus line 12 is formed by using a well-known photo-etching method. The gate bus line 12 has an extended portion extending in the region where the capacitor (Cadd) is formed.

The gate bus lines 12 thus formed are formed as a plurality of parallel lines arranged in parallel in the Y direction, but in this embodiment, they are formed as shown in FIG. Of the gate terminal 12B, and the extending portions are commonly connected to each other to form a pattern.

This is for performing anodization for insulating the side surface of the Al layer 13 positioned as the lowermost layer of the gate bus line 12.

That is, as shown in FIG. 6, an electrode for anodization in the gate bus line 12 is formed by exposing the Al layer 13 by, for example, laser processing.

Then, as shown in FIG. 7, the glass substrate 10 is immersed in the anodizing liquid 30 filled in the container 31, and a voltage is applied between the exposed Al layer 13 and the platinum electrode 32. I am trying.

As a result, as shown in FIG. 4, anodized Al oxide films 13A are formed on both sides of the Al layer 13 positioned as the lowermost layer of the gate bus line 12.

Step 2. (FIGS. 9 and 14) An ITO film 24 and an Al layer 25 are sequentially formed on the entire main surface of the glass substrate 10 on which the gate bus lines 12 are formed as described above.

After that, the signal bus line 23 and the pixel electrode 80 are formed by using a well-known photo etching method. In this case, the pixel electrode 80 is provided with the source electrode 30 which has an extension part in a part thereof and the extension part intersects the gate bus line 12, and also extends in other parts. This extended portion extends to the formation region of the capacitor (Cadd).

As a result, a capacitor (Cadd) having the SiN film 14 as a dielectric is formed in this region.

The Al layer 2 formed by the photo etching
For the selective etching of 5 and the ITO film 24, a dry etching method using a mixed gas of Bcl ₃ and cl ₂ can be used. In this case, since the Cr layer 17 is formed on the uppermost layer of the gate bus line 12, the underlying a-Si layers 16 and 15 have the role of the Cr layer 17 serving as an etching stopper.

Step 3. (FIGS. 10 and 15) After that, the Cr layer 17 formed on the uppermost layer of the gate bus line 12 using the signal bus line 23 and the like as a mask,
Then, the a-Si layer 16 doped with the high-concentration n-type impurity formed in the lower layer is sequentially dry-etched.

As a result, the uppermost layer of the gate bus line 12 becomes the a-Si layer 15, and the Cr layer 17 and the Cr layer 17 are formed only at the intersections with the signal bus line 23 and the source electrode 30.
A-Si layer 16 doped with a high concentration of n-type impurities
Will remain. These function as contact layers.

Here, in the etching of the Cr layer 17, for example, a mixed gas of Cl ₂ + O ₂ is used and a high concentration of n is used.
In the a-Si layer 16 doped with type impurities, a mixed gas of SF ₆ + Cl ₂ can be used, for example.

Step 4. (FIGS. 11 and 16) The glass substrate 1 on which the signal bus lines 23 are formed in this manner .
Protective film (PAS) consisting of SiN film on the entire main surface of 0
70 is formed.

Then, the protective film (PAS) 70 is perforated by using a well-known photoetching method. The holes are formed in the pixel effective region of the pixel electrode 80, the gate terminal 12B forming region, the signal terminal 23A forming region, and the regions on the gate bus line 12 on both sides of the capacitor Cadd.

As a result, the uppermost layer A is formed on the pixel electrode.
The I layer 24 is exposed, the gate terminal 12B is exposed with the uppermost a-Si layer 15, and the signal terminal 23A is exposed with the uppermost Al layer 25.

Further, the a-Si layer 15 is exposed in the regions on the gate bus line 12 on both sides of the capacitor Cadd.

Step 5. (FIGS. 12 and 17) Using the protective film (PAS) 70 as a mask, the Al layer 24 in the pixel electrode 80 is removed with an appropriate removing liquid.

Further, with the protective film (PAS) 70 as a mask, the gate bus lines 12 on both sides of the capacitor are provided.
The upper a-Si layer 15 is removed with a suitable removing liquid.

In this embodiment, the gate terminal 12B and the signal terminal 23A are formed and the capacitor Cadd is formed.
12B on both sides of the gate bus line at the opening of the protective film (PAS), the underlying a-Si film 1
Although only 5 is removed, at this time, the SiN film 14 may be removed after the a-Si film. In this case, the gate drive voltage when driving the liquid crystal is directly applied to the liquid crystal without passing through the SiN film 14, which causes deterioration of the liquid crystal. Therefore, S
After removing the iN film to expose the Al film 13, only the Al film opened on both sides of the capacitor Cadd 12B is inactivated by the anodization method described above, and the alumina film 13B is selectively formed on the Al film of FIG. There must be. In addition,
This method is not limited to the structure of the present invention and is an effective method for compensating for defects in the protective film in any structure as long as it uses a gate bus line.

[0079]

As is apparent from the above description,
According to the liquid crystal display substrate of the present invention, the number of manufacturing steps can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a partial plan view showing an embodiment of a liquid crystal display substrate according to the present invention.

FIG. 2 is a sectional view taken along line II-II in FIG.

FIG. 3 is a sectional view taken along line III-III in FIG.

FIG. 4 is a sectional view taken along line IV-IV in FIG.

FIG. 5 is an equivalent circuit diagram of a liquid crystal display substrate and its peripheral circuits according to the present invention.

FIG. 6 is a plan view showing an example of a pattern of gate bus lines on a glass substrate during anodization.

FIG. 7 is an explanatory diagram showing an example of a method for anodizing.

8 is a process 1. showing an embodiment of the manufacturing method along the line II-II in FIG. FIG.

9 is a step 2. showing an embodiment of a manufacturing method along the line II-II in FIG. FIG.

FIG. 10 is a step 3. showing an embodiment of the manufacturing method along the line II-II in FIG. FIG.

FIG. 11 is a process showing an example of the manufacturing method along the line II-II in FIG. FIG.

FIG. 12 is a step 5. showing an embodiment of the manufacturing method along the line II-II in FIG. FIG.

FIG. 13 is a step 1. showing an embodiment of the manufacturing method along the line III-III in FIG. FIG.

FIG. 14 is a process 2. showing an embodiment of the manufacturing method along the line III-III in FIG. FIG.

FIG. 15 is a step 3. showing an embodiment of the manufacturing method along the line III-III in FIG. FIG.

FIG. 16 is a step showing an embodiment of the manufacturing method along the line III-III in FIG. FIG.

FIG. 17 is a step 5. showing an embodiment of the manufacturing method along the line III-III in FIG. FIG.

FIG. 18 is a diagram showing another embodiment of the present invention.

[Explanation of symbols]

 12 gate bus line 23 signal bus line 80 pixel electrode TFT thin film semiconductor element Cadd capacitor PAS protective film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masahiro Yanai, 3300 Hayano, Mobara, Chiba Prefecture, Electronic Device Division, Hitachi, Ltd. (72) Juichi Horii, 3300, Hayano, Mobara City, Chiba Hitachi, Ltd. Electronic Device Business (72) Inventor Yuichi Hashimoto 3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd. Electronic Devices Division (72) Inventor Masaaki Matsuda 3300 Hayano, Mobara-shi, Chiba Hitachi Ltd. Electronic Devices Division

Claims (3)

[Claims] 1. A pixel electrode to which a voltage is applied via a thin film semiconductor element on a gate bus line, and an extension of this pixel electrode is adjacent to another gate bus line. And a protective film formed by exposing at least the effective pixel region of the pixel electrode, the gate bus line having a conductive layer and an insulating film having the same pattern. A liquid crystal display substrate, comprising a sequentially laminated body of semiconductor layers, wherein the semiconductor layer of the gate bus line is selectively removed between each thin film semiconductor element and a capacitor by using the protective film as a mask. 2. The liquid crystal display substrate according to claim 1, wherein the semiconductor layer and the insulating film in the terminal portion of the gate bus line are selectively removed by using the protective film or the liquid crystal substrate as a mask. 3. A pixel electrode to which a voltage is applied via a thin film semiconductor element on a gate bus line, and an extension of this pixel electrode is adjacent to another gate bus line. And a protective film formed by exposing at least the effective pixel region of the pixel electrode while forming a capacitor by superimposing
A method for manufacturing a liquid crystal display substrate having a passivation process for gate bus lines after forming a protective film.