JPH07131457A - Data communication system - Google Patents

Abstract

PURPOSE:To enable each of n boards, where control circuits are mounted, to transmit information that is required to transmitted the all of information by each board to all other boards. CONSTITUTION:A means 101 is provided which supplies a clock signal and a frame signal to n boards where control circuits 105 are mounted, and each board is provided with a timing signal generating part 108, a parallel-serial conversion circuit 106, and a serial-parallel conversion circuit 107, and an individual timing signal is generated from the clock signal and the frame signal in accordance with the ID signal given to each board, and data sent from the control circuit 105 is transmitted as serial data in accordance with this timing signal. Serial data transmitted from another board is received from the multiplex data line in accordance with the set timing and is taken into the control circuit 105.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for multi-CPU data communication using a control bus. The present invention relates to an improvement in a method in which a plurality of CPUs having a board structure mutually transmit data. The present invention relates to a data communication system capable of broadcasting information that a board having all control circuits wants to transmit.

[0002]

2. Description of the Related Art Conventionally, in the case of performing data communication between a plurality of boards having a control circuit, for example, means such as an Ethernet driver 202 as shown in FIG. As disclosed in Japanese Patent Laid-Open No. 289664, mutual communication is performed using dedicated hardware.

[0003]

When all the boards having the control circuit transfer information to be transferred to all the other boards by broadcasting, for example, in the method using the Ethernet driver 202, the circuit scale becomes large, Further, there is a drawback that the overhead in performing data communication becomes large, and, for example, JP-A-63-289.
In the example disclosed in Japanese Patent No. 664, it is difficult for all the boards to broadcastly transfer the data to all the boards because the master is decided and communication is performed with the slaves.

The present invention solves such a problem, and it is an object of the present invention to provide a data communication system capable of transmitting information desired by each board to all other boards with a small-scale circuit configuration. To aim.

[0005]

According to the present invention, there are provided a plurality of n boards each having a control circuit mounted thereon, and means for commonly supplying a clock signal and a frame signal to the n boards. The board is provided with a timing signal generation unit that generates an individual timing signal from the clock signal and the frame signal according to an ID signal provided thereto, and a parallel signal transmission unit that transmits the data sent from the control circuit as serial data according to the timing signal. -Serial conversion circuit and serial data received from other boards according to the set timing and received by the control circuit from the multiplexed data line-
And a parallel conversion circuit.

Each board is provided with n insertion data lines for transmitting serial data to be transmitted, and an AND circuit having a signal of the insertion data line as an input and an output of the AND circuit are synchronized with the clock signal. A multiplexing unit including a flip-flop for transmitting to the multiplex data line,
Each board is provided with a pull-up circuit for transmitting a logic "1" to the output circuit of the parallel-serial conversion circuit when data is not transmitted, or with a buffer circuit for the output circuit of the parallel-serial conversion circuit. It is preferable that the output of the buffer circuit is connected to the multiplex data line by wire or, and the set timing is generated by the timing signal generator or the control circuit.

[0007]

A clock signal and a frame signal are commonly supplied to each of a plurality of n boards on which a control circuit is mounted. In each board, an individual timing signal is generated from the supplied clock signal and frame signal at timings that do not coincide with each other according to the ID signal provided by the timing signal generation unit. The parallel-serial conversion circuit transmits the data sent from the control circuit as serial data according to this timing signal, and the serial data transmitted by another board according to the set timing is transmitted from the other data board through the multiple data line. Receive and capture in control circuit.

Thus, the information that each board wants to transmit can be sent to all the other boards.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention.

In the first embodiment of the present invention, the control circuit 1 is used.
And a plurality of n boards 111 to 11n on which 05 is mounted,
The n boards 111 to 11n are provided with a signal supply unit 101 that supplies a clock signal a and a frame signal b in common, and each board 111 to 11n is provided with an ID
A timing signal generation unit 108 that generates individual timing signals from the clock signal a and the frame signal b in accordance with the signals 121 to 12n, and parallel serial that transmits the data sent from the control circuit 105 as serial data in accordance with the timing signals. Conversion circuit 1
06, and a serial / parallel conversion circuit 107 that receives serial data transmitted from another board from the multiplex data line c according to the set timing and fetches it into the control circuit 105.

Further, with the insertion data lines d ₁ to d _n of the n transmitting serial data each board 111~11n transmits respectively, the AND circuit which receives the signal of the insertion data lines d ₁ to d _n 104 and this AND circuit 10
The output of 4 is synchronized with the clock signal a and the multiplexed data line c
10 including a flip-flop 103 for transmitting to
2, each of the boards 111 to 11n is provided with a pull-up circuit 109 that transmits a logic “1” to the output circuit of the parallel-serial conversion circuit 106 when data is not transmitted.

Next, the operation of the first embodiment of the present invention thus constructed will be described.

A signal supply unit 101 generates a clock signal a and a frame signal b to generate a plurality of n boards 111-1.
Supply to 1n. In each of the boards 111 to 11n, the ID signals 121 to 1 to which the timing signal generator 108 is applied
According to 2n, an individual timing signal is generated from the clock signal a and the frame signal b supplied from the signal supply unit 101.

The data sent by the control circuit 105 is output as serial data by the parallel / serial conversion circuit 106 in accordance with the timing signal generated by the timing signal generation unit 108. When the control circuit 105 does not transmit data, the pull-up circuit 109 transmits a logic "1" at that time.

In the multiplexer 102, the AND circuit 104 inputs the data transmitted from each of the boards 111 to 11n via the n insertion data lines d _{1 to} d _n , and the flip-flop 103 of the AND circuit 104. The output is transmitted to the multiplexed data line c in synchronization with the clock signal a.

On the other hand, the serial / parallel conversion circuit 107 of each of the boards 111 to 11n includes the timing signal generator 10
According to the timing generated by 8, the serial data transmitted by the other board is received from the multiplex data line c and fetched in the control circuit 105.

In this way, the information desired to be transmitted by each of the boards 111 to 11n can be transmitted to all the boards.

FIG. 2 is a timing chart showing the operation timing of each signal and insertion data in the first embodiment of the present invention, and FIG. 3 shows the parallel / serial conversion circuit and the register of the serial / parallel conversion circuit in the first embodiment of the present invention. It is a figure which shows the content.

By the clock signal a and the frame pulse signal b from the signal supply unit 101 and the ID signals 121 to 12n giving different IDs to the boards 111 to 11n, the timing signal generation unit 108 makes the boards 111 to 1n.
Different timing is generated for each 1n and output to the parallel / serial conversion circuit 106. The parallel / serial conversion circuit 106 outputs the content of the register set by the control circuit 105 as a serial signal at a given timing. At this time, the serial data output by each of the boards 111 to 11n is output to different time slots by the ID signals 121 to 12n and the timing signal generation unit 108. The insertion data output from each of the boards 111 to 11n is multiplexed by the multiplexing unit 102 and output. The multiplexed data output from the multiplexing unit 102 is parallel-developed by the serial / parallel conversion circuit 107 of each of the boards 111 to 11n, and the control circuit 105 can obtain the parallel-developed data as a register.

(Second Embodiment) FIG. 4 is a block diagram showing the configuration of the second embodiment of the present invention.

In the second embodiment of the present invention, a plurality of n boards 131 to 13n each mounted with a control circuit 105 for generating a timing signal and the n boards 131 to 1n.
3n, and a signal supply unit 101 that supplies a clock signal a and a frame signal b in common.
3n includes a timing signal generation unit 108 that generates individual timing signals from the clock signal a and the frame signal b in accordance with the given ID signals 121 to 12n.
And a parallel / serial conversion circuit 106 that transmits the data sent from the control circuit 105 as serial data according to this timing signal, and the serial data that another board transmits according to the set timing from the multiplex data line c. The serial / parallel conversion circuit 107 which is then taken into the control circuit 105, the transmission buffer circuit 110a which temporarily holds the data from the parallel / serial conversion circuit 106, and the control circuit 105 which temporarily holds the data to the serial / parallel conversion circuit 107. And a reception buffer circuit 110b for outputting according to the control of. The output of the transmission buffer circuit 110a is the multiple data line c
Connected to the wireless network.

In the case of the second embodiment, the signal supply unit 101
Generates a clock signal a and a frame signal b and supplies them to a plurality of n boards 131 to 13n. Each board 13
1 to 13n, the signal supply unit 1 according to the ID signals 121 to 12n provided by the timing signal generation unit 108.
An individual timing signal is generated from the clock signal a and the frame signal b supplied from 01.

The data transmitted by the control circuit 105 is output as serial data via the transmission buffer circuit 110a in accordance with the timing signal generated by the parallel / serial conversion circuit 106 by the timing signal generation unit 108.

Further, the serial / parallel conversion circuit 107 of each of the boards 131 to 13n transmits the serial data transmitted by the desired partner board from the multiplex data line c to the reception buffer circuit 110b in accordance with the timing generated by the control circuit 105. And is received by the control circuit 105.

With such an operation, the second embodiment of the present invention can obtain the same effects as the first embodiment.

[0027]

As described above, according to the present invention, it is possible to broadcast the information desired to be transmitted by each of the boards having all the control circuits in a small-scale circuit configuration to all the boards. is there. The configuration of the present invention has a simple device configuration and is useful for data transmission in a device having a board configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation timing of each signal and insertion data in the first embodiment of the present invention.

FIG. 3 is a diagram showing the contents of registers of the parallel / serial conversion circuit and the serial / parallel conversion circuit in the first embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

101 signal supply unit 102 multiplexing unit 103 flip-flop 104 AND circuit 105, 201 control circuit 106 parallel-serial conversion circuit 107 serial-parallel conversion circuit 108 timing signal generation unit 109 pull-up circuit 110a transmission buffer circuit 110b reception buffer circuit 111 to 11n , 131 to 13n, 211 to 211n
Board 121 to 12n ID signal 202 Ethernet driver 203 Termination unit 210 Control bus

Claims (5)

[Claims] 1. A plurality of n boards, each having a control circuit mounted thereon, and means for supplying a clock signal and a frame signal commonly to the n boards, each board being provided with an ID signal provided thereto. A timing signal generator that generates individual timing signals from the clock signal and the frame signal, and a parallel-serial conversion circuit that transmits the data sent from the control circuit as serial data in accordance with the timing signal. And a serial / parallel conversion circuit that receives serial data transmitted from another board from a multiplex data line and captures the serial data into a control circuit according to the timing. 2. An AND circuit having n insertion data lines for respectively transmitting serial data transmitted by each board, and an AND circuit to which a signal of the insertion data line is input, and an output of the AND circuit are synchronized with the clock signal. A pull-up for transmitting a logic "1" to the output circuit of the parallel-serial conversion circuit when data is not transmitted to each board. The data communication system according to claim 1, further comprising a circuit. 3. The data communication system according to claim 1, wherein each board is provided with a buffer circuit in an output circuit of the parallel-serial conversion circuit, and an output of the buffer circuit is connected to the multiple data line by wire or wire connection. 4. The data communication system according to claim 2, wherein the set timing is generated by the timing signal generator. 5. The data communication system according to claim 2, wherein the set timing is generated by the control circuit.