JPH06125352A - Information transfer method - Google Patents

Abstract

PURPOSE:To reduce the number of signal wires from a central control section to a controlled section by providing a clock section generating a clock and a frame pulse synchronous with a clock and a frame pulse outputted from a common clock section. CONSTITUTION:A clock and a frame pulse are supplied from a common clock section 4, the clock section 12 generates a clock and a frame pulse synchronously with the clock and the frame pulse fed from the clock section 4 and supplies them to a communication processing section 11. The communication processing section 11 outputs a bus use request signal, sends transmission data according to the bus use enabling signal and receives data sent from a controlled section. The bus use request signal is inserted to a position delayed by a prescribed value from a frame pulse and the bus use enabling signal inserted to the prescribed position is read and the bus use request/bus use enabling signals are transferred while being multiplexed on one signal line. Thus, the signal is transferred to a bus arbitration circuit via a multiplexer demultiplexer circuit. The transmission data are inputted to a reception processing circuit 13 and the reception processing circuit sends the data to all controlled circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of transferring information between a central control unit and a controlled unit in a communication device, and in particular, supplying a clock for information transfer from a clock source common to the system, and , An information transfer method capable of performing bus arbitration by one signal line.

A typical example of a system composed of a central control unit and a controlled unit is an electronic computer, but a system similar to the computer or a system having a similar configuration has been used in the communication field for a long time. It is in the world. An example of the former is an electronic exchange, a typical example of the latter is a monitoring and control system, and the present invention relates to the latter.

Generally, in a monitoring / control system, a large number of signal lines are required, the wiring is congested, and a large number of connection connectors are required. Therefore, the number of controlled parts that can be accommodated in one frame is reduced. There are constraints. Therefore, it is desired to realize an information transfer method capable of reducing the number of wires between the central control unit and the controlled unit and enabling bus arbitration by a simple method.

[0004]

2. Description of the Related Art FIG. 4 is a diagram showing a conventional information transfer method in a communication device. In FIG. 4, 1a is a central control unit,
Reference numeral 2a is a controlled portion 1, and 3a is a controlled portion n. The central control unit has a communication processing unit 11a, a clock supply unit 12a, a reception processing unit 13a, and a bus arbitration unit 14a. Each controlled unit has a communication processing unit.

In the conventional information transfer method, the central control unit and each controlled unit are connected in a star shape, and various information is transferred by individual signal lines. The information includes a clock, transmission data, reception data, a bus use request signal, and a bus use permission signal, and the central control unit and the controlled unit all require signal lines for these information. Therefore, the central control unit that accommodates all the signal lines requires a large number of wirings, connection connectors, and buffer circuits, which increases the hardware scale, resulting in a controlled unit that can be accommodated in one frame. There is a problem that the number is limited.

[0006]

In view of such a problem, the present invention reduces the number of wires between the central control unit and the controlled unit,
Moreover, it is an object of the present invention to provide an information transfer method capable of bus arbitration by a simple method.

Generally, the communication system has a common clock source, and in the configuration for realizing the conventional information transfer method, both the clock generation in the central control unit and the clock required for the individual operation of the controlled unit are performed. , Is rooted in this common clock. The signal line for bus arbitration is provided independently for the request signal and the permission signal. Solving these is the solution to the problem.

[0008]

FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, 1 is a central control unit, 2 is a controlled unit 1, 3 is a controlled unit n, and 4 is a common clock source. The central control unit 1 includes a communication processing unit 11 and a clock unit 1.
2, reception processing unit 13, bus arbitration unit 14, demultiplexing unit 15
The controlled unit has a communication processing unit and a clock unit.

[0009]

By providing each unit with the clock output from the common clock unit and the clock unit synchronized with the frame pulse and the clock unit for generating the frame pulse necessary for information transfer, the clock is transferred from the central control unit to each controlled unit. The clock line to be supplied is not needed, and the number of signal lines can be reduced.

In addition, each unit operates according to the clock and frame pulse received from the common clock source 4,
Since each unit operates in synchronization, it is possible to multiplex and transfer information, and it is possible to multiplex the bus use request / bus use permission signal and transfer it by one signal line. Specifically, the bus use request signal is inserted from the frame pulse at the time position of the phase difference corresponding to the address, and the bus use permission signal is read at the time position of the second phase difference corresponding to the address from the frame pulse.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Although only the portion of the principle of the present invention directly related to the invention has been described above, the overall function of the configuration of FIG. 1 will be described before a detailed description. (Since the communication processing unit performs the same operation in both the central control unit and the controlled unit, this is represented by the explanation of the central control unit.) The common clock unit 4 supplies the clock and the frame pulse, and the clock unit 12 supplies them. A clock and a frame pulse synchronized with the clock and the frame pulse are generated and supplied to the communication processing unit 11. The communication processing unit 11 issues a bus use request signal, sends out transmission data according to the bus use permission signal, and receives data transmitted by the controlled unit. The bus use request signal is inserted at a predetermined delay from the frame pulse, and the bus use enable signal inserted at the predetermined position is read. The bus use request / bus use enable signal is multiplexed and transferred to one signal line. To do. Since the bus use request / bus use permission signal is multiplexed in this way, it is transferred to the bus arbitration circuit via the demultiplexing circuit.

The transmission data is input to the reception processing circuit 13, and the reception processing circuit sends the data to all controlled circuits (OR processing). Since the address of the controlled circuit which should receive the data is attached to the data, only the controlled circuit whose address is equal to the address accompanying the data is read. The reception processing circuit also performs an OR process on the data from the controlled unit and sends it to the central control unit and other than the controlled unit that transmitted the data.

FIG. 2 is a detailed block diagram of the communication processing unit according to the embodiment of the present invention. In FIG. 2, 11
Reference numeral 1 is a counter, 112 is a pulse generation circuit, 113 is a high impedance control circuit, 114 is a flip-flop circuit, and 115 is a communication processing circuit.

In the counter 111, a divided clock is generated from the clock and the frame pulse supplied from the common clock unit, and a phase for issuing a bus use request and a bus use permission signal are generated from the divided clock and the address signal. Generate a pulse with a read phase.

To output the bus use request signal, the high-impedance control circuit is enabled at the position of the bus use request pulse of the bus use request signal output from the communication processing circuit and output to the multiple signal line. To read the bus use permission signal, the signal on the multiple signal line is read by the flip-flop circuit 114 at the position of the bus use permission detection pulse of FIG. 3 is a time chart of the communication processing unit.

The bus use request signal and the bus use permission signal are multiplexed for a predetermined time based on the frame pulse.
R means a bus request signal, A means a bus use permission signal, and numbers correspond to addresses. For example, 0 means a central control unit and 1 means a controlled unit 1. .

Now, in order for the controlled unit 1 to issue the bus use request signal, the request signal is inserted at the position of the bus use request pulse of, and the bus use enable signal is read by the phase of the bus use enable signal. , Read the data input to the flip-flop circuit.

The demultiplexing circuit extracts the bus request state from each unit and transmits it to the bus arbitration circuit by the same function as above, and in the bus arbitration circuit, only one of the central control unit and the controlled unit is permitted to use the bus. Is given, and the signal is multiplexed by the demultiplexing circuit and transmitted.

In addition, the communication processing circuit sends data to another communication processing unit and receives data from another communication processing unit.

[0020]

As described above, the number of signal lines can be reduced by supplying the clock that the communication system has in common to the central control unit and the controlled unit, and as a result, the hardware scale can be reduced.

Further, by supplying the common clock and the frame pulse, the respective parts can be synchronized with each other, the bus use request signal and the bus use permission signal can be multiplexed, the reduction of the signal line related to the bus arbitration, and the bus Simplification of arbitration is possible.

[Brief description of drawings]

FIG. 1 is a principle of the present invention.

FIG. 2 is a detailed block diagram of a communication processing unit according to the embodiment of this invention.

FIG. 3 is a time chart of a communication processing unit.

FIG. 4 is a conventional information transmission method in a communication device.

[Explanation of symbols]

1 central processing unit, 11 communication processing unit, 12 clock unit, 13 reception processing circuit, 14 bus arbitration circuit, 15 demultiplexing circuit 2 controlled unit, 21 communication processing unit, 22 clock unit 3 controlled unit, 31 communication processing unit , 32 clock section

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hirotomo Miyawaki 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Noriyuki, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (1)

[Claims] 1. An information transfer method for transmitting and receiving a control signal, a supervisory signal and the like between a central control unit and a controlled unit in a communication device having a clock source common to the system, the central control unit and the controlled unit. The clock for the information transfer between the two parts is supplied from the clock source common to the system, and the central control part and the controlled part multiplex the bus use request signal and the bus use permission signal transmitted and received prior to the information transfer. hand,
An information transfer method characterized in that bus arbitration is performed by one signal line.