JPH0581173A - Status information transfer device between system buses - Google Patents

Abstract

PURPOSE:To realize a status information transfer device between system buses capable of surely recognizing the status of each module in a system in which many modules on a system bus are connected. CONSTITUTION:In a status information transfer device between system buses obtaining the status information of each module of a system in which plural modules are connected on a system bus, the ID information of a module trying to obtain the status information is transmitted as serial data on a system bus, a master control circuit MC receiving the status information transmitted via the system bus from each module is incorporated in one of plural modules or a master module M, the 10 information transmitted from the master control circuit MC is compared with the ID information within each module S1 to Sn, and a slave control circuit SC transmitting the status information of the module as serial data when the ID information coincides is incorporated in the each remaining module S1 to Sn.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a status information transfer device between system buses.

[0002]

2. Description of the Related Art When a trouble occurs in a system in which a large number of card-type modules are connected to the same system bus, a clue for solving the trouble is indicated by an LED display on the front panel of each module. The status information given has important meaning.

In particular, when the system is down, access to each module is disabled, so that the LED display which allows the user to directly visually know the status greatly contributes to troubleshooting.

However, there is a limit to the content (amount of information) that can be displayed due to the restrictions on the panel surface. Therefore, it is necessary to infer the details of the failure from a few status information sources. In other words, it is no exaggeration to say that the more the content of the status information displayed on each card, the shorter the time required for troubleshooting.

[0005]

However, according to the above method, it is necessary to directly confirm the panel surface of each module. Therefore, when many modules are connected to the same system bus, it is difficult to visually recognize the panel surfaces of all the modules.

The present invention has been made paying attention to such a point, and an object thereof is to reliably recognize the status of each module in a system in which a large number of modules are connected to the system bus. It is to provide a possible status information transfer device between system buses.

[0007]

SUMMARY OF THE INVENTION The present invention for solving the above-mentioned problems is a system bus status information transfer device for obtaining status information of each module of a system in which a plurality of modules are connected on a system bus. , A master that is built in one of a plurality of modules, sends out the ID information of the module for which status information is to be obtained as serial data on the system bus, and receives the status information sent from each module via the system bus. The control circuit and the module other than the module in which the master control circuit is built-in are incorporated in each module, and the ID information sent from the master control circuit is compared with the ID information in each module, and I
When the D information matches, a slave control circuit for sending the status information of the module as serial data is provided.

[0008]

In the present invention, the master control circuit built in one module sends the ID information of the module for which status information is to be obtained as serial data. The slave control circuit of the module that has received the ID information compares the received ID information with the ID information of its own module, and if the ID information matches, sends the status information as serial data. The status information is transferred in this manner, but since it operates independently of the system bus as serial data, it is not affected by system trouble or system bus down.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a system configuration diagram showing an entire embodiment of the present invention, and FIGS. 2 and 3 are configuration diagrams showing in detail the configuration of the main part shown in FIG. Further, FIG. 4 is a time chart showing operation states, and FIG. 5 is a state transition diagram showing state transitions during operation of the device shown in FIG.

In this embodiment, a case where a VME bus, which is an industry standard, is used as a system bus will be described. A plurality of modules are connected to the VME bus 1, one of which is a master (master module) M for status communication, and the rest are slaves (slave modules) S. The VME bus 1 uses SERCLK (serial communication clock) for serial communication and SERD.
AT (serial data) is prepared, and this protocol is open to users. Therefore, in this embodiment, by using this SERCLK and SERDAT,
The master module can know the status information of each slave module.

The master control circuit MC incorporated in the master module M shown in FIG. 2 has the following functions. A clock (SERCLK) oscillator 3 for serial communication is supplied onto the bus 1. However, when the system clock (SYSCLK) is used for communication, it is not necessary to supply SERCLK. When the status information from the slave module S is read out, the ID information of the slave module is used as serial data and V is transmitted via the parallel / serial conversion shift register 5.
It is sent to the SERDAT line on the ME bus 1. By transmitting the ID information, the status information from the slave module S corresponding to the ID information is converted into parallel data by the serial / parallel conversion shift register 7.

Next, the slave control circuit SC incorporated in the slave module shown in FIG. 3 has the following functions. Each slave module has independent ID information (card base address is set by dip switch etc.), and SERCLK from master module M
ID information (signal on the SERDAT line) and your ID
Compare with the information. As a result of the comparison of the ID information, if they match, it means that there is a status read request from the master module M. In this case, the own status information is sent out as SEDAT via the logic sequencer 9. In this case, SEDAT should be synchronized with SECLK.

The operation timing of each section having such a function will be described with reference to the time chart shown in FIG. Here, a case will be described in which 4-bit data as ID information and 4-bit data as status information of each slave module are exchanged.

The ID information of the slave whose status is to be read is stored in the shift register 5 of the master control circuit MC.
(Step 1).

Set the IDEN bar LOW. As a result, the contents of the inputs A to E of the shift register 5 are changed to the clock SERC.
Output as SERDAT bar in synchronization with LK. in this case,
The first bit of the SERDAT bar is always LOW and plays the role of a start bit. When all the 5-bit data has been transmitted, the IDEN bar is set to HIGH to stop the transmission (step 2).

The ID information sent from the master module in this way is also received by all the slave modules. Then, each slave module compares and determines by the comparison means in the slave control circuit SC whether or not it matches with its own ID information (step 3).

When there is a slave module whose ID information matches, that module synchronizes the contents of its own status information with the clock SERCLK and SE through the gate 10.
4-bit data is output as the RDAT bar (step 4).

The master control circuit MC sets the STRD bar to LOW and outputs the SERDAT bar data in series / while the status information is transmitted from the slave module whose ID information matches.
Parallel conversion is performed (step 5).

After the status information has been transmitted from the slave module, the master module M reads the output of the shift register 7. As a result, it is possible to know the status of the slave module for which the ID information is set in step 1 (step 6).

Next, referring to FIG. 5, the slave control circuit SC
The state transition of the logic sequencer 9 will be described.

Normally, it is in the standby state of S0, and SE
Waiting for the start bit to be sent on the RDAT bar. When the LOW level start bit is detected, S
Transition to 1, and the master also starts comparing the ID information from the module with his own ID information. That is, the ID information is 1
Compare bit by bit, transition to S2, S3, S4,
If all match, the status transitions to S5 and later. On the other hand, if the IDs do not match, the process transits to S1 'to S4'. In this case, since another slave module has detected the coincidence of the IDs, S1 'to S4' are sequentially transited in order to adjust the timing.

The slave module having the matching ID information sends 4-bit status information to S5, S6, S7,
It is sent to the master module in S8. On the other hand, ID
The slave modules whose information does not match transit to S5 ', S6', S7 ', S8' in order to adjust the timing, and wait until the status transmission of other slave modules is completed.

As described in detail above, according to this embodiment, more status information of each module can be known when a trouble occurs in a system composed of a large number of modules, which greatly contributes to solving the trouble. In particular, in the configuration of this embodiment, since the status of each module can be read by the signal line independent of the system bus,
Even if the system bus goes down, the status of each module can be easily known. Moreover, since the communication is performed by serial communication, if the bit length of the data is made longer, more information can be known. Therefore, the time spent for troubleshooting can be shortened.

Further, since the status information transfer system of this embodiment is independent of the system bus, it can be applied not only to the occurrence of a trouble but also to an application for monitoring the status of each module in a normal use state. It can be achieved without affecting the system performance.

Since serial communication is performed,
It is sufficient to prepare at least one required signal line on the system bus (in this case, substitute the system clock as the serial clock). Therefore, there is no need to significantly expand the bus for this system.

[0027]

As described in detail above, according to the present invention, in a system in which a large number of modules are connected to the system bus, it is possible to reliably recognize the status of each module. An inter-bus status information transfer device can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a main part of the configuration shown in FIG.

FIG. 3 is a configuration diagram showing a main part of the configuration shown in FIG.

FIG. 4 is a time chart showing an operation state of the apparatus according to the embodiment of the present invention.

FIG. 5 is a state transition diagram showing an operation state of the embodiment of the present invention.

[Explanation of symbols]

 1 System Bus 3 Clock Oscillator 4 Buffer 5 Parallel / Serial Conversion Shift Register 6 Gate 7 Serial / Parallel Conversion Shift Register 8 Buffer 9 Logic Sequencer 10 Gate 11 Inverter M Master Module S Slave Module MC Master Control Circuit SC Slave Control Circuit

Claims (1)

[Claims] 1. A status information transfer device between system buses for obtaining status information of each module of a system in which a plurality of modules are connected on a system bus, the status information transfer apparatus being built in one of the plurality of modules and having a status. A master control circuit (MC) that sends the ID information of the module for which information is to be obtained as serial data to the system bus and receives the status information sent from each module via the system bus, and the master control circuit are built-in. Built in each module other than the above module, compares the ID information sent from the master control circuit (MC) with the ID information in each module, and if the ID information matches, sends the status information of the module as serial data. Slave control circuit (SC)
And a status information transfer device between system buses.