JPH11243405A - Asynchronous serial communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain miniaturization of chip size of an asynchronous serial communication system by reducing a master and a slave transmission and reception parts into single equipment and making a signal line of a bus format. SOLUTION: This device is composed of a master 1 including a transmission and reception part 1-1, a data processing part 1-2, a master 2 including a transmission and reception part 2-1, a data processing part 2-2, and slaves 3,4 and 5 for communicating with these masters. The slaves 3,4 and 5 are provided with a transmission and reception part 3-1, a peripheral circuit part 3-2, a transmission and reception part 4-1, a peripheral circuit part 4-3 and a transmission and reception part 5-1, a peripheral circuit part 5-2 respectively. Transmission and reception parts in each master and each slave are all constituted of the same functional circuit elements and are incorporated as single structural element respectively, irrespective of the number of corresponding masters or slaves.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an asynchronous serial communication system, and more particularly, to an asynchronous serial communication system formed by a master and a slave.

[0002]

2. Description of the Related Art Generally, as described above, an asynchronous serial communication system of this type mainly includes one or more masters for controlling the communication system and a plurality of slaves. The two-wire system is mainly used for data communication between internal devices including a microcomputer and the like built in the master and the slave. Normally, in order to enable simultaneous data reception during data transmission, the above-described two-wire full-duplex communication is performed. However, in many cases, data is transmitted. In communication operation, data transmission and data reception are often divided and operated by half-duplex communication. FIG. 6 shows a system configuration of an example of such a conventional asynchronous serial communication system.
As shown in FIG. 6, in the conventional example, masters 28 and 29 and slaves 30 and 31 communicating with the corresponding masters through the communication control action of these masters.
And 32.

The master 28 is composed of transmitting / receiving sections 28-1, 28-2 and 28-3 for transmitting and receiving data to and from a corresponding slave, and a data processing section 28-4 including a microcomputer or the like as control means. Is composed of
Similarly, master 29 transmits / receives data to / from a corresponding slave by transmitting / receiving sections 29-1, 29-2 and 29-2
-3 and a data processing unit 2 including a microcomputer and the like
9-4. Also, the slave 30
Includes a transmission / reception unit 30-1 and 30-2 for transmitting and receiving data to and from a corresponding master, and a microcomputer as a control unit, and a storage device having a ROM / RAM storage medium mounted thereon, or a reception device. Peripheral circuit unit 3 including a control unit for controlling other devices / systems based on data
Similarly, each of the other slaves 31 and 32 also includes the same number of transmitting / receiving units and peripheral circuit units. In the asynchronous serial communication system, data transmission and reception between the master and the slave is basically performed by a one-wire system or a two-wire system.
Although this is performed via a wire-type signal line, a two-wire system is generally used as described above. However, in FIG. 6, the signal lines are displayed in a simplified single line without distinction. As is apparent from FIG. 6, in this conventional example, each master and each slave are provided with a corresponding slave or a number of transmitting / receiving units corresponding to the number of masters.

[0006] In the asynchronous serial communication system shown in FIG. 6, examples of a transmission / reception unit included in the master and the slave are disclosed in, for example, Japanese Patent Application Laid-Open No. 05-22261. Communication and
A bidirectional communication device capable of performing switching between two-wire bidirectional communication and full-duplex communication is shown. In addition,
In the following, the two-way communication device will be referred to as a transmitting / receiving unit in conformity with FIG. FIG.
FIG. 3 is a block diagram showing a configuration of the transmission / reception unit, in which a transmission / reception unit 28-1 included in the master 28 is extracted and an internal configuration thereof is shown. The internal configuration of the transmission / reception unit included in the other masters and slaves is the same as that in the block diagram of FIG.

As shown in FIG. 7, a transmitting section 28-1 of the conventional example has a receiving terminal 48 for receiving and inputting data from a corresponding master or slave, and transmitting and outputting data to the corresponding master or slave. Transmitting terminal 4
9, corresponding to the data bus terminal 50 to which the data bus is connected to the internal data processing unit 28-4 and the internal data bus 51, a reception shift register 33 for receiving and storing received data, A reception buffer register for transferring and outputting predetermined bits of data to the data bus 51;
9, the transmission shift register 35 for outputting the stored transmission data, and the transmission shift register 35 for receiving the transmission data transferred from the data processing unit 28-4 via the data bus 51. 35, a baud rate generator 37 for generating and outputting a basic timing signal for transmission and reception, and receiving the basic timing signal and a start bit of received data to generate a reception clock signal during reception; A reception clock control circuit 38 for controlling the shift timing of the reception shift register 33; and a 1/16 frequency divider for dividing the frequency of the reception clock output from the reception clock control circuit 16 by 16 and outputting to the reception shift register 33 39,
At the time of transmission, a transmission clock is generated in response to the input of the basic timing signal, and a transmission clock control circuit 40 for controlling the shift timing of the transmission shift register 35, and the frequency of the transmission clock output from the transmission clock control circuit 40 is set to 16 A 1/16 frequency divider 41 that divides and outputs the data and a microcomputer (not shown) included in the data processing unit 28-4 issues a data transmission request according to a setting instruction transferred via the data bus 51. , A start bit detector 43 that receives the input of the received data and detects a start bit of the received data, and sets the operation mode to the master mode or the slave mode by the setting instruction by the microcomputer. Slave / master switching flag 44 for switching control
And a switch 45 that is turned on / off in accordance with the mode switching control by the slave / master switching flag 44, and receives a transmission clock output from the transmission clock control circuit 40 and outputs the transmission clock from the transmission shift register 35. A start bit generator 46 for outputting a start bit or a signal for defining the addition or prohibition of the addition of the start bit to the transmission data to be transmitted, and monitoring the start bit in accordance with a setting instruction by the microcomputer; And a reception permission flag 47 for controlling the transmission clock control circuit 40.

In FIG. 7, the operation mode of the transmission / reception unit 28-1 is the same as that of the data processing unit 2 transferred to the slave / master switching flag 44 via the data bus 50.
The setting is made in response to an instruction from the microcomputer included in 8-4. When the operation mode is set to the master mode according to the instruction of the microcomputer, the output of the start bit detected and generated by the start bit detector 43 is permitted, and the switch 45 is turned off. The control operation on the transmission clock control circuit 40 is prohibited, and the control operation on the reception clock control circuit 38 is permitted. Thus, in the master mode, the transmission data output from the transmission shift register 35 via the transmission terminal 49 is output in synchronization with the start bit output by the transmission shift register 35, and is also input via the reception terminal 47. The received data is sequentially input to the reception shift register 33 in synchronization with the start bit of the received data detected by the start bit detector 43. Also,
When the operation mode is set to the slave mode, the switch 45 is turned on, and the transmission clock control circuit 40 and the reception clock control circuit 3 based on the start bit are used.
8 and the start bit generator 46 prohibits additional output to the transmission terminal 49. Accordingly, in the slave mode, data transmission and reception performed via the transmission shift register 35 and the reception shift register 35 via the transmission terminal 49 and the reception terminal 48, respectively,
Both are performed in a state synchronized with the start bit of the received data output from the start bit detector 43.

Therefore, if the master 28 and the corresponding slave 30 communicate with each other when the master mode is set in each of the master 28 and the slave 30 when the master 28 and the corresponding slave 30 perform communication, Due to the operation function of the unit, the master 28 and the slave 30 are in an operation state in which two-wire bidirectional serial communication is performed, the master 28 is set in the master mode, and the slave 30 is set in the slave mode. In this case, the operation state is such that one-wire bidirectional serial communication is performed. This means that when communication is performed between the master 28 and the slave 31 or 32, the master 29 and the slave 30 or 31 or 32
The same applies to the case where communication is performed between the server and the server.

[0008]

In the above-mentioned conventional asynchronous serial communication system, there are a plurality of masters, and when performing one-wire bidirectional serial communication between the master and the slave, for example, as shown in FIG. 6, in an operation state in which communication is performed from the two master devices, the master 28 and the master 29, to one slave 30, the data transmission requests of both masters are in a conflicting state. As shown in FIG. 8, the data received from both masters are superimposed due to contention, and the data sent from master 28 (see FIG. 8A) and the data sent from master 29 (see FIG. 8A). 8
(See (b)) is completely different data (see FIG. 8 (c))
Transform into. Therefore, in the conventional asynchronous serial communication system, in order to maintain normal one-wire bidirectional serial communication between the master and the slave, the communication between the master and the slave in a one-to-one correspondence relationship. However, there is a disadvantage that it must be limited to

Further, it is necessary to provide the same number of transmitting / receiving units in each master according to the number of corresponding slaves, and the same number of transmitting / receiving units in each slave according to the number of corresponding masters. It is necessary to provide a part.
For this reason, there is a drawback that the device configuration scale in the master and the slave and the number of signal lines connecting them mutually increase, and the occupation area in the semiconductor chip forming the system increases.

[0010] Furthermore, although the right to issue a start bit is given to the master, a signal line is provided between the masters.
When asynchronous serial communication is performed between the masters, since the criterion for judging data during transmission and reception is not clear between the masters, the communication operation state is a two-wire bidirectional serial communication function between these masters. Therefore, there is a disadvantage that one-wire bidirectional serial communication cannot be selectively performed between masters.

[0011]

According to the present invention, there is provided an asynchronous serial communication system comprising at least one or more masters and at least one or more slaves. In the asynchronous serial communication system formed by connecting signal lines functioning as a single unit, a single transmitting / receiving unit having a bidirectional communication function of the same functional configuration as a data transmitting / receiving unit included in the master and the slave, It is characterized in that it is provided separately for each master and each slave.

The signal line is formed in the form of a data bus for interconnecting the transmitting and receiving means in each of the masters and the transmitting and receiving means in each of the slaves. Via an arbitrary master to the slaves
It is possible to perform line-type bidirectional data transmission and reception, and when there are a plurality of masters, perform one-line bidirectional data transmission and reception between the arbitrary masters via the data bus. May be enabled.

The transmission / reception means compares and compares own transmission data with data received on the data bus when transmission data is simultaneously output from the plurality of masters to the data bus, Data bit comparing means for determining whether or not the transmission data from itself can secure the data bus with reference to the comparison / collation result may be provided. If the transmission is successful, set “success” in the transmission success / failure setting means. If the data bus reservation by the transmission data fails, set “failure” in the transmission success / failure holding means. A success / failure setting means may be provided, and whether or not the data bus is in use is determined by detecting a use state of the data bus, and Bus monitoring means for suspending data transmission when data transmission is in use and starting data transmission when not in use. The use state of the data bus may be detected, and the start / hold / retransmission of data transmission may be appropriately executed according to the determination result.

Further, the transmission / reception means determines whether or not the data bus is in use by detecting a use state of the data bus, and suspends data transmission when the data bus is in use, A bus monitoring unit that performs a control operation so as to start data transmission when not in use is provided, and at the time of data transmission, the bus monitoring unit detects the use state of the data bus immediately before transmission, and In accordance with the determination result, the start / hold / retransmission of data transmission is appropriately executed, and a predetermined microcomputer functioning as a control means operates until a program detects that the data bus is not in use by a program. By setting release detection time information in advance,
The data transmission may be automatically performed with reference to the release detection time information.

[0015]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a system configuration according to an embodiment of the present invention. As shown in FIG. 1, masters 1 and 2 and corresponding masters are controlled through a communication control operation by these masters. Slaves 3 and 4 that communicate with
And 5 are provided. The master 1 transmits and receives data to and from a corresponding slave.
And a data processing unit 1-2 including a microcomputer (not shown) as control means, and the master 2 also has a transmission / reception unit 2-1 for transmitting / receiving data to / from a corresponding slave. , A data processing unit 2-2 including a microcomputer (not shown) as control means. Also, slave 3
Includes a transmission / reception unit 3-1 for transmitting / receiving data to / from a corresponding master, and a microcomputer as a control means, and a storage means having a ROM / RAM storage medium mounted thereon, or based on received data. It is constituted by a peripheral circuit section 3-2 including control means for controlling other devices / systems and the like. Similarly, each of the other slaves 4 and 5 is also constituted by a transmission / reception section and a peripheral circuit section.
Unlike the case of the above-described conventional example, in the present embodiment, the transmitting and receiving units in each master and each slave include:
Regardless of the number of masters and slaves that correspond to each other,
The equipment configuration is simplified by providing only a single transmission / reception unit, and signal lines between the master and the slave and between the masters are also set in a data bus format and integrated. As one application example, for example, when the present invention is applied to an asynchronous serial communication system formed on a semiconductor device, the size of the semiconductor chip can be reduced.

FIG. 2 is a block diagram showing one embodiment of a transmission / reception unit having the same configuration provided in common for each master and each slave. FIG. 2 is a block diagram illustrating a transmission / reception unit 1-1 included in FIG. In addition,
Just in case, the other master 2 and slaves 3-1 and 4-1
2 and the internal configuration of the transmitting / receiving unit included in 5-1 are exactly the same as those in the block diagram of FIG. As shown in FIG.
The transmission / reception unit 1-1 of this embodiment includes a reception shift register 6, a reception buffer register 7, a transmission shift register 8, and a reception terminal 23, a transmission terminal 24, a data bus terminal 25, and a data bus 27, respectively. A transmission buffer register 9, a rate generator 10, a reception clock control circuit 11, 1/16 frequency dividers 12 and 14, a transmission clock control circuit 13, a reception permission flag 15, a transmission request flag 16, It comprises a bit detector 17, a start bit generator 18, a slave / master switching flag 19, a bit comparison circuit 20, a transmission success / failure flag 21, and a bus monitoring circuit 22. The bit comparison circuit 20, the transmission success / failure flag 21, and the bus monitoring circuit 22 are circuits newly added in the present invention.

In the above configuration, the reception shift register 6, the reception buffer register 7, the transmission shift register 8, the transmission buffer register 9, the baud rate generator 10, the reception clock control circuit 11, the 1/16 frequency divider 12, The operation functions of a transmission clock control circuit 13, a reception permission flag 15, a transmission request flag 16, a start bit detector 17, a slave / master switching flag 19, and the like are the same as those of the conventional example.
Reception shift register 33, reception buffer register 34,
The transmission shift register 35, the transmission buffer register 36,
Baud rate generator 37, reception clock control circuit 38, 1/16 frequency dividers 39 and 41, transmission clock control circuit 40, transmission request flag 42, start bit detector 43, slave / master switching flag 44, reception permission flag 47, etc. The operation functions of the components having the same names as those of the conventional example are the same as those of the above-described conventional example. In the following, the operation functions of the respective components common to the conventional example and the related operation contents will be described. Are omitted in order to avoid duplication and redundancy. In particular, the bit comparison circuit 20, the transmission success / failure flag 21, and the bus monitoring circuit 22, which are newly added in the present invention, have characteristics. The relevant operation contents will be mainly described.

As an example of the description of the operation of the present embodiment, first, a case will be described in which the data transmission timings of the master 1 and the master 2 match, and data is transmitted and output to the slave 3 at the same time. And Since the transmitting and receiving units included in the masters 1 and 2 and the slave 3 have the same configuration as described above, the transmitting and receiving units will be described with reference to FIG. . 3 (a), 3 (b) and 3 (c), FIG.
(A), (b) and (c), and FIG.
(B) and (c) are operation timing diagrams each showing an 8-bit data waveform in the above operation state. 3 (a), 4 (a) and 5 (a)
FIG. 3 shows transmission data of the master 1, transmission data of the master 2, and data received by the slave 3, respectively. FIG. 3 shows a data race condition when the start bit timings of the transmission bit data of both masters match. FIG. 4 shows a data race condition when the timings of the start bits of the transmission bit data of both masters are shifted, and FIG. 5 shows an operation timing diagram when the data race is avoided. .

As described above, since the data transmission timings of the master 1 and the master 2 match, the low-level start bit S of the transmission data “11010100” of the master 1 and the transmission data “111101010” of the master 2 The timings also match (see FIGS. 3A and 3B). When data transmission to the slave 3 occurs in the master 1 and the master 2, the start bit S of the data of both masters is detected by the start bit detector 17 in FIG. , And the slave 3 starts data reception. Following the start bit S, the bit data # 1 in the transmission shift register 8 is transmitted and output from both masters as shown in FIGS. 3A and 3B. The data “1” on the data bus input via the terminal 23 is stored in the reception shift register 6 and is also input to the bit comparison circuit 20 via the reception shift register 6.

Here, the operation of the bit comparison circuit 20 and the transmission success / failure flag 21 according to the present invention will be briefly described prior to the operation example. In the present invention, in the bit comparison circuit 20, the data bits transmitted and output from the transmission shift register 8 and the bit data input from the reception shift register 6 are compared and collated on a bit-by-bit level. Is determined. In the comparison result, when all bits of the transmission data and the reception data match each other, the transmission data does not compete with the transmission data of another master via the corresponding data bus. Is determined to have been successfully transmitted in the normal state, the determination result is set to the transmission success / failure flag 21 as “success”, and data transmission is continuously performed. When all bits of the transmission data and the reception data do not match in the comparison result, it is determined that the reception data received and input to the reception shift register 6 is transmission data from another master. The bit comparison circuit 20
As a result, a transmission stop control signal is sent to the transmission clock control circuit 13, the data transmission from the master is stopped, the data bus is released, and the bit comparison circuit 2
A determination result of 0 is set in the transmission success / failure flag 21 as “failure”. This is exactly the same in the transmission / reception unit 2-1 in the master 2. Therefore, in the present embodiment, even in an operation state in which data is simultaneously transmitted and output from a plurality of masters, a bit comparison circuit is provided in the transmission / reception unit in the master, and the transmission data is received by the bit comparison circuit. By judging whether or not the data signal on the data bus is the same data, unnecessary data race condition on the data bus is avoided, and the asynchronous serial communication can be normally maintained.

The two start bits S described above correspond to FIG.
As shown in (b) and (b), in the operation example at the same timing, the bit data # 1 transmitted and output from the masters 1 and 2 are both "1" and coincide with each other. The comparison circuit 20 secures the data bus, determines that the transmission was successful, and continues the transmission. Then, in the slave 3 in the reception operation state, the bit data “1” is received and input via the reception terminal 23 of the transmission / reception unit 3-1.
It is stored in the reception shift register 6. In this operation state, the bit comparison circuit 20 does not operate in the transmission / reception unit 3-1 of the slave device 3 in the reception operation state. This is the same as shown in FIGS. 3A and 3B at the timing of transmitting and outputting the bit data # 2. Since the bits of the transmission data of both masters are the same, The operation state is the same as that of. However, at the timing when bit data # 3 is transmitted and output, data bit “0” is transmitted and output from master 1, and data bit “1” is transmitted and output from master 2. In this case, as described above, since both transmission data have the same timing, the data bit of the transmission data on the data bus is logically ANDed to “0”, and in response to this, the master 1 , The transmission is determined to be successful by the bit comparison circuit 20 and the transmission operation is continuously performed.
As a result, the transmission is determined to be unsuccessful, the transmission is stopped, and the slave 3 enters the operation state in which the transmission data of the master 1 is received. After this operation state, all the transmission data from the master 1 is received by the slave 3, and the asynchronous serial communication is normally maintained. As shown, the transmission data “11010” from the master 1
100 "is received as normal data.

In the present invention, the bus monitoring circuit 2
By detecting the state of the data on the data bus immediately before the data transmission, it is determined whether or not the data bus is in use. If the data bus is not in use, the data transmission is stopped. Data transmission is suspended if it is started and in use. Then, after the transmission start is suspended, when the signal line monitoring circuit 22 determines the release state of the data bus, the data transmission is restarted again. As a control function of the bus monitoring circuit 22, for example, in the case of the master device 1, a microcomputer (not shown) functioning as a control unit included in the data processing unit 1-2 via the data bus 27 in the transmission / reception unit In), by setting in advance the time until the signal line release is detected by the program, it is possible to automatically detect the signal line release via the signal line monitoring circuit 22. , The data transmission from the master device 1 can be automatically performed. This is the same in the transmission / reception unit 2-1 of the master device 2 and also in the transmission / reception units 3-1 4-1 and 5-1 of the slave devices 3, 4 and 5. Therefore, in the present embodiment, in the one-wire asynchronous communication, even when there are a plurality of master devices, the one-wire asynchronous communication system can appropriately communicate with any slave device. Can be configured.

In connection with the operation function of the bus monitoring circuit 22, an operation in the case where the data transmission timing of each master slightly fluctuates will be described. As an operation example,
The operation in the master 2 when data transmission is started in the master 1 and subsequently data transmission is started in the master 2 will be described. At the start of transmission, the master 2 first transmits a predetermined transmission request signal to the bus monitoring circuit 22 from the transmission request flag 16 provided in the transmission / reception unit. The state of the received data at the terminal 23 is detected, and it is determined whether or not the data bus can be used. At this time, the receiving state at the receiving terminal 23 is “0” in response to the input of the low-level start bit S from the master 1, whereby the corresponding data bus is set by the bus monitoring circuit 22. It is determined that the bus is not in the bus release state, but is occupied and in use by the master 1, and the start of data transmission is suspended until the data bus enters the release state.
Accordingly, in this case, as shown in FIGS. 4A, 4B and 4C, the data from the master 1 is
The data is transmitted as it is and received by the slave 3. When the data bus enters the release state, a transmission request signal is input from the bus monitoring circuit 22 to the transmission clock circuit 13, and data transmission is started. The same applies to the case where the transmission start is preceded by the master 2. In this case, the transmission data from the master 2 is transmitted to the slave 3. Therefore, in the present invention, by providing the bus monitoring circuit 22 in the transmission / reception unit, it is possible to avoid a data race condition on the data bus beforehand by monitoring the data reception state at the reception terminal during data transmission. It becomes possible.

FIGS. 5A, 5B and 5C show a state in which data transmission by the master 1 has been started and the start bit S has been transmitted and output, and the master 2 has detected the start bit. FIG. 7 is a timing chart corresponding to an operation example when data transmission is to be started. Note that the relationship between the times t ₁ , t ₂ and t ₃ in FIG. 5 is t ₁ = t ₂ and t ₃ = 2t ₁ . In this case, the start bit S is transmitted and output from the master 1, and the transmission start is suspended in the master 2 according to the determination by the bus monitor circuit 22, as described above. Detector 17
Is detected. Then, during a time t ₁ after the detection of the start bit, the master 2 sets the transmission request flag 16 to start data transmission. Is ready for transmission. However,
Subsequently, during the time t ₂ at time t ₁ after the start bit S to be transmitted output from the master 1 again
Is detected, after the start bit S is detected,
During the addition time t _3, the start of the data transmission is suspended. Then, after the elapse of the time t _3, the bus release state is detected by the bus monitoring circuit 22 of the master 2, and data transmission to the data bus is started. In this case, in the control microcomputer included in the data processing unit 2-2, if the time required until the bus release is set in advance by a program, the data bus 27 in the transmission / reception unit is set. With reference to the time information transmitted from the data processing unit 2-2 via the
It is also possible to start the data transmission automatically and efficiently,

[0026]

As described above, according to the present invention, the data transmission / reception means of the master and the slave compare and compare their own transmission bit and data on the data bus at the bit level, and release the data bus. Bit comparison means for judging the state, bus monitoring means for monitoring the state of data received from the data bus to judge whether transmission can be started, and transmission success / failure for setting success or failure of securing the data bus by transmission data By adding a flag and making the signal line between the master and the master-slave a data bus, it is possible to obtain the effect that bidirectional serial communication can be performed between any master and slave. If the number of transmission / reception means in the slave can be unified, it is possible to reduce the device configuration scale There is a cormorant effect.

In addition, when the device is constituted by a semiconductor device, there is an effect that the size of the semiconductor chip can be reduced.

Further, in the present invention, by providing the above-mentioned additional means in the transmitting / receiving means, there is an effect that asynchronous serial communication can be performed between masters.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a transmission / reception unit included in a master device / slave device of the present embodiment.

FIG. 3 is a timing chart (1) showing a data race condition in the first embodiment.

FIG. 4 is a timing chart (2) showing a data race condition in the first embodiment.

FIG. 5 is a timing chart (3) showing a data race condition in the first embodiment.

FIG. 6 is a block diagram showing a system configuration of a conventional example.

FIG. 7 is a timing chart showing a data race condition in a conventional example.

[Explanation of symbols]

1,2,28,29 Master 1-1,2-1,3-1,4-1,5-1,28-1
28-3, 29-1 to 19-3, 30-1, 30-2,
31-1, 31-2, 32-1, 32-2 transmitting / receiving section 1-2, 2-2, 28-4, 29-4 data processing section 3, 4, 5, 30, 31, 32 slave 3-2 , 4-2, 5-2, 30-3, 31-3, 32-
3 Peripheral circuit section 6, 33 Reception shift register 7, 34 Reception buffer register 8, 35 Reception shift register 9, 36 Transmission buffer register 10, 37 Baud rate generator 11, 38 Reception clock control circuit 12, 14, 39, 411 / 16 frequency divider 13, 40 Transmission clock control circuit 15, 47 Reception permission flag 16, 42 Transmission request flag 17, 43 Start bit detector 18, 46 Start bit generator 19, 44 Slave / master switching flag 20 Bit comparison circuit 21 Transmission success / failure flag 22 Bus monitoring circuit 23, 48 Reception terminal 24, 49 Transmission terminal 25, 50 Data bus terminal 27, 51 Data bus 45 Switch

Claims (6)

[Claims] 1. An asynchronous system comprising at least one or more masters and at least one or more slaves, wherein a signal line functioning as a data transmission is connected between the master and the slaves. In the serial communication system, as the data transmitting / receiving means included in the master and the slave, a single transmitting / receiving means having a bidirectional communication function having the same functional configuration is individually provided for each master and each slave. Asynchronous serial communication method. 2. The signal line is formed in the form of a data bus for interconnecting transmission / reception means in each of the masters and transmission / reception means in each of the slaves. Through a single-wire bidirectional data transmission / reception from any master to the plurality of slaves, and when there is a plurality of masters, the 2. The asynchronous serial communication system according to claim 1, wherein one-wire bidirectional data transmission / reception can be performed via a data bus. 3. The transmission / reception means, when transmission data is simultaneously output from a plurality of masters to the data bus, compares and compares its own transmission data with the data on the received data bus. 3. The asynchronous serial communication according to claim 2, further comprising a data bit comparing unit that determines whether or not the transmission data from itself can secure the data bus by referring to the comparison and collation result. method. 4. The transmission / reception means sets "success" in the transmission success / failure setting means when the data bus is secured by its own transmission data, and the data bus securing by the transmission data fails. 4. The asynchronous serial communication system according to claim 2, further comprising a transmission success / failure setting means for setting "failure" in the transmission success / failure holding means in the case. 5. The transmission / reception means judges whether or not the data bus is in use by detecting a use state of the data bus. If the data bus is in use, data transmission is suspended, and A bus monitoring unit that performs a control operation so as to start data transmission when the data transmission is not being performed; and when the data is transmitted, the bus monitoring unit detects a use state of the data bus immediately before the transmission, and determines the state. 5. The asynchronous serial communication system according to claim 2, wherein start / hold / retransmission of data transmission is appropriately performed according to a result. 6. The transmission / reception means judges whether or not the data bus is in use by detecting the use state of the data bus. If the data bus is in use, the data transmission is suspended, and A bus monitoring unit that performs a control operation so as to start data transmission when the data transmission is not being performed; and when the data is transmitted, the bus monitoring unit detects a use state of the data bus immediately before the transmission, and determines the state. In accordance with the result, the start / hold / retransmission of data transmission is appropriately executed, and the release until the data bus detects that the data bus is not in use by a predetermined microcomputer which functions as a control means. By setting detection time information in advance, data transmission is automatically started with reference to the release detection time information. 5. The asynchronous serial communication system according to claim 2, claim 3, or claim 4.