JPH0591080A - Communication controller - Google Patents

Abstract

PURPOSE:To attain loopback connection between different line adaptors with respect to the communication controller provided with a function implementing multiplexing and demultiplexing to data sent/received by a line adaptor section and implementing loopback connection in its inside. CONSTITUTION:A loop control section 6 receives the count of a reception frame outputted from a reception time slot counter section 2 when a flip-flop 7 is set and a loop control signal commanding loopback connection is set and outputs a signal in which the least significant bit of the inputted count is inverted. When the flip-flop 7 is reset and the loopback connection is released, the loop control section 6 outputs an output of the reception time slot counter section 2 as it is. A time slot number comparison section 4 compares the output of the loop control section 6 with the content of the time slot number latch section 5. The time slot number comparison section 3 compares the output of a transmission time slot counter section 1 with the content of the time slot number latch section 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control apparatus for connecting transmission data to a time division multiplexing line to its own reception data and looping back connection of data of a certain time slot to another time slot. In recent years, ISDN (Integrated
With the start of services (Services Digital Network), communication control devices that multiplex multiple lines have become popular. As a means for verifying each circuit of such a communication control device, there is a demand for using the conventional line verification program as it is.

[0002]

2. Description of the Related Art FIG. 15 is a block diagram of a communication control device. In FIG. 15, the communication control device 51 is replaced by the CPU unit 2
8 and the demultiplexing adapter unit 27. C
The PU unit 28 converts the data processed by the CPU into the data processed by the line and the line corresponding unit 32.
Have. There are a plurality of line-corresponding units 32 that function in the same manner, and each disassembles and assembles transmission / reception data, and serves as an interface between the transmission / reception control unit 31 and the CPU interface. The demultiplexing adapter unit 27 has a transmission / reception control unit 31 that multiplexes and demultiplexes transmission / reception data, a frame control unit 30 that controls a transmission / reception frame, and a driver receiver unit 29 that serves as an electrical interface with a multiplexing line.

When the return connection is designated, the transmission / reception control unit 31 turns on the loop control signal. When this is turned on, the selector 50 selects and outputs the transmission data output by the latter frame control unit 30 from the reception data output by the driver receiver unit 29 and the transmission data output by the frame control unit 30. The frame controller 30 sends the output of the selector 50 to the transmission / reception controller 31 as received data.

FIG. 16 is a diagram for explaining a conventional technique.
In FIG. 16, each unit 33 to 4 constituting the transmission / reception control unit
2, 43a to 43n and line corresponding units 44a to 44n are shown. The flip-flop 38 is set by a control program or a switch of the CPU unit, and is in a set state when the return connection is designated. The transmission time slot counter unit 33 counts the transmission timing signal transmitted by the frame control unit and outputs the count value. The reception time slot counter section 34 counts the reception timing signals sent by the frame control section and outputs the count value.

The demultiplexing control units 43a to 43n are provided for each of the line corresponding units 44a to 44n. In FIG. 16, the internal configurations of the demultiplexing control unit and the line corresponding unit are shown only for the demultiplexing control unit 43a and the line corresponding unit 44a. Others 43b to 43n and 44b to 44n have the same internal configuration, although not shown. The time slot number holding unit 37 has a line interface unit 44.
Record the time slot number used by a. The time slot number comparison unit 35 compares the output of the transmission time slot counter unit 33 and the contents of the time slot number holding unit 37. If the comparison results are in agreement, the transmission permission signal is turned on, and the line interface 44a is used in that time slot.
Controls to output the transmission data. The time slot number comparison unit 36 uses the reception time slot counter unit 3
4 is compared with the contents of the time slot number holding unit 37. If the comparison results are in agreement, the reception permission signal is turned on, and the line interface 44a is controlled to input the reception data in that time slot.

An 8-bit transmission character is set in the transmission buffer 41 constituting the line interface 44a by the control program of the CPU. The shift register 42 decomposes the 8-bit transmission character and sends 8-bit data to the line one bit at a time. 8 shift registers 42
An interrupt occurs when the bit shift operation is completed. The next transmission character is set in the transmission buffer 41. Line data is shifted and input to the shift register 39 bit by bit. When the shift register 39 completes the 8-bit shift operation, an interrupt occurs. The contents of the shift register 39 are transferred to the reception buffer 40, and the reception buffer 40
The received character is set in.

[0007]

In FIG. 16, each of the demultiplexing control units 43a to 43n has a line interface unit 4 forming a pair.
It holds the time slot numbers used by 4a to 44n. Since the transmission / reception timing is determined by the time slot number, when the flip-flop 38 is set and the loop connection is made, the transmission character sent by a certain line corresponding part becomes the received character received by the same line corresponding part. Therefore, in the conventional technology, it is possible to verify full-duplex communication,
At the same time, there was a problem in that it was not possible to verify half-duplex communication, in which bidirectional communication was not possible.

In view of the above conventional problems, the present invention converts the time slot number used by the line interface unit.
(EN) Provided is a communication control device in which a transmission character transmitted by a line corresponding unit can be received by another line corresponding unit by changing the time slot numbers of the transmitting side and the receiving side to be different. With the goal.

[0009]

According to the invention, the above mentioned objects are achieved by means of the patent claims.

That is, the invention of claim 1 is connected to a multiplexing line and comprises a CPU section and a demultiplexing adapter section,
The CPU unit has a plurality of line corresponding units for disassembling and assembling transmitted / received data, and the demultiplexing adapter unit has a driver / receiver unit for electrically interfacing with the multiplexed line and a frame control for controlling a transmitted / received frame. And a transmission / reception control unit that multiplexes and demultiplexes transmission / reception data, the transmission / reception control unit including a transmission time slot counter unit that counts time slots of a transmission frame and a reception time slot that counts time slots of a reception frame. A counter unit, a register for instructing loopback of transmission data to be multiplexed, and a plurality of demultiplexing control units provided for each of the line corresponding units, and the demultiplexing control unit includes:
Prepared by the line interface when the contents of the time slot number holding unit that stores the time slot number used by the line interface corresponding to the pair and the contents of the time slot number holding unit and the output of the transmission time slot counter unit match. When the contents of the time slot number holding unit and the output of the reception time slot counter unit match, the received data is sent to the line interface unit. In a communication control device comprising a second time slot number comparison unit for instructing to capture, when the register instructs return, either the transmission time slot counter unit or the reception time slot counter unit outputs Is a communication control device provided with a loop control unit for inverting the least significant bit of the count value of

According to a second aspect of the invention, the circuit is connected to a multiplexed line,
A CPU unit and a demultiplexing adapter unit, and the CPU
The unit has a plurality of line corresponding units for disassembling and assembling transmitted / received data, and the demultiplexing adapter unit has a driver / receiver unit for electrical interface with the multiplexed line, and a frame control unit for controlling the transmitted / received frame. A transmission / reception control unit that multiplexes and demultiplexes transmission / reception data, the transmission / reception control unit counting a time slot of a transmission frame and a reception time slot counter unit counting a time slot of a reception frame. And a register for instructing loopback of transmission data to be multiplexed, and a plurality of demultiplexing control units provided for each line corresponding unit, wherein the demultiplexing control unit is a time slot number used by a pair of line corresponding units. And a content of the time slot number holding unit and the transmission target. A first time slot number comparison unit for instructing to output the transmission data line interface is provided when the output of the beam slot counter matches,
A communication control device comprising a second time slot number comparison unit for instructing the line interface to fetch received data when the contents of the time slot number holding unit match the output of the reception time slot counter unit. In the first time slot number holding unit referred to by the first time slot number comparison unit, the second time slot number holding unit referred to by the second time slot number comparison unit, the first and And a means for arbitrarily changing the contents of the second time slot number holding unit.

[0012]

FIG. 1 is a diagram for explaining the principle of the invention of claim 1.
The invention configuration shown in FIG. 1 is a configuration in which a loop control unit 6 is added to the configuration of the above-described conventional technique. Other than the loop control unit 6, each unit 1 to 5, 7 to 11, 12a to 1 shown in FIG.
2n and 13a to 13n operate in the same manner as described in the related art. When the flip-flop 7 is in the set state and the loop control signal for instructing the loopback connection is turned on, the loop control unit 6 inputs the count value of the reception frame output by the reception time slot counter unit 2,
The inverted least significant bit of the input count value is output. When the flip-flop 7 is in the reset state and the return connection is released, the loop control unit 6 outputs the output of the reception time slot counter unit 2 as it is.

The time slot number comparison unit 4 compares the output of the loop control unit 6 with the contents of the time slot number holding unit 5. The time slot number comparison unit 3 compares the output of the transmission time slot counter unit 1 with the contents of the time slot number holding unit 5. It should be noted that even if the loop control unit 6 is added to the transmission time slot counter unit 1 side, the same operational effect is produced. In this case, the time slot number comparison unit 3 compares the output of the loop control unit 6 with the contents of the time slot number holding unit 5. Then, the time slot number comparison unit 4 compares the output of the reception time slot counter unit 2 with the content of the time slot number holding unit 5.

FIG. 2 is a diagram for explaining the principle of the invention of claim 2. In the invention of claim 2, the time slot number comparison unit 1
Time slot number holding units 18 and 19 are provided respectively for 6 and 17. Two time slot number holding units 18, 1
The contents of 9 can be arbitrarily changed through the control program of the CPU section. In FIG. 2, the time slot number comparison unit 16 includes a transmission time slot counter unit 14
And the contents of the transmission time slot number holding unit 18 are compared. The time slot number comparison unit 17 compares the output of the reception time slot counter unit 15 with the content of the reception time slot number holding unit 19.

[0015]

3 to 5 are timing charts for explaining the operation of the invention shown in FIG. 1 in the non-loop state. In the non-loop state, the flip-flop 7 shown in FIG. 1 is in the reset state and the loop control signal is off. Therefore, the loop control unit 6 outputs the output of the reception time slot counter unit 2 as it is. Line interface α
Uses the time slot number “0” and
Uses the time slot number “1”. Illustration of other line-corresponding units is omitted.

The clock signal, transmission timing signal, reception timing signal, and multiplexed reception data shown in FIGS. 3 to 5 are sent from the frame control section to the transmission / reception control section. The multiplexed transmission data is sent from the transmission / reception control unit to the frame control unit. In FIG. 3, when the transmission timing signal is turned on, the transmission time slot counter starts counting transmission frames. At the same time, the transmission bit counter starts counting the transmission bits, with one time slot having an 8-bit length. When the reception timing signal is turned on, the reception time slot counter starts counting received frames. At the same time, the received bit counter is 1
Counting of received bits has started, assuming that the time slot is 8 bits long. When the clock cycle is τ, in this embodiment, there is a delay of 4τ from when the transmission timing signal is turned on to when the reception timing signal is turned on.

The line interface α uses the time slot number "0". Therefore, when the transmission time slot counter is counting "0", the transmission permission signal for the line interface α is turned on. During this time, the transmission character set in the transmission buffer is transferred to the shift register, and the shift register performs a shift operation, so that the line interface α
The transmission character is output from. This transmission character constitutes multiplexed transmission data together with the transmission character output by the line interface β when the transmission time slot counter is counting “1”.

When the loop control signal is off, the loop control section outputs the output of the reception time slot counter as it is. When the output of the loop controller is "0", the line corresponding unit α takes in the reception permission signal, so that the multiplexed reception data appearing on the line at that time is fetched by 8 bits using the shift register. The received characters captured by the shift register are transferred to the receive buffer. Similarly, the line interface β performs the receiving operation when the output of the loop controller is “1”. Note that FIG. 4 is a diagram continuing from the rear part of FIG. 3, and FIG. 5 shows the start of the next frame.

6 to 8 are timing charts for explaining the operation of the invention shown in FIG. 1 in the loop. During the loop, the flip-flop 7 shown in FIG. 1 is in the set state and the loop control signal is on.
Therefore, the loop control unit 6 inputs the count value output by the reception time slot counter unit 2, and outputs the inverted least significant bit of the count value. As shown in FIGS. 6 to 8, the loop control unit 6 inputs “0” and outputs “1”, inputs “1” and outputs “0”, and inputs “2”. "3" is output.

As a result, during the loop, the reception permission signal of the line interface α is turned on when the reception time slot counter is counting "1". Further, the reception permission signal of the line interface β is turned on when the reception time slot counter is counting “0”. Therefore, the return connection is made between the adjacent line corresponding units α and β. Note that FIG. 7 is a diagram continued from the rear part of FIG. 6, and FIG. 8 shows the start of the next frame.

FIGS. 9 to 11 show FIG. 2 in the non-loop state.
5 is a timing chart for explaining the operation of the invention shown in FIG. 9 to 11, “0” is stored in the transmission time slot number holding unit of the demultiplexing control unit for the line corresponding unit γ, and “0” is stored in the reception time slot number holding unit. Further, “1” is stored in the transmission time slot number holding unit of the demultiplexing control unit for the line corresponding unit δ,
"1" is also stored in the reception time slot number holding unit. Illustration of other line-corresponding units is omitted.

In the non-loop state, the flip-flop 20 shown in FIG. 2 is in the reset state and the loop control signal is off. The line corresponding unit γ performs the transmission operation when the transmission time slot counter is “0” and the reception operation when the reception time slot counter is “0”.
The transmission time slot counter of the line interface δ is “1”.
When the reception time slot counter is "1", the reception operation is performed. Note that FIG.
Indicates that the frame following the frame shown in FIGS. 9 and 10 starts.

12 to 14 are diagrams shown in FIG.
5 is a timing chart for explaining the operation of the invention shown in FIG. 12 to 14, “0” is stored in the transmission time slot number holding unit of the demultiplexing control unit for the line corresponding unit γ, and “1” is stored in the reception time slot number holding unit. Further, “1” is stored in the transmission time slot number holding unit of the demultiplexing control unit for the line corresponding unit δ,
“0” is stored in the reception time slot number holding unit. During the loop, the flip-flop 20 shown in FIG. 2 is in the set state and the loop control signal is on.

Therefore, when the transmission time slot counter is "0", the transmission character output from the line corresponding part γ is folded and appears in the multiplexed reception data after a delay of 4τ. This is received by the line interface δ whose reception permission signal is turned on when the reception time slot counter is “0”. The transmission character output by the line interface δ is received by the line interface γ connected back to the line interface δ by the same principle.

[0025]

As described above, according to the present invention,
Since the time slot numbers to be compared can be converted or changed, it is possible to perform a loopback test by connecting adjacent or arbitrary line corresponding units. Therefore, not only full-duplex communication but also half-duplex communication can be verified.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the invention of claim 1;

FIG. 2 is a diagram for explaining the principle of the invention of claim 2;

FIG. 3 is a timing chart illustrating the operation of the invention shown in FIG. 1 in the non-loop state.

FIG. 4 is a timing chart that follows FIG.

FIG. 5 is a timing chart diagram following FIG. 4;

FIG. 6 is a timing chart for explaining the operation of the invention shown in FIG. 1 in a loop.

FIG. 7 is a timing chart diagram following FIG. 6;

8 is a timing chart following FIG. 7. FIG.

9 is a timing chart illustrating the operation of the invention shown in FIG. 2 in the non-loop state.

FIG. 10 is a timing chart diagram following FIG. 9;

FIG. 11 is a timing chart diagram following FIG. 10;

FIG. 12 is a timing chart illustrating the operation of the invention shown in FIG. 2 during a loop.

13 is a timing chart that follows FIG.

FIG. 14 is a timing chart diagram following FIG. 13;

FIG. 15 is a block diagram of a communication control device.

FIG. 16 is a diagram illustrating a conventional technique.

[Explanation of symbols]

1, 14, 33 Transmission time slot counter section 2, 15, 34 Reception time slot counter section 3, 4, 16, 17, 35, 36 Time slot number comparison section 5, 37 Time slot number holding section 6 Loop control section 7, 20, 38 Flip-flop 8, 11, 12, 24, 39, 42 Shift register 9, 22, 40 Reception buffer 10, 23, 41 Transmission buffer 12a-12n, 25a-25n, 43a-43n
Demultiplexing control unit 13a to 13n, 26a to 26n, 32, 44a to 44
n line support unit 18 transmission time slot number holding unit 19 reception time slot number holding unit 27 demultiplexing adapter unit 28 CPU unit 29 driver receiver unit 30 frame control unit 31 transmission / reception control unit 50 selector 51 communication control device

Claims (2)

[Claims] 1. A connection to a multiplexed line, comprising a CPU section and a demultiplexing adapter section, said CPU section having a plurality of line corresponding sections for disassembling and assembling transmitted and received data,
The demultiplexing adapter unit has a driver / receiver unit that electrically interfaces with the multiplexed line, a frame control unit that controls a transmission / reception frame, and a transmission / reception control unit that multiplexes and demultiplexes transmission / reception data. The control unit includes a transmission time slot counter unit for counting the time slots of the transmission frame, a reception time slot counter unit for counting the time slots of the reception frame, a register for instructing loopback of the transmission data to be multiplexed, and each line interface unit. And a plurality of demultiplexing control units, each of which includes a time slot number holding unit that stores a time slot number used by a pair of line corresponding units, and the contents of the time slot number holding unit. Prepared by the line interface when the output of the transmission time slot counter matches. When the contents of the first time slot number comparison unit for instructing to output the received data and the contents of the time slot number holding unit and the output of the reception time slot counter unit match, the received data is fetched into the line corresponding unit. And a second time slot number comparison unit for instructing the above, in the case where the register instructs the loopback, either the transmission time slot counter unit or the reception time slot counter unit outputs A communication control device comprising a loop control unit for inverting a least significant bit of a count value. 2. A CPU unit and a demultiplexing adapter unit connected to a multiplexing line, said CPU unit having a plurality of line corresponding units for disassembling and assembling transmission / reception data,
The demultiplexing adapter unit has a driver / receiver unit that electrically interfaces with the multiplexed line, a frame control unit that controls a transmission / reception frame, and a transmission / reception control unit that multiplexes and demultiplexes transmission / reception data. The control unit includes a transmission time slot counter unit for counting the time slots of the transmission frame, a reception time slot counter unit for counting the time slots of the reception frame, a register for instructing loopback of the transmission data to be multiplexed, and each line interface unit. And a plurality of demultiplexing control units, each of which includes a time slot number holding unit that stores a time slot number used by a pair of line corresponding units, and the contents of the time slot number holding unit. Prepared by the line interface when the output of the transmission time slot counter matches. When the contents of the first time slot number comparison unit for instructing to output the received data and the contents of the time slot number holding unit and the output of the reception time slot counter unit match, the received data is fetched into the line corresponding unit. In a communication control device comprising a second time slot number comparison unit for instructing, a first time slot number holding unit referred to by the first time slot number comparison unit, and the second time slot number. A communication control device comprising: a second time slot number holding unit referred to by the comparison unit; and means for arbitrarily changing the contents of the first and second time slot number holding units.