CN115729149A - Multi-board-card synchronous sampling device based on JESD204B protocol - Google Patents

Abstract

The invention discloses a multi-board synchronous sampling device based on a JESD204B protocol, which mainly solves the problem of synchronous sampling caused by the fact that ADC chips based on the JESD204B protocol are distributed on multiple boards. The device comprises a synchronous control board and intermediate frequency sampling boards, wherein the synchronous control board completes synchronous control of clocks of all the intermediate frequency sampling boards, and is the key for realizing synchronous sampling of all the intermediate frequency sampling boards. All the intermediate frequency sampling plates are consistent in hardware design, and a multi-channel sampling function can be realized. The invention can meet the miniaturization design of the sampling module and is easy for channel expansion. Meanwhile, the device is powered on, synchronous sampling of all intermediate frequency sampling plates can be achieved, the synchronous stability is good, and the additional step of clock phase adjustment is avoided.

Description

Multi-board-card synchronous sampling device based on JESD204B protocol

Technical Field

The invention belongs to the synchronous sampling technology of an analog-to-digital converter, and particularly relates to a multi-board synchronous sampling device based on a JESD204B protocol.

Background

The ADC sampling technology is widely applied to the detection fields of radar, communication, electronic warfare, medical imaging and the like. With the improvement of the ADC resolution and the sampling rate, the conventional LVDS (low voltage differential signaling) parallel interface protocol is increasingly unable to meet the requirement of higher-rate data transmission. In order to meet the requirement of higher transmission rate of ADC, the joint electronic device engineering committee proposed JESD204B protocol, which is a serial interface protocol and is mainly used for data transmission between ADC/DAC (analog-digital/digital-analog converter) and logic devices. Compared with the LVDS interface protocol, the rate bandwidth of the JESD204B protocol is up to 12.5G, and data pins on an ADC chip are reduced, so that the circuit layout design is facilitated. Although the advantages of the ADC chip based on the JESD204B protocol are significant in terms of transmission rate and chip size, it requires an additional synchronous reference clock, increasing the complexity of the hardware system.

Furthermore, due to manufacturing process variations, more than 2 ADCs typically have sampling asynchrony during the power-up cycle, which is characterized by sampling data with different time delays. In order to solve the problem of synchronous sampling of more than 2 ADCs, many researchers have conducted related research on a single board card using an ADC chip based on the JESD204B protocol. Chenyang et al verified synchronous sampling of 8 ADCs on a single board in "application of synchronous acquisition technique for downward of phased array radar based on JESD204B protocol", and Huang Runlong proposed a synchronous sampling device using 24 ADCs on a single board in patent CN 211264148U.

As the number of ADC chips expands further, limited by the board size, more ADC chips will be distributed on different boards. Compared with a single board card, the data transmission link between different board cards is longer, and higher synchronous sampling difficulty is brought. In order to solve the problem of synchronous sampling among multiple board cards, liu renhua provides a master-slave board card architecture in 'design and implementation of a multi-path radio frequency synchronous acquisition system', and synchronous sampling among the boards is ensured by a clock from the master board card. However, as the number of slave boards is further expanded, the number of clocks output on the master board also needs to be increased, and redundancy of design on hardware is increased. Meanwhile, the clock phase on the slave board card needs to be adjusted for many times, and the synchronization speed is low. The patent CN108134607A by tremolo et al proposes an ADC synchronous sampling circuit and a synchronization method between boards, but it also needs an additional synchronization method to adjust the relative phase relationship between the sampling clock output by the HM7043 chip on the acquisition board and the reference clock to obtain the relative timing requirement, and increase the time for achieving synchronous sampling between boards.

In summary, in the existing ADC sampling technology based on the JESD204B protocol, the requirement for synchronous sampling can be met in a single board card, but when the ADC sampling technology is extended to multiple board cards, a step of adjusting the clock phase is additionally required, so that the multiple board cards cannot obtain a synchronous sampling function after being powered on, and the ADC sampling technology has certain limitations.

Disclosure of Invention

The invention aims to overcome the defects of the existing synchronous sampling technology and provide a multi-board synchronous sampling device in order to solve the problem of synchronous sampling caused by the fact that an ADC chip based on a JESD204B protocol is distributed on multiple boards.

The technical scheme for realizing the purpose of the invention is as follows: a multi-board card synchronous sampling device based on a JESD204B protocol comprises N synchronous control boards and M intermediate frequency sampling boards; the synchronous control board is used for sending coherent clocks and control signals to each intermediate frequency sampling board; the hardware structure of the M intermediate frequency sampling plates is the same, the synchronous control plate is respectively connected with the M intermediate frequency sampling plates through radio frequency cables and control cables, the radio frequency cables are equal-phase radio frequency cables, so that phase synchronization of coherent clocks from the synchronous control plate to each intermediate frequency sampling plate is achieved, the control cables are equal-length cables, and control signals from the synchronous control plate to each intermediate frequency sampling plate are synchronized.

Preferably, the synchronous control board comprises 1 FPGA, x LMK04828 chips and y HMC7043 chips, the y HMC7043 chips are placed on the periphery of the LMK04828 chip, and the LMK04828 chip is designed in an equal length mode by fanning out a clock line to the HMC7043 chip, so that the clock output from the LMK04828 chip synchronously reaches the y HMC7043 chips; the FPGA completes parallel configuration of registers of an x-piece LMK04828 chip and a y-piece HMC7043 chip through an SPI (serial peripheral interface); the x LMK04828 chips and the y HMC7043 chips realize clock coherent to all intermediate frequency sampling plates; the LMK04828 chip receives an external clock, fans out 2 clocks to each HMC7043 through an internal phase-locked loop, and one clock is sent to the FPGA; after the y HMC7043 chips receive the clock from the LMK04828 chip, the fan-out M sampling clocks with the same frequency are fanned out, and each path of sampling clock is connected to any intermediate frequency sampling plate through a radio frequency cable; the FPGA receives a clock output by the LMK04828 chip, and outputs M paths of SYSREF synchronous signals with the same frequency under clock beat, each path of SYSREF synchronous signal is connected to any intermediate frequency sampling plate, and the M paths of SYSREF synchronous signals realize clock synchronization output by the LMK04828 chip on all the intermediate frequency sampling plates.

Preferably, the monolithic intermediate frequency sampling plate comprises a z-chip LMK04828 chip and an i-chip j-channel ADC chip, and is used for implementing an i x j-channel sampling function; and the M intermediate frequency sampling plates realize the sampling function of the total M i j channels.

Preferably, the i-piece ADC chip is placed on the periphery of the LMK04828 chip, the LMK04828 chip is fanned out to a clock line of the i-piece ADC chip for equal-length design, and the requirement that a clock output from the LMK04828 chip reaches the i-piece ADC chip synchronously is met. The LMK04828 chip is designed to be in a distribution function mode, a CLKin1 pin on the LMK04828 chip receives a sampling clock from a synchronous control board, and the sampling clock is fanned out to each ADC chip through a clock distribution path; a CLKin0 pin on the LMK04828 chip receives a SYSREF synchronous signal from the synchronous control board and fans out to each ADC chip; all sampling clocks and SYSREF synchronous signals meet the equal-length design of wiring on an intermediate frequency sampling plate, and the relative phase relation between the sampling clocks and the SYSREF synchronous signals in the plate is ensured; and (3) sending the sampling data of the i/j channels to an FPGA chip under the intermediate frequency sampling plate by using a JESD204B interface protocol.

Preferably, the two clocks are a device clock and a system reference clock, the device clock is used as a clock input of the HMC7043 chip, and the system reference clock is used for synchronizing a sampling clock output by the HMC7043 chip.

Preferably, the device clock and the system reference clock satisfy a wiring equal length design on the PCB.

Preferably, the SYSREF synchronization signal frequency f _SYSREF Satisfies the following conditions:

wherein f is _bitrate Represents the line rate of the high-speed transceiver, F represents the number of bytes per frame, K represents the number of frames, n is any positive integer, and is fullIn the case of sufficient signal transmission quality, the larger n is, the better.

Preferably, the M sampling clocks of the same frequency satisfy the design of equal length of wiring.

Preferably, the sampling clock and the SYSREF synchronization signal from the LMK04828 chip to the i-chip ADC chip on the intermediate frequency sampling board are designed to satisfy the equal length of wiring.

Compared with the prior art, the invention has the following advantages:

(1) The channel expansibility is high: for example, each intermediate frequency sampling board can complete sampling of 8 channels, that is, a sampling function of 14x8=112 channels is added.

(2) Synchronous automation among the board cards: and the synchronous sampling of the ADCs on all the intermediate frequency sampling plates can be automatically realized by electrifying without an additional clock phase adjustment step.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

fig. 1 is a schematic circuit diagram of an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below by taking a single (N = 1) synchronous control board and an 8 (M = 8) intermediate frequency sampling board as an example, in conjunction with the drawings of the embodiments. The synchronous control board comprises 1 (x = 1) LMK04828 chip and 2 (y = 1) HMC7043 chip, and the monolithic intermediate frequency sampling board comprises 1 (z = 1) LMK04828 chip and 2 (i = 2) 4 (j = 4) channel ADC chip. The exemplary embodiments and descriptions of the present invention are provided only for explaining the present invention and not for limiting the present invention.

The embodiment provides a multi-board card synchronous sampling device based on a JESD204B protocol, and the circuit principle is shown in fig. 1, and the device comprises 1 synchronous control board and 8 intermediate frequency sampling boards; the synchronous control board is used for sending coherent clocks and control signals to each intermediate frequency sampling board; the hardware structure of the 8 intermediate frequency sampling plates is the same, the synchronous control plate is respectively connected with the 8 intermediate frequency sampling plates through radio frequency cables and control cables, the radio frequency cables are equal-phase radio frequency cables, phase-coherent clocks from the synchronous control plate to the intermediate frequency sampling plates are in phase synchronization, the control cables are equal-length cables, and control signals from the synchronous control plate to the intermediate frequency sampling plates are synchronized.

As shown in the circuit diagram layout of the synchronous control board in FIG. 1, 1 LMK04828 chip is positioned at the left side, and 2 HMC7043 chips are positioned at the right side. The distance between the 2 HMC7043 chips and the LMK04828 chip is equal, so that the clock lines from the LMK04828 chip fan-out to the HMC7043 chip are designed in equal length. The clock output from the LMK04828 chip is synchronized to reach 2 HMC7043 chips.

In the circuit diagram layout of the intermediate frequency sampling board shown in fig. 1, the left side is an LMK04828 chip, and the right side 2 ADC chips are equidistant from the LMK04828 chip. The ADC chip on the frequency sampling plate is placed to the LMK04828 chip in equal length, so that the clock lines of the LMK04828 chip fanned out to the 2 ADC chips are designed in equal length, and the clock output from the LMK04828 chip can synchronously reach the 2 ADC chips.

The synchronous control board is the key for realizing synchronous sampling of all intermediate frequency acquisition boards. The synchronous control board comprises 1 FPGA, 1 LMK04828 chip and 2 HMC7043 chips. And the FPGA completes the parallel configuration of registers of the 1-chip LMK04828 chip and the 2-chip HMC7043 chip through the SPI interface. The 1 LMK04828 chip and the 2 HMC7043 chip implement clock coherence to all intermediate frequency sampling boards. The LMK04828 chip receives an external clock, fans out 2 clocks to each HMC7043 through an internal phase-locked loop, and one clock is sent to the FPGA. The two clocks are Device clocks (Device CLK 1-Device CLK 2) and system reference clocks (SYSREF CLK 1-SYSREF CLK 2). The device clock is used for the clock input of the HMC7043 chip, and the system reference clock is used for synchronizing the sampling clock output by the HMC7043 chip. After each HMC7043 chip receives the device clock from the LMK04828 chip, fan-out 14 sampling Clocks (CLK) of the same frequency. The sampling clock is connected to any intermediate frequency sampling plate through a radio frequency cable. The FPGA receives a clock (CLK _ FPGA) output by the LMK04828 chip, and outputs 8 SYSREF synchronous signals to the LMK04828 chip on each intermediate frequency sampling plate through a pin after frequency division processing. The SYSREF synchronization signal and the sampling clock fanned out to the intermediate frequency sampling plate by the HMC7043 chip meet the deterministic phase relationship. And the 8 paths of SYSREF synchronous signals realize clock synchronization of the output of LMK04828 chips on all intermediate frequency sampling boards.

The intermediate frequency sampling plate comprises 1 LMK04828 chip and 2 ADC chips. The LMK04828 chip is designed to assign functional modes. The CLKin1 pin on the LMK04828 chip receives the sampling clock from the synchronous control board and fans out to each ADC chip through a clock distribution path. And a CLKin0 pin on the LMK04828 chip receives a SYSREF synchronous signal from the synchronous control board and fans out to each ADC chip. All sampling clocks and SYSREF synchronous signals need to meet the equal-length design of wiring on an intermediate frequency sampling board, so that the relative phase relation between the sampling clocks and the SYSREF synchronous signals in the board is guaranteed. Each ADC chip completes signal sampling of 4 channels, and the single intermediate frequency sampling plate completes signal sampling of all 8 channels. And the sampling data of the 8 channels are sent to an FPGA chip under the intermediate frequency sampling plate by a JESD204B interface protocol.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

It should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes described in the context of a single embodiment, or with reference to a single figure, for the purpose of streamlining the disclosure and aiding in the understanding of various aspects of the invention by those skilled in the art. However, the present invention should not be construed to include features in the exemplary embodiments which are all the essential technical features of the patent claims.

It should be understood that the modules, units, components, and the like included in the device of one embodiment of the present invention may be adaptively changed to be provided in a device different from that of the embodiment. The different modules, units or components comprised by the apparatus of an embodiment may be combined into one module, unit or component or they may be divided into a plurality of sub-modules, sub-units or sub-components.

Claims (9)

1. A multi-board-card synchronous sampling device based on a JESD204B protocol is characterized by comprising N synchronous control boards and M intermediate frequency sampling boards; the synchronous control board is used for sending coherent clocks and control signals to each intermediate frequency sampling board; the hardware structure of the M intermediate frequency sampling plates is the same, the synchronous control plate is respectively connected with the M intermediate frequency sampling plates through radio frequency cables and control cables, the radio frequency cables are equal-phase radio frequency cables, phase-coherent clocks from the synchronous control plate to the intermediate frequency sampling plates are in phase synchronization, the control cables are equal-length cables, control signals from the synchronous control plate to the intermediate frequency sampling plates are synchronized, and M and N are natural numbers.

2. The JESD204B protocol-based multi-board synchronous sampling device of claim 1, wherein the synchronous control board comprises 1 FPGA, x LMK04828 chips and y HMC7043 chips, the y HMC7043 chips are placed on the periphery of the LMK04828 chips, and a clock line from the LMK04828 chip to the HMC7043 chip is designed in an equal length manner, so that the clock output from the LMK04828 chip reaches the y HMC7043 chips synchronously; the FPGA completes parallel configuration of registers of an x-piece LMK04828 chip and a y-piece HMC7043 chip through an SPI (serial peripheral interface); the x LMK04828 chips and the y HMC7043 chips realize clock coherent to all intermediate frequency sampling plates;

the LMK04828 chip receives an external clock, fans out 2 clocks to each HMC7043 through an internal phase-locked loop, and one clock is sent to the FPGA; after the y HMC7043 chips receive the clock from the LMK04828 chip, the fan-out M sampling clocks with the same frequency are fanned out, and each path of sampling clock is connected to any intermediate frequency sampling plate through a radio frequency cable; the FPGA receives a clock output by the LMK04828 chip, and outputs M paths of SYSREF synchronous signals with the same frequency under clock beat, each path of SYSREF synchronous signal is connected to any intermediate frequency sampling plate, the M paths of SYSREF synchronous signals realize clock synchronization output by the LMK04828 chip on all the intermediate frequency sampling plates, and x and y are natural numbers.

3. The device of claim 2, wherein the single intermediate frequency sampling board includes z LMK04828 chips and i ADC chips for j channels, and is configured to implement a sampling function for i x j channels; and the M intermediate frequency sampling plates realize the sampling function of total M i j channels, and z, i and j are all natural numbers.

4. The JESD204B protocol-based multi-board synchronous sampling device as claimed in claim 3, wherein the i-piece ADC chip is placed at the periphery of the LMK04828 chip, and the LMK04828 chip is fanned out to the clock lines of the i-piece ADC chip for equal-length design, so that the clock output from the LMK04828 chip reaches the i-piece ADC chip synchronously. The LMK04828 chip is designed to be in a distribution function mode, a CLKin1 pin on the LMK04828 chip receives a sampling clock from a synchronous control board, and the sampling clock is fanned out to each ADC chip through a clock distribution path; a CLKin0 pin on the LMK04828 chip receives a SYSREF synchronous signal from the synchronous control board and fans out to each ADC chip; all sampling clocks and SYSREF synchronous signals meet the equal-length design of wiring on an intermediate frequency sampling plate, and the relative phase relation between the sampling clocks and the SYSREF synchronous signals in the plate is ensured; and (3) sending the sampling data of the i/j channels to an FPGA chip under the intermediate frequency sampling plate by using a JESD204B interface protocol.

5. The device of claim 4, wherein the two clocks are a device clock and a system reference clock, the device clock is used as a clock input of the HMC7043 chip, and the system reference clock is used to synchronize the sampling clock output by the HMC7043 chip.

6. The JESD204B protocol-based multi-board synchronous sampling device as claimed in claim 4, wherein the device clock and the system reference clock satisfy the equal-length design of wiring on the PCB.

7. The JESD204B protocol-based multi-board identity module as claimed in claim 4Step sampling device, characterized in that the frequency f of the SYSREF synchronous signal _SYSREF Satisfies the following conditions:

wherein, f _bitrate The method comprises the steps of representing the line rate of a high-speed transceiver, F representing the number of bytes per frame, K representing the number of frames, and n being any positive integer, wherein the larger the n, the better the n, under the condition of meeting the signal transmission quality.

8. The JESD204B protocol-based multi-board synchronous sampling device as claimed in claim 4, wherein M sampling clocks with the same frequency satisfy the design of equal length of wiring.

9. The device according to claim 4, wherein the sampling clock and the SYSREF synchronization signal from the LMK04828 chip to the i-chip ADC chip on the intermediate frequency sampling board are designed to meet the requirement of equal length in wiring.

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