JPH07130903A - Ic package - Google Patents

Ic package

Info

Publication number
JPH07130903A
JPH07130903A JP5271091A JP27109193A JPH07130903A JP H07130903 A JPH07130903 A JP H07130903A JP 5271091 A JP5271091 A JP 5271091A JP 27109193 A JP27109193 A JP 27109193A JP H07130903 A JPH07130903 A JP H07130903A
Authority
JP
Japan
Prior art keywords
package
component mounting
wiring
cap
wiring part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5271091A
Other languages
Japanese (ja)
Other versions
JP2522185B2 (en
Inventor
Takao Ikeuchi
隆雄 池内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5271091A priority Critical patent/JP2522185B2/en
Publication of JPH07130903A publication Critical patent/JPH07130903A/en
Application granted granted Critical
Publication of JP2522185B2 publication Critical patent/JP2522185B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To obtain a higher mounting density by increasing the number of mounted components with an IC package that mounts elements including semiconductor integrated circuit. CONSTITUTION:A first component mounting part and a wiring part 3 are connected with an IC chip 1 by a bonding wire 2 and with an IC lead 4. A second wiring part 5 is connected with the IC lead 4 or with the first component mounting part and the wiring part 3, a third wiring part 6 is connected with the IC lead 4 or with the first component mounting part and the wiring part 3 through the lead 4. A fourth component mounting part and a wiring part 7 that are arranged outside an IC cap are connected with the third wiring part 6, fifth component mounting part and a wiring part 8 that are arranged inside the IC cap 9 are connected with the second wiring part 5. A wiring part is arranged on not only the outside and the inside of the IC cap but also the side of the package and the number of mounted components is increased, and a higher surface mounting density is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体集積回路に関
し、特にそのパッケージの構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to the structure of its package.

【０００２】[0002]

【従来の技術】従来の半導体集積回路を含む複数の素子
を搭載するＩＣパッケージは、図２に示す様に、部品搭
載部及び配線部３はＩＣチップ１とボンディングワイヤ
２で接続され、また、ＩＣリード４に接続される構造を
有している。部品搭載部及び配線部３には、入力または
出力の信号伝送路を終端するための終端抵抗や、電源ノ
イズを除去するためのバイパスコンデンサが搭載されて
いるため、ＩＣパッケージの外部には、前述した終端抵
抗やバイパスコンデンサ及びそれを接続するためのパタ
ーンを備える必要がなくなり、実装密度を高めることが
可能となっている。2. Description of the Related Art In a conventional IC package mounting a plurality of elements including a semiconductor integrated circuit, a component mounting portion and a wiring portion 3 are connected to an IC chip 1 and a bonding wire 2 as shown in FIG. It has a structure connected to the IC lead 4. Since the component mounting section and the wiring section 3 are equipped with a terminating resistor for terminating the input or output signal transmission path and a bypass capacitor for eliminating power source noise, the above-mentioned external parts of the IC package are It is not necessary to provide the terminating resistor, the bypass capacitor, and the pattern for connecting the terminating resistor and the bypass capacitor, and the mounting density can be increased.

【０００３】[0003]

【発明が解決しようとする課題】しかし、上述した従来
の半導体集積回路を含む複数の素子を搭載するＩＣパッ
ケージは、半導体集積回路の入出力信号数の増加や電源
供給信号数が増加すると、部品搭載部及び配線部３の面
積を広げなければならない。この結果ＩＣパッケージの
外形寸法が大きくなり、ＩＣパッケージの実装面積が増
加してしまうという欠点を有している。However, when the number of input / output signals of the semiconductor integrated circuit and the number of power supply signals increase, the IC package mounting a plurality of elements including the above-mentioned conventional semiconductor integrated circuit is a component. The area of the mounting part and the wiring part 3 must be increased. As a result, the external dimensions of the IC package increase, and the mounting area of the IC package increases.

【０００４】[0004]

【課題を解決するための手段】本発明の目的は、上述の
欠点を除去し、入力信号数等が増加しても、実装面積が
増加しないＩＣパッケージを提供することにある。本発
明のＩＣパッケージは、上記目的を達成するために、Ｉ
Ｃパッケージの側面部上に搭載し封止する構造をもつＩ
Ｃキャップの表面に部品搭載部と該部品搭載部を接続す
るための配線部を備え、ＩＣパッケージと外部を接続す
るためのＩＣリード部に接続された側面部外側に備えら
れた配線部とＩＣキャップの表面の配線部を接続してい
る。またＩＣキャップの裏面に部品搭載部と該部品搭載
部を接続するための配線部を備え、ＩＣリード部に接続
された側面部内側に備えられた配線部とＩＣキャップの
裏面の配線部を接続している。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide an IC package in which the mounting area does not increase even if the number of input signals increases. In order to achieve the above object, the IC package of the present invention has the following features.
I having a structure that is mounted on the side surface of the C package and sealed
A component mounting portion and a wiring portion for connecting the component mounting portion are provided on the surface of the C cap, and a wiring portion and an IC provided outside the side surface portion connected to the IC lead portion for connecting the IC package and the outside. The wiring part on the surface of the cap is connected. Further, a component mounting portion and a wiring portion for connecting the component mounting portion are provided on the back surface of the IC cap, and the wiring portion provided inside the side surface portion connected to the IC lead portion and the wiring portion on the back surface of the IC cap are connected. is doing.

【０００５】[0005]

【実施例】次に本発明について、図面を参照して説明す
る。The present invention will be described below with reference to the drawings.

【０００６】図１は、本発明の一実施例を示すＩＣパッ
ケージの断面図である。図において、第１の部品搭載部
及び配線部３は、ＩＣチップ１とボンディングワイヤ２
で接続され、また、ＩＣリード４に接続されている。第
２の配線部５はパッケージ側面の内側に設けられ、ＩＣ
リード４もしくは、第１の部品搭載部及び配線部３に接
続されている。第３の配線部６はパッケージ側面の外側
に設けられＩＣリード４、もしくは、ＩＣリード４を通
じて第１の部品搭載部及び配線部３に接続されている。
ＩＣキャップ９の表面には第４の部品搭載部及び配線部
７が設けられ、第３の配線部６に接続されている。一
方、ＩＣキャップ９の裏面に設けた第５の部品搭載部及
び配線部８は、第２の配線部５と接続される。FIG. 1 is a sectional view of an IC package showing an embodiment of the present invention. In the figure, the first component mounting portion and the wiring portion 3 are the IC chip 1 and the bonding wire 2
, And is also connected to the IC lead 4. The second wiring part 5 is provided inside the side surface of the package, and
It is connected to the lead 4 or the first component mounting portion and the wiring portion 3. The third wiring portion 6 is provided outside the side surface of the package, and is connected to the IC lead 4 or the first component mounting portion and the wiring portion 3 through the IC lead 4.
A fourth component mounting portion and a wiring portion 7 are provided on the surface of the IC cap 9 and are connected to the third wiring portion 6. On the other hand, the fifth component mounting portion and the wiring portion 8 provided on the back surface of the IC cap 9 are connected to the second wiring portion 5.

【０００７】この様な構造にすることにより、半導体集
積回路の入出力信号数や電源供給信号数が増加し、搭載
する部品が増加しても、ＩＣパッケージの外形寸法を大
きくすることなく、部品搭載部及び配線部の面積を増加
させることができ、実装密度を高めることが可能であ
る。With such a structure, even if the number of input / output signals and the number of power supply signals of the semiconductor integrated circuit is increased and the number of mounted components is increased, the external dimensions of the IC package are not increased, and The area of the mounting portion and the wiring portion can be increased, and the mounting density can be increased.

【０００８】[0008]

【発明の効果】以上説明した様に本発明はＩＣキャップ
の表面及び裏面に部品搭載部及び配線部を設け、ＩＣリ
ードからＩＣパッケージ側面の内側及び外側の配線部を
通じてＩＣキャップの表面及び裏面に設けた部品搭載部
及び配線部に接続したので、半導体集積回路の入出力信
号数や電源供給信号数が増加し、搭載する部品が増加し
ても、ＩＣパッケージの外形寸法を大きくすることな
く、部品搭載部及び配線部の面積を増加させることが出
来、実装密度を高めるという効果を有する。As described above, according to the present invention, the component mounting portion and the wiring portion are provided on the front surface and the back surface of the IC cap, and the front surface and the back surface of the IC cap are provided from the IC lead through the wiring portions inside and outside the side surface of the IC package. Since the number of input / output signals and the number of power supply signals of the semiconductor integrated circuit increase due to the connection to the provided component mounting portion and wiring portion, the external dimensions of the IC package do not increase even if the number of mounted components increases. It is possible to increase the area of the component mounting portion and the wiring portion, which has the effect of increasing the mounting density.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例を示す断面図。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図２】従来のＩＣパッケージの断面図。FIG. 2 is a cross-sectional view of a conventional IC package.

【符号の説明】[Explanation of symbols]

１ ＩＣチップ ２ ボンディングワイヤ ３，８，７ 部品搭載部及び配線部 ４ ＩＣリード ５，６ 配線部 ９ ＩＣキャップ 1 IC chip 2 Bonding wire 3,8,7 Component mounting part and wiring part 4 IC lead 5,6 Wiring part 9 IC cap

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 半導体集積回路を含む複数の素子を搭載
するＩＣパッケージにおいて、ＩＣパッケージの側面部
上に搭載し封止する構造をもつＩＣキャップの表面に部
品搭載部と該部品搭載部を接続するための配線部を備
え、ＩＣパッケージと外部を接続するためのＩＣリード
部に接続された前記側面部外側に備えられた配線部と前
記ＩＣキャップの表面の配線部を接続したことを特徴と
するＩＣパッケージ。1. In an IC package mounting a plurality of elements including a semiconductor integrated circuit, a component mounting portion and the component mounting portion are connected to a surface of an IC cap having a structure for mounting and sealing on a side surface of the IC package. And a wiring portion provided on the outside of the side surface portion connected to an IC lead portion for connecting the IC package to the outside, and a wiring portion on the surface of the IC cap are connected. IC package to do. 【請求項２】 前記ＩＣキャップの裏面に部品搭載部と
該部品搭載部を接続するための配線部を備え、前記ＩＣ
リード部に接続された前記側面部内側に備えられた配線
部と、前記ＩＣキャップの裏面の配線部を接続したこと
を特徴とする請求項１記載のＩＣパッケージ。2. The IC cap is provided with a component mounting portion and a wiring portion for connecting the component mounting portion on the back surface of the IC cap.
2. The IC package according to claim 1, wherein the wiring portion provided inside the side surface portion connected to the lead portion is connected to the wiring portion on the back surface of the IC cap.
JP5271091A 1993-10-29 1993-10-29 IC package Expired - Lifetime JP2522185B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5271091A JP2522185B2 (en) 1993-10-29 1993-10-29 IC package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5271091A JP2522185B2 (en) 1993-10-29 1993-10-29 IC package

Publications (2)

Publication Number Publication Date
JPH07130903A true JPH07130903A (en) 1995-05-19
JP2522185B2 JP2522185B2 (en) 1996-08-07

Family

ID=17495239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5271091A Expired - Lifetime JP2522185B2 (en) 1993-10-29 1993-10-29 IC package

Country Status (1)

Country Link
JP (1) JP2522185B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002319644A (en) * 2001-04-20 2002-10-31 Kyocera Corp Package for housing semiconductor element and semiconductor device
JP2002319645A (en) * 2001-04-20 2002-10-31 Kyocera Corp Package for housing semiconductor element and semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01251644A (en) * 1988-03-31 1989-10-06 Nec Corp Semiconductor integrated circuit device
JPH0468551A (en) * 1990-07-09 1992-03-04 Nec Corp Package for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01251644A (en) * 1988-03-31 1989-10-06 Nec Corp Semiconductor integrated circuit device
JPH0468551A (en) * 1990-07-09 1992-03-04 Nec Corp Package for semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002319644A (en) * 2001-04-20 2002-10-31 Kyocera Corp Package for housing semiconductor element and semiconductor device
JP2002319645A (en) * 2001-04-20 2002-10-31 Kyocera Corp Package for housing semiconductor element and semiconductor device

Also Published As

Publication number Publication date
JP2522185B2 (en) 1996-08-07

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Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19960402