JPH03222351A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03222351A JPH03222351A JP1612390A JP1612390A JPH03222351A JP H03222351 A JPH03222351 A JP H03222351A JP 1612390 A JP1612390 A JP 1612390A JP 1612390 A JP1612390 A JP 1612390A JP H03222351 A JPH03222351 A JP H03222351A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- line
- power supply
- semiconductor chip
- gnd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000011347 resin Substances 0.000 claims abstract description 6
- 229920005989 resin Polymers 0.000 claims abstract description 6
- 238000007789 sealing Methods 0.000 claims abstract description 5
- 239000004593 Epoxy Substances 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 4
- 230000007257 malfunction Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract 1
- 239000004642 Polyimide Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は、ガラスエポキシ等の樹脂で封止された半導
体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device sealed with a resin such as glass epoxy.
［従来の技術］
第２図は従来の半導体装置を示し、図において、（１）
は半導体チップてリードフレームのタイパノド部（２ａ
）に接続されたのち、Ａｕ線（３）等てリドフレームの
インナリード部（２ｂ）に接続される。[Prior Art] Figure 2 shows a conventional semiconductor device, in which (1)
is the tiepan node part (2a) of the semiconductor chip lead frame.
), and then connected to the inner lead part (2b) of the lid frame using an Au wire (3) or the like.
さらに、ガラスエポキシ等の封止樹脂（４）で封止され
る。（２ｃ）はリードフレームの外部リード端子部であ
る。Furthermore, it is sealed with a sealing resin (4) such as glass epoxy. (2c) is an external lead terminal portion of the lead frame.
上記の構成になる半導体装置は、リードフレムの外部リ
ード端子（２ｃ）を通して外部から入力信号、電源、Ｇ
ＮＤ電位が半導体チップ（１）に供給され、逆に半導体
チ／ブ（１）から外部リード端子（２ｃ）を通して出力
信号が外部へ出力されて動作する。The semiconductor device with the above configuration receives input signals from the outside through the external lead terminal (2c) of the lead frame, and receives power and G.
An ND potential is supplied to the semiconductor chip (1), and conversely, an output signal is output from the semiconductor chip (1) to the outside through the external lead terminal (2c) to operate.
［発明が解決しようとする課題］
従来の半導体装置は、そのパッケージ構造が以上のよう
に、信号ライン、ＧＮＤライン、電源ラインにつながる
リードが同一の形状、材質で形成され、特にＧＮＤライ
ン、電源ラインにつながるリードのインダクタンスを低
くする方策がなされていなかったので、出力信号変化に
よる出力電流の変化が生じた際、ＧＮＤ、ｍ源の電位が
上記インダクタンスに比例して変化し、ノイズが発生し
て次段の電子部品を誤動作させるという問題点があった
。[Problems to be Solved by the Invention] As described above, the package structure of the conventional semiconductor device is such that the leads connected to the signal line, GND line, and power supply line are formed of the same shape and material. No measures had been taken to lower the inductance of the leads connected to the line, so when the output current changed due to a change in the output signal, the potential of the GND and m sources changed in proportion to the above inductance, causing noise. There was a problem in that the electronic components in the next stage would malfunction.
この発明は上記のような問題点を解消するためになされ
たもので、ＧＮＤライン、電源ラインにつながるリード
のインダクタンスを低減することができる半導体装置を
得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device that can reduce the inductance of leads connected to a GND line and a power supply line.
［課題を解決するための手段］
この発明に係る半導体装置は、信号ライン、ＧＮＤライ
ン、電源ラインがそれぞれ個別の層で形成され、このう
ちＧＮＤライン、電源ラインは十分大きな面積が確保さ
れ、かつ、半導体チップおよびリードフレームと接続す
るための端子を有しているポリイミド等の配線基板を介
して、半導体チップとリードフレームを接続したもので
ある。[Means for Solving the Problems] In the semiconductor device according to the present invention, the signal line, the GND line, and the power supply line are each formed in separate layers, and among these, the GND line and the power supply line have a sufficiently large area, and , a semiconductor chip and a lead frame are connected via a wiring board made of polyimide or the like and having terminals for connection to the semiconductor chip and lead frame.
［作 用］
この発明においては、ＧＮＤライン、電源ラインに十分
大きな面積が確保されているので、それぞれのインダク
タンスの値が小さくなり、出力信号変化による出力電流
の変化が生じた際にもＧＮＤ。[Function] In this invention, since a sufficiently large area is secured for the GND line and the power supply line, the inductance value of each becomes small, and even when the output current changes due to a change in the output signal, the GND line and the power supply line are connected.
電源の電位の変動を抑えることができる。Fluctuations in the power supply potential can be suppressed.
［実施例］
第１図はこの発明の一実施例を示し、図において、符号
（１）、 （２ｂ）、 （２ｃ）、 （３）、 （４）
は第２図と同一ないし相当部分を示す。（１０）はポリ
イミド等で形成された配線基板である。この配線基板（
１ｏ）は１層目に信号ライン（６）が、２層目にＧＮＤ
ライン（７）が、３層目に電源ライン（８）が形成され
た多層構造になっており、ＧＮＤライン、電源ラインは
十分大きな面積が確保されている。また、１層目には半
導体チップ（１）と接続するための端子（５ａ）および
リードフレームのインナーリード部（２ｂ）と接続する
ための端子（５ｂ）があり、信号ライン（６）からは直
接、ＧＮＤライン（７）、電源ライン（８）からはスル
ーホール（９）を介して接続されている。[Embodiment] FIG. 1 shows an embodiment of the present invention, and in the figure, symbols (1), (2b), (2c), (3), (4)
indicates the same or equivalent portion as in FIG. 2. (10) is a wiring board made of polyimide or the like. This wiring board (
1o) has the signal line (6) on the first layer and the GND on the second layer.
The line (7) has a multilayer structure in which the power line (8) is formed in the third layer, and a sufficiently large area is secured for the GND line and the power line. The first layer also has terminals (5a) for connecting to the semiconductor chip (1) and terminals (5b) for connecting to the inner lead part (2b) of the lead frame, and there are terminals (5b) for connecting to the semiconductor chip (1) and the inner lead part (2b) of the lead frame. It is directly connected to the GND line (7) and power supply line (8) via a through hole (9).
まず、半導体チップ（１）を配線基板（ｌＯ）に形成さ
れたタイバット部（１１）に接続し、次にＡｕ線（３）
で半導体チップ０）の端子と配線基板（１０）の端子（
５ａ）を接続する。さらに配線基板（１０）の端子（５
ｂ）とリードフレームのインナーリード部（２ｂ）を接
続し、最後にガラスエポキシ等の封止樹脂（４）により
封止する。外観では、従来のパッケージと同一のものと
なる。First, the semiconductor chip (1) is connected to the tie butt part (11) formed on the wiring board (lO), and then the Au wire (3)
The terminals of the semiconductor chip 0) and the terminals of the wiring board (10)
Connect 5a). Furthermore, the terminal (5) of the wiring board (10)
b) is connected to the inner lead portion (2b) of the lead frame, and finally sealed with a sealing resin (4) such as glass epoxy. In appearance, it will be the same as the conventional package.
以上の構成により、配線基板（１０）はＧＮＤライン（
７）、電源ライン（８）の面積を十分大きく確保してい
るので、インダクタンスが従来のバッケジと比較して十
分低減されている。このため、出力信号の変化による出
力電流変化によって生じるＧＮＤ、電源の変動を抑える
ことができる。With the above configuration, the wiring board (10) connects to the GND line (
7) Since the area of the power supply line (8) is sufficiently large, the inductance is sufficiently reduced compared to the conventional bag. Therefore, fluctuations in GND and power supply caused by changes in output current due to changes in output signals can be suppressed.
［発明の効果］
以上のように、この発明によれば、ＧＮＤ、’１源のリ
ードインダクタンスを低減したので、ノイズによる次段
の電子部品の誤動作を防止することができる。[Effects of the Invention] As described above, according to the present invention, since the lead inductance of the GND source is reduced, it is possible to prevent malfunctions of electronic components in the next stage due to noise.
第１図はこの発明の一実施例の断面図、第２図は従来の
半導体装置の一部切欠き斜視図である。
（１） ・・半導体チップ、（２ａ）・・リードフレ
ムのダイパッド部、（２ｂ）・・リードフレームのイン
ナリード部、（２ｃ）・・リードフレームの外部リド端
子、（４）・・封止樹脂、（５ａ）・・半導体チップと
接続するための端子、（５ｂ）・・リードフレームのイ
ンナーリード部と接続するための端子、（６）・・信号
ライン、り７）・・ＧＮＤヲィン、（８） ・・電源
ライン、（９） ・・スルーホール、（１０）・・配
線基板。
なお、各図中、同一符号は同−又は相当部分を示す。FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a partially cutaway perspective view of a conventional semiconductor device. (1) Semiconductor chip, (2a) Die pad part of lead frame, (2b) Inner lead part of lead frame, (2c) External lead terminal of lead frame, (4) Sealing resin , (5a)...Terminal for connecting to the semiconductor chip, (5b)...Terminal for connecting to the inner lead part of the lead frame, (6)...Signal line, ri7)...GND win, ( 8) ...Power line, (9) ...Through hole, (10) ...Wiring board. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
ンがそれぞれ個別の層で形成された多層構造になってい
る配線基板と、この配線基板を介して前記半導体チップ
に接続されたリードフレムと、前記半導体チップと前記
配線基板および前記リードフレームのインナリード部と
を封止した封止樹脂とを備えてなる半導体装置。A semiconductor chip, a wiring board having a multilayer structure in which signal lines, GND lines, and power lines are each formed of separate layers, a lead frame connected to the semiconductor chip via the wiring board, and the semiconductor chip. and a sealing resin that seals the wiring board and the inner lead portion of the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1612390A JPH03222351A (en) | 1990-01-29 | 1990-01-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1612390A JPH03222351A (en) | 1990-01-29 | 1990-01-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03222351A true JPH03222351A (en) | 1991-10-01 |
Family
ID=11907734
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1612390A Pending JPH03222351A (en) | 1990-01-29 | 1990-01-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03222351A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04286148A (en) * | 1991-03-14 | 1992-10-12 | Hitachi Cable Ltd | Multi-pin multilayer interconnection lead frame |
-
1990
- 1990-01-29 JP JP1612390A patent/JPH03222351A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04286148A (en) * | 1991-03-14 | 1992-10-12 | Hitachi Cable Ltd | Multi-pin multilayer interconnection lead frame |
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