JP2513145B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JP2513145B2 JP2513145B2 JP5231967A JP23196793A JP2513145B2 JP 2513145 B2 JP2513145 B2 JP 2513145B2 JP 5231967 A JP5231967 A JP 5231967A JP 23196793 A JP23196793 A JP 23196793A JP 2513145 B2 JP2513145 B2 JP 2513145B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- power supply
- circuit device
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路装置に
関し、特に、半導体集積回路チップをパッケ−ジに収容
した構造の半導体集積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a structure in which a semiconductor integrated circuit chip is housed in a package.
【０００２】[0002]
【従来の技術】この種の半導体集積回路装置では、電源
電極及びグラウンド電極間に電源ノイズバイパス用のコ
ンデンサを接続し、スイッチング時における電源からの
過渡電流を吸収するようにしている。2. Description of the Related Art In a semiconductor integrated circuit device of this type, a capacitor for power supply noise bypass is connected between a power supply electrode and a ground electrode so as to absorb a transient current from the power supply during switching.
【０００３】従来より、かかる半導体集積回路装置にお
いては、図３に示すように、電源ノイズバイパス用のコ
ンデンサ３０は、半導体集積回路チップ３２を収容する
パッケ−ジ３４には収容されておらず、パッケ−ジ３４
に外付けして使用されている。Conventionally, in such a semiconductor integrated circuit device, as shown in FIG. 3, the power source noise bypass capacitor 30 is not housed in the package 34 housing the semiconductor integrated circuit chip 32. Package 34
It is used externally to.
【０００４】[0004]
【発明が解決しようとする課題】しかし、この従来の半
導体集積回路装置では、電源ノイズバイパス用のコンデ
ンサ３０が外付けして使用されているので、半導体集積
回路装置３６内部のボンディングワイヤ−３８や外部リ
−ド端子４０のインピ−ダンス等の影響により、半導体
集積回路装置３６のスイッチング時に生じる電源からの
過渡電流を十分に吸収することができなかった。即ち、
上述した電源からの過渡電流は、電源ノイズバイパス用
のコンデンサ３０によって吸収されることなく、そのま
まボンディングワイヤ−３８や外部リ−ド端子４０に流
れ込んでしまう。However, in this conventional semiconductor integrated circuit device, since the capacitor 30 for power supply noise bypass is externally used, the bonding wire 38 inside the semiconductor integrated circuit device 36 and Due to the influence of the impedance of the external lead terminal 40 and the like, the transient current from the power supply generated when the semiconductor integrated circuit device 36 is switched cannot be sufficiently absorbed. That is,
The transient current from the power supply described above flows into the bonding wire 38 and the external lead terminal 40 as it is without being absorbed by the capacitor 30 for bypassing the power supply noise.
【０００５】従って、この過渡電流がボンディングワイ
ヤ−３８や外部リ−ド端子４０を流れる時に、これらの
インピ−ダンス等の影響で電源ノイズが発生し、半導体
集積回路装置３６のグラウンドレベルが不安定になった
り、半導体集積回路装置３６からノイズを放射してしま
うという問題点があった。Therefore, when this transient current flows through the bonding wire 38 and the external lead terminal 40, power supply noise is generated due to the influence of these impedances and the like, and the ground level of the semiconductor integrated circuit device 36 becomes unstable. And the semiconductor integrated circuit device 36 emits noise.
【０００６】このような問題点を解決すべく、例えば、
特開平４−７９２６４号に示されるように、電源ノイズ
バイパス用のコンデンサを半導体集積回路チップを収容
したパッケ−ジに内臓する構造の半導体集積回路装置も
提案されている。この半導体集積回路装置によれば、半
導体集積回路チップに極めて近い位置でノイズを吸収で
きるので、ノイズの放射や誤動作の原因は除去される。In order to solve such a problem, for example,
As disclosed in Japanese Patent Laid-Open No. 4-79264, there is also proposed a semiconductor integrated circuit device having a structure in which a power source noise bypass capacitor is built in a package accommodating a semiconductor integrated circuit chip. According to this semiconductor integrated circuit device, since noise can be absorbed at a position extremely close to the semiconductor integrated circuit chip, the cause of noise emission and malfunction can be eliminated.
【０００７】しかしながら、この特開平４−７９２６４
号に記載された半導体集積回路装置では、第一及び第二
の電極とこれら第一及び第二の電極間に挟まれた誘電体
とから構成した電源ノイズバイパス用のコンデンサが、
第一の電極を電源線と接続し第二の電極を接地線と接続
するようにして、半導体集積回路チップの下面側に設け
られている。従って、半導体集積回路チップをパッケ−
ジに封入して半導体集積回路装置を組み立てる一連の工
程において、上記の電源ノイズバイパス用のコンデンサ
を製作して半導体集積回路チップの下面側に設置する工
程が別途必要となり、半導体集積回路装置製造のための
コストの増加や工程の複雑化を避けられなかった。However, this Japanese Patent Laid-Open No. 4-79264
In the semiconductor integrated circuit device described in No. 1, a capacitor for power supply noise bypass composed of first and second electrodes and a dielectric material sandwiched between the first and second electrodes,
The first electrode is connected to the power supply line and the second electrode is connected to the ground line, and is provided on the lower surface side of the semiconductor integrated circuit chip. Therefore, the semiconductor integrated circuit chip is packaged.
In a series of steps of assembling the semiconductor integrated circuit device by enclosing it in a package, it is necessary to separately manufacture the above-mentioned capacitor for power supply noise bypass and install it on the lower surface side of the semiconductor integrated circuit device. Therefore, increase in cost and complication of the process cannot be avoided.
【０００８】本発明の目的は、スイッチング時における
グラウンドレベルの変動やノイズの放射を有効に防止す
ることができる上に製造が容易な半導体集積回路装置を
提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device which can effectively prevent fluctuations in the ground level and radiation of noise during switching and is easy to manufacture.
【０００９】[0009]
【課題を解決するための手段】本発明によれば、半導体
集積回路チップと、該半導体集積回路チップの周辺部に
それぞれ設けられた電源電極及びグラウンド電極と、該
電源電極及びグラウンド電極間に接続された電源ノイズ
バイパス用のコンデンサとを有する半導体集積回路装置
において、前記半導体集積回路チップの上面に絶縁膜を
形成し、該絶縁膜上に前記電源電極に接続された電源領
域と前記グラウンド電極に接続されたグラウンド領域と
をそれぞれ形成し、前記電源領域と前記グラウンド領域
の間に前記電源ノイズバイパス用のコンデンサを具備す
ることを特徴とする半導体集積回路装置が得られる。According to the present invention, a semiconductor integrated circuit chip, a power supply electrode and a ground electrode respectively provided on the periphery of the semiconductor integrated circuit chip, and a connection between the power supply electrode and the ground electrode. In a semiconductor integrated circuit device having a capacitor for bypassing power supply noise, an insulating film is formed on the upper surface of the semiconductor integrated circuit chip, and a power supply region connected to the power supply electrode and the ground electrode are formed on the insulating film. A semiconductor integrated circuit device is obtained which is characterized in that it forms a connected ground region and that the power source noise bypass capacitor is provided between the power source region and the ground region.
【００１０】また、本発明によれば、前記電源領域と前
記グラウンド領域とは前記電源電極及び前記グラウンド
電極から前記半導体集積回路チップ及び前記絶縁膜の上
面を略二分して覆っていることを特徴とする半導体集積
回路装置が得られる。Further, according to the present invention, the power supply region and the ground region cover the upper surface of the semiconductor integrated circuit chip and the insulating film from the power supply electrode and the ground electrode by substantially dividing them into two parts. A semiconductor integrated circuit device is obtained.
【００１１】[0011]
【実施例】以下、本発明の一実施例に係る半導体集積回
路装置について図面を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device according to an embodiment of the present invention will be described below with reference to the drawings.
【００１２】本実施例の半導体集積回路装置１０は、図
１及び図２に示すように、半導体集積回路チップ１２
と、半導体集積回路チップ１２の周辺部にそれぞれ設け
られた電源電極１４及びグラウンド電極１６を有してい
る。半導体集積回路チップ１２の上面には、絶縁膜１８
が形成され、絶縁膜１８上には電源電極１４に接続され
た電源領域２０とグラウンド電極１６に接続されたグラ
ウンド領域２２とがそれぞれ形成されている。電源領域
２０とグラウンド領域２２の間には、電源ノイズバイパ
ス用のコンデンサとして積層セラミックチップコンデン
サ２４、２４が具備されている。また、電源領域２０と
グラウンド領域２２とは電源電極１４及びグラウンド電
極１６から半導体集積回路チップ１２及び絶縁膜１８の
上面を略二分して覆っている。As shown in FIGS. 1 and 2, the semiconductor integrated circuit device 10 of this embodiment has a semiconductor integrated circuit chip 12 as shown in FIG.
And a power electrode 14 and a ground electrode 16 respectively provided on the periphery of the semiconductor integrated circuit chip 12. An insulating film 18 is formed on the upper surface of the semiconductor integrated circuit chip 12.
Is formed, and a power source region 20 connected to the power source electrode 14 and a ground region 22 connected to the ground electrode 16 are formed on the insulating film 18. Between the power supply area 20 and the ground area 22, multilayer ceramic chip capacitors 24, 24 are provided as capacitors for bypassing the power supply noise. In addition, the power supply region 20 and the ground region 22 cover the upper surface of the semiconductor integrated circuit chip 12 and the insulating film 18 from the power supply electrode 14 and the ground electrode 16 in a substantially bisected manner.
【００１３】この半導体集積回路装置１０を製造するに
は、半導体集積回路チップ１２の上面に絶縁膜１８を形
成し、この絶縁膜１８上に電源電極１４から半導体集積
回路チップ１２の上面の略半分を覆う幅広の電源領域２
０と、グラウンド電極１６から半導体集積回路チップ１
２の上面の他の略半分を覆う幅広のグラウンド領域２２
とを形成し、各積層セラミックチップコンデンサ２４の
両電極２４ａ及び２４ｂと電源領域２０及びグラウンド
領域２２とをそれぞれ導電性ペ−スト２６、２６によっ
て接着すればよい。従って、半導体集積回路チップ１２
の製造工程の中で、そのためのマスクを使用して電源領
域２０及びグラウンド領域２２を形成すれば足りるの
で、上述した特開平４−７９２６４号に記載された半導
体集積回路装置に比べ、その製造が極めて容易である。In order to manufacture this semiconductor integrated circuit device 10, an insulating film 18 is formed on the upper surface of the semiconductor integrated circuit chip 12, and from this power supply electrode 14 to approximately half the upper surface of the semiconductor integrated circuit chip 12 is formed on this insulating film 18. Wide power supply area 2
0 and the ground electrode 16 to the semiconductor integrated circuit chip 1
Wide ground region 22 covering the other half of the upper surface of 2
Then, both electrodes 24a and 24b of each monolithic ceramic chip capacitor 24 and the power source region 20 and the ground region 22 may be bonded by conductive pastes 26 and 26, respectively. Therefore, the semiconductor integrated circuit chip 12
Since it suffices to form the power supply region 20 and the ground region 22 by using a mask therefor in the manufacturing process of 1. It's extremely easy.
【００１４】さて、本実施例の半導体集積回路装置１０
においては、電源ノイズバイパス用の積層セラミックチ
ップコンデンサ２４、２４が、パッケ−ジ３４に収容さ
れ、しかも半導体集積回路チップ１２の上面に絶縁膜１
８を介して半導体集積回路チップ１２の上面を略二分し
て覆うように形成された幅広の電源領域２０及びグラウ
ンド領域２２間に具備されている。従って、電源からの
過渡電流は、そのままボンディングワイヤ−３８や外部
リ−ド端子４０に流れ込むことなく、電源ノイズバイパ
ス用の各積層セラミックチップコンデンサ２４により吸
収される。よって、ボンディングワイヤ−３８や外部リ
−ド端子４０に流れる電源からの過渡電流が減少するの
で、ボンディングワイヤ−３８や外部リ−ド端子４０を
介して生じるグラウンドレベルの変動や半導体集積回路
装置１０から放射されるノイズを十分に抑制することが
可能である。Now, the semiconductor integrated circuit device 10 of the present embodiment.
, The multilayer ceramic chip capacitors 24, 24 for bypassing the power supply noise are housed in the package 34, and the insulating film 1 is formed on the upper surface of the semiconductor integrated circuit chip 12.
It is provided between a wide power source region 20 and a ground region 22 formed so as to cover the upper surface of the semiconductor integrated circuit chip 12 in approximately two portions with the intermediate portion 8 interposed therebetween. Therefore, the transient current from the power supply is absorbed by the multilayer ceramic chip capacitors 24 for power supply noise bypass without flowing into the bonding wire 38 or the external lead terminal 40 as it is. Therefore, the transient current from the power supply flowing through the bonding wire-38 and the external lead terminal 40 is reduced, so that the fluctuation of the ground level generated through the bonding wire-38 and the external lead terminal 40 and the semiconductor integrated circuit device 10 are caused. It is possible to sufficiently suppress the noise radiated from the.
【００１５】尚、電源領域２０とグラウンド領域２２と
は、それぞれ電源電極１４及びグラウンド電極１６から
半導体集積回路チップ１２の上面の略半分を覆うように
幅広に形成されている。従って、その分インピ−ダンス
が小さくなるので、上述した過渡電流がこれら電源領域
２０及びグラウンド領域２２を流れる時にノイズが発生
するのも防止される。The power supply region 20 and the ground region 22 are formed wide so as to cover the power supply electrode 14 and the ground electrode 16 and substantially half of the upper surface of the semiconductor integrated circuit chip 12, respectively. Therefore, since the impedance is reduced accordingly, noise is also prevented from occurring when the above-described transient current flows through the power supply region 20 and the ground region 22.
【００１６】上記実施例では、電源ノイズバイパス用の
各積層セラミックチップコンデンサ２４の両電極２４ａ
及び２４ｂと電源領域２０及びグラウンド領域２２とを
それぞれ導電性ペ−スト２６、２６によって接着した
が、導電性ペ−ストによらず、半田付けによってもよ
い。In the above embodiment, both electrodes 24a of each multilayer ceramic chip capacitor 24 for power supply noise bypass are used.
, 24b and the power source region 20 and the ground region 22 are adhered by the conductive pastes 26, 26, respectively, but may be soldered instead of the conductive paste.
【００１７】[0017]
【発明の効果】以上説明したように、本発明によれば、
半導体集積回路チップと、この半導体集積回路チップの
周辺部にそれぞれ設けられた電源電極及びグラウンド電
極とを有する半導体集積回路装置において、半導体集積
回路チップの上面に絶縁膜を形成し、この絶縁膜上に電
源電極に接続された電源領域とグラウンド電極に接続さ
れたグラウンド領域とをそれぞれ形成し、これら電源領
域とグラウンド領域の間に電源ノイズバイパス用のコン
デンサを具備しているので、半導体集積回路装置のスイ
ッチング時に生じる電源からの過渡電流を半導体集積回
路チップ上に設けた電源ノイズバイパス用のコンデンサ
により吸収することができる。As described above, according to the present invention,
In a semiconductor integrated circuit device having a semiconductor integrated circuit chip and a power electrode and a ground electrode respectively provided in the peripheral portion of the semiconductor integrated circuit chip, an insulating film is formed on the upper surface of the semiconductor integrated circuit chip, and the insulating film is formed on the insulating film. Since a power supply region connected to the power supply electrode and a ground region connected to the ground electrode are formed in each of them, and a capacitor for power supply noise bypass is provided between the power supply region and the ground region, the semiconductor integrated circuit device It is possible to absorb the transient current from the power supply generated at the time of switching by the power supply noise bypass capacitor provided on the semiconductor integrated circuit chip.
【００１８】従って、ボンディングワイヤ−や外部リ−
ド端子に流れる電源からの過渡電流を減少させるので、
ボンディングワイヤ−や外部リ−ド端子を介して生じる
グラウンドレベルの変動や半導体集積回路装置から放射
されるノイズを抑制することが可能である。Therefore, the bonding wire and the external lead
Since the transient current from the power supply flowing to the terminal is reduced,
It is possible to suppress the fluctuation of the ground level generated through the bonding wire or the external lead terminal and the noise radiated from the semiconductor integrated circuit device.
【００１９】よって、スイッチング時におけるグラウン
ドレベルの変動やノイズの放射を有効に防止することが
できる半導体集積回路装置を提供し得る。Therefore, it is possible to provide a semiconductor integrated circuit device which can effectively prevent fluctuations in the ground level and noise emission during switching.
【００２０】また、従来の電源ノイズバイパス用のコン
デンサをパッケ−ジに外付けして使用するものと異な
り、半導体集積回路装置単体でＥＭＣ対策が可能とな
る。Further, unlike the conventional one in which a capacitor for power supply noise bypass is externally attached to the package and used, the semiconductor integrated circuit device alone can take EMC countermeasures.
【図１】本発明の一実施例に係る半導体集積回路装置の
断面図である。FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention.
【図２】図１に示した半導体集積回路装置の半導体集積
回路チップの平面図である。FIG. 2 is a plan view of a semiconductor integrated circuit chip of the semiconductor integrated circuit device shown in FIG.
【図３】従来の半導体集積回路装置の構成を示す図であ
る。FIG. 3 is a diagram showing a configuration of a conventional semiconductor integrated circuit device.
１０ 半導体集積回路装置 １２ 半導体集積回路チップ １４ 電源電極 １６ グラウンド電極 １８ 絶縁膜 ２０ 電源領域 ２２ グラウンド領域 ２４ 電源ノイズバイパス用のコンデンサ 10 semiconductor integrated circuit device 12 semiconductor integrated circuit chip 14 power supply electrode 16 ground electrode 18 insulating film 20 power supply region 22 ground region 24 power supply noise bypass capacitor
Claims (2)
回路チップの周辺部にそれぞれ設けられた電源電極及び
グラウンド電極と、該電源電極及びグラウンド電極間に
接続された電源ノイズバイパス用のコンデンサとを有す
る半導体集積回路装置において、前記半導体集積回路チ
ップの上面に絶縁膜を形成し、該絶縁膜上に前記電源電
極に接続された電源領域と前記グラウンド電極に接続さ
れたグラウンド領域とをそれぞれ形成し、前記電源領域
と前記グラウンド領域の間に前記電源ノイズバイパス用
のコンデンサを具備することを特徴とする半導体集積回
路装置。1. A semiconductor integrated circuit chip, a power supply electrode and a ground electrode respectively provided in the peripheral portion of the semiconductor integrated circuit chip, and a power supply noise bypass capacitor connected between the power supply electrode and the ground electrode. In a semiconductor integrated circuit device having, an insulating film is formed on an upper surface of the semiconductor integrated circuit chip, and a power source region connected to the power electrode and a ground region connected to the ground electrode are respectively formed on the insulating film. A semiconductor integrated circuit device comprising the capacitor for bypassing the power supply noise between the power supply region and the ground region.
いて、前記電源領域と前記グラウンド領域とは前記電源
電極及び前記グラウンド電極から前記半導体集積回路チ
ップ及び前記絶縁膜の上面を略二分して覆っていること
を特徴とする半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein the power supply region and the ground region cover the power supply electrode and the ground electrode by dividing the upper surface of the semiconductor integrated circuit chip and the upper surface of the insulating film into approximately two parts. And a semiconductor integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5231967A JP2513145B2 (en) | 1993-09-17 | 1993-09-17 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5231967A JP2513145B2 (en) | 1993-09-17 | 1993-09-17 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0786491A JPH0786491A (en) | 1995-03-31 |
| JP2513145B2 true JP2513145B2 (en) | 1996-07-03 |
Family
ID=16931862
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5231967A Expired - Lifetime JP2513145B2 (en) | 1993-09-17 | 1993-09-17 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2513145B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4811437B2 (en) * | 2008-08-11 | 2011-11-09 | 日本テキサス・インスツルメンツ株式会社 | Mounting electronic components on IC chips |
-
1993
- 1993-09-17 JP JP5231967A patent/JP2513145B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0786491A (en) | 1995-03-31 |
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| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19960305 |