JPH07130794A - Manufacture of semiconductor - Google Patents
Manufacture of semiconductorInfo
- Publication number
- JPH07130794A JPH07130794A JP5274480A JP27448093A JPH07130794A JP H07130794 A JPH07130794 A JP H07130794A JP 5274480 A JP5274480 A JP 5274480A JP 27448093 A JP27448093 A JP 27448093A JP H07130794 A JPH07130794 A JP H07130794A
- Authority
- JP
- Japan
- Prior art keywords
- gap
- resin
- sealing resin
- substrate
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体の製造方法に関す
る。FIELD OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor.
【０００２】[0002]
【従来技術とその問題点】半導体の製造に際し、フリッ
プチップの実装は、フリップチップ素子の電極と、基板
の電極とをバンプを介して接続固定することにより行な
われ、基板と、該基板上に搭載された素子との間には、
バンプにもとづく隙間が生ずる。この隙間内には、熱サ
イクル寿命の向上を目的として、封止樹脂が充填され
る。2. Description of the Related Art In manufacturing a semiconductor, flip chip mounting is performed by connecting and fixing electrodes of a flip chip element and electrodes of a substrate through bumps. Between the mounted element,
A gap is created based on the bump. A sealing resin is filled in the gap for the purpose of improving the thermal cycle life.
【０００３】従来、このような樹脂封止方法として、図
３に概略的に示すように、基板１上に搭載されたフリッ
プチップ素子２の側部にディスペンサよりの吐出で所定
量の液状封止樹脂３を供給した後、該樹脂３を、基板１
と素子２との間に生ずるバンプ４にもとづく隙間５内に
毛細管現象を利用してしみ込ませ充填しているが、これ
は次の通りの問題点があった。Conventionally, as such a resin sealing method, as shown schematically in FIG. 3, a predetermined amount of liquid sealing is performed by discharging from a dispenser on the side of a flip chip element 2 mounted on a substrate 1. After supplying the resin 3, the resin 3 is applied to the substrate 1
The gap 5 based on the bump 4 generated between the element 2 and the element 2 is soaked and filled by using the capillary phenomenon, but this has the following problems.
【０００４】イ） 隙間５内に封止樹脂３がしみ込んで
完全に充填されるまでにかなりの放置時間を必要とし、
実装工程中、最も時間のかかる工程となっており、生産
効率の低下を招いている。B) It takes a considerable time for the sealing resin 3 to soak into the gap 5 and be completely filled.
This is the most time-consuming step in the mounting process, which causes a reduction in production efficiency.
【０００５】ロ） 隙間５内に充填された封止樹脂３中
に気泡が含まれ易く信頼性に問題がある。(B) Bubbles are likely to be contained in the sealing resin 3 filled in the gap 5 and there is a problem in reliability.
【０００６】ハ） 封止樹脂３の粘度が高いと隙間５内
に入りにくいので、おのずと樹脂に配合されるフイラー
量も制限され、信頼性の高い樹脂配合がむずかしい。C) If the viscosity of the sealing resin 3 is high, it is difficult for the resin to enter the gap 5. Therefore, the amount of filler to be naturally mixed with the resin is also limited, and it is difficult to mix the resin with high reliability.
【０００７】ニ） 封止樹脂の粘度を下げないとしみ込
みにくいので基板を予熱する必要があり、面倒である。D) Since it is difficult for the sealing resin to penetrate unless the viscosity of the sealing resin is reduced, it is necessary to preheat the substrate, which is troublesome.
【０００８】ホ） ０．０５ｍｍ以下の隙間に対して
は、封止樹脂がしみ込んで行かない。E) The sealing resin does not soak into the gap of 0.05 mm or less.
【０００９】本発明は、このような従来の問題点を一層
することを目的としてなされたものである。The present invention has been made for the purpose of further solving the above conventional problems.
【００１０】[0010]
【問題点を解決するための手段】本発明は、基板上にフ
リップチップ素子をバンプを介し搭載した後に、上記基
板と素子との間に生ずるバンプにもとづく隙間内に液状
封止樹脂を充填する半導体の製造方法において、上記基
板の上記素子が搭載される位置の略々中央部に予め貫通
孔を形成しておき、該貫通孔を通じて上記隙間内を減圧
状態に保持することにより、液状封止樹脂を上記隙間内
に強制的に吸引充填することを特徴とする半導体の製造
方法に係る。According to the present invention, a flip-chip element is mounted on a substrate via bumps, and then a liquid sealing resin is filled in a gap formed by the bumps between the substrate and the element. In the method for manufacturing a semiconductor, a through hole is formed in advance in a substantially central portion of the substrate where the element is mounted, and the inside of the gap is maintained in a reduced pressure state through the through hole, so that liquid sealing is performed. The present invention relates to a semiconductor manufacturing method, which comprises forcibly suction-filling a resin into the gap.
【００１１】[0011]
【実施例】以下に本発明製造方法を添附図面にもとづき
説明すると、次の通りである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The manufacturing method of the present invention will be described below with reference to the accompanying drawings.
【００１２】図１は本発明製造方法の１実施状況を概略
的に示す模式図であり、樹脂封止に供される半導体装置
Ａは、基板１と、該基板１上にバンプ４を介し搭載され
たフリップチップ素子２とから構成され、基板１と素子
２との間には、バンプ４にもとづく隙間５が生じてい
る。このような半導体装置Ａは常法に従い製造される。FIG. 1 is a schematic view schematically showing one embodiment of the manufacturing method of the present invention. A semiconductor device A used for resin sealing is mounted on a substrate 1 and bumps 4 on the substrate 1. The flip chip element 2 is formed with a gap between the substrate 1 and the element 2 based on the bump 4. Such a semiconductor device A is manufactured according to a conventional method.
【００１３】本発明製造方法によれば、上記基板１の素
子２が搭載される位置の中央部に、配線に支障を来さな
いように予め貫通孔６が形成されている。貫通孔６とし
ては、基板１に表裏の配線を接続するスルーホールが形
成されている場合は、該スルーホールを貫通孔６として
利用してもよい。According to the manufacturing method of the present invention, the through hole 6 is previously formed in the central portion of the substrate 1 where the element 2 is mounted so as not to hinder the wiring. As the through hole 6, when a through hole for connecting front and back wirings is formed in the substrate 1, the through hole may be used as the through hole 6.
【００１４】貫通孔６の直径としては、これがあまり小
さいと吸引減圧の効果が不充分となり、またあまり大き
いと配線の面で支障を招く虞れがあるので、０．０２〜
３．０ｍｍ程度の範囲内から適宜選択決定される。If the diameter of the through hole 6 is too small, the effect of suction and decompression will be insufficient, and if it is too large, the wiring surface may be hindered.
It is appropriately selected and determined within the range of about 3.0 mm.
【００１５】尚バンプ４としては、ハンダ、金などの金
属バンプ、電導性樹脂バンプなどを例示できるが、その
他導電性接着剤、異方性導電膜などを構成要素として含
むようなバンプであってもよい。The bumps 4 may be, for example, solder, metal bumps of gold or the like, conductive resin bumps, or the like, but may be conductive bumps, anisotropic conductive films or the like as constituent elements. Good.
【００１６】ベース基板としては、特に限定されず公知
のものがいずれも使用できる。例えばアルミナセラミッ
ク基板、ガラスセラミック基板などの無機質基板、ガラ
ス−エポキシ基板、アラミド−エポキシ基板、紙−フェ
ノール基板などの有機質基板、アルミ基板、鉄基板など
の金属基板である。The base substrate is not particularly limited, and any known substrate can be used. Examples thereof include inorganic substrates such as alumina ceramic substrates and glass ceramic substrates, glass-epoxy substrates, aramid-epoxy substrates, organic substrates such as paper-phenol substrates, and aluminum substrates and metal substrates such as iron substrates.
【００１７】半導体装置Ａはテーブル７の多孔部７ａ上
に載置されこの状態で、素子２下方の間隙５内は、真空
発生装置８の作動をして多孔部７ａ及び貫通孔６を通じ
吸引され、減圧状態におかれる。The semiconductor device A is placed on the porous portion 7a of the table 7, and in this state, the inside of the gap 5 under the element 2 is sucked through the porous portion 7a and the through hole 6 by operating the vacuum generator 8. , Placed under reduced pressure.
【００１８】間隙５内を減圧状態に保持した状態で液状
封止樹脂３が、スキージ９の作動をしてメタルマスク１
０を通じ、上記素子２の周側部のまわりの全体に転写供
給される。この転写供給状態が図２の左側に概略的に示
されている。この転写供給は周側部に加え素子２の上面
側の全面を被覆するように行なってもよい。The liquid encapsulating resin 3 operates the squeegee 9 while keeping the inside of the gap 5 in a depressurized state to operate the metal mask 1.
Through 0, it is transferred and supplied all around the peripheral side portion of the element 2. This transfer supply state is schematically shown on the left side of FIG. This transfer supply may be performed so as to cover the entire upper surface side of the element 2 in addition to the peripheral side portion.
【００１９】上記素子２の周側部に転写供給された液状
封止樹脂３は隙間５内が減圧に保持されるので、隙間５
内に強制的に吸引充填され、充填後の状態が図２の右側
に概略的に示されている。Since the liquid sealing resin 3 transferred and supplied to the peripheral side portion of the element 2 is maintained in a reduced pressure in the gap 5, the gap 5 is formed.
It is forcibly filled by suction into the inside, and the state after filling is schematically shown on the right side of FIG.
【００２０】この種用途に使用される液状封止樹脂は公
知であり、公知の各種の液状封止樹脂を用い得る。The liquid encapsulating resin used for this type of application is known, and various known liquid encapsulating resins can be used.
【００２１】本発明において、樹脂封止は、通常の空気
雰囲気中はもとより、不活性ガス又は不活性液体の雰囲
気中で実施することができる。In the present invention, the resin sealing can be carried out not only in a normal air atmosphere but also in an atmosphere of an inert gas or an inert liquid.
【００２２】[0022]
【発明の効果】本発明製造方法によれば、次の通りの効
果が得られる。According to the manufacturing method of the present invention, the following effects can be obtained.
【００２３】 隙間５内に液状封止樹脂３を吸引減圧
により強制的に吸引充填できるので、樹脂封止に要する
時間を従来法の例えば５〜１５分程度から例えば１０秒
程度にまで短縮できる。Since the liquid sealing resin 3 can be forcibly sucked and filled into the gap 5 by suction decompression, the time required for resin sealing can be shortened from about 5 to 15 minutes in the conventional method to about 10 seconds.
【００２４】 減圧吸引方式であるので、封止樹脂中
に気泡が含まれることがなくなり、樹脂封止の信頼性を
向上できる。Since the vacuum suction method is used, bubbles are not contained in the sealing resin, and the reliability of resin sealing can be improved.
【００２５】 減圧吸引方式であるので、液状封止樹
脂の粘度は吸引が可能な範囲であれば多少高くとも特に
問題はなく、信頼性の高い樹脂配合が可能になる。Since the vacuum suction method is used, there is no particular problem even if the viscosity of the liquid encapsulating resin is slightly high as long as the viscosity can be sucked, and highly reliable resin blending is possible.
【００２６】 減圧吸引方式であるので、基板を予熱
する必要がなくなる。Since the vacuum suction method is used, it is not necessary to preheat the substrate.
【００２７】 減圧吸引方式であるので、０．０５ｍ
ｍ以下のような小さな隙間に対しても支障なく封止樹脂
を充填できる。Since it is a vacuum suction method, 0.05 m
The sealing resin can be filled even in a small gap of m or less without any trouble.
【００２８】[0028]
【実験例】以下に本発明の実験例１，２を上げ、比較例
１，２と比較すると、表１，２の通りである。[Experimental Examples] Experimental Examples 1 and 2 of the present invention are listed below and are compared with Comparative Examples 1 and 2 as shown in Tables 1 and 2.
【００２９】実験例１ フリップチップが搭載される位置の中央に直径０．３ｍ
ｍの貫通穴をあけた厚さ０．５ｍｍのガラスセラミック
基板上に厚さ０．４ｍｍ×１２ｍｍ×１２ｍｍのフリッ
プチップを高さ５０μｍのハンダバンプで接続されたも
のをフリップチップ封止用の樹脂、ＮＦ−５００Ｚ−１
（商品名、日本レック（株）製、粘度４０ポイズ）で図
１にもとづき印刷によって封止した。Experimental Example 1 Diameter 0.3 m in the center of the position where the flip chip is mounted
A resin for flip chip sealing, in which a 0.4 mm × 12 mm × 12 mm thick flip chip is connected by a solder bump having a height of 50 μm on a 0.5 mm thick glass ceramic substrate having a through hole of m. NF-500Z-1
(Trade name, manufactured by Nippon Lec Co., Ltd., viscosity 40 poise) was used to seal by printing based on FIG.
【００３０】実験例２ フリップチップが搭載される位置の中央に直径０．３ｍ
ｍの貫通穴をあけた厚さ０．５ｍｍのガラスセラミック
基板上に厚さ０．４ｍｍ×１２ｍｍ×１２ｍｍのフリッ
プチップを高さ５０μｍのハンダバンプで接続されたも
のをフリップチップ封止用の樹脂、ＮＦ−５００Ｚ−２
（商品名、日本レック（株）製、粘度１２０ポイズ）で
図１にもとづき印刷によって封止した。Experimental Example 2 Diameter 0.3 m in the center of the position where the flip chip is mounted
A resin for flip chip sealing, in which a 0.4 mm × 12 mm × 12 mm thick flip chip is connected by a solder bump having a height of 50 μm on a 0.5 mm thick glass ceramic substrate having a through hole of m. NF-500Z-2
(Trade name, manufactured by Nippon Lec Co., Ltd., viscosity 120 poise) was used to seal by printing based on FIG.
【００３１】比較例１ 厚さ０．５ｍｍのガラスセラミック基板上に厚さ０．４
ｍｍ×１２ｍｍ×１２ｍｍのフリップチップを高さ５０
μｍのハンダバンプで接続されたものをフリップチップ
封止用の樹脂、ＮＦ−５００Ｚ−１（商品名、日本レッ
ク（株）製、粘度４０ポイズ）でディスペンサーによっ
てチップの側面に吐出し図３にもとづき封止した。Comparative Example 1 A glass ceramic substrate having a thickness of 0.5 mm and a thickness of 0.4
Height of flip chip of mm × 12mm × 12mm 50
What was connected with a solder bump of μm was discharged to the side of the chip with a dispenser using a resin for flip chip sealing, NF-500Z-1 (trade name, manufactured by Nippon Lec Co., Ltd., viscosity 40 poise), and based on FIG. Sealed.
【００３２】比較例２ 厚さ０．５ｍｍのガラスセラミック基板上に厚さ０．４
ｍｍ×１２ｍｍ×１２ｍｍのフリップチップを高さ５０
μｍのハンダバンプで接続されたものをフリップチップ
封止用の樹脂、ＮＦ−５００Ｚ−２（商品名、日本レッ
ク（株）製、粘度１２０ポイズ）でディスペンサーによ
ってチップの側面に吐出し図３にもとづき封止した。COMPARATIVE EXAMPLE 2 A glass ceramic substrate having a thickness of 0.5 mm has a thickness of 0.4.
Height of flip chip of mm × 12mm × 12mm 50
What was connected with a solder bump of μm was discharged to the side of the chip by a dispenser with a resin for flip chip sealing, NF-500Z-2 (trade name, manufactured by Nippon Lec Co., Ltd., viscosity 120 poise), and based on FIG. Sealed.
【００３３】[0033]
【００３４】[0034]
【表１】 [Table 1]
【図１】 本発明製造方法の１実施状況を概略的に示す
模式図である。FIG. 1 is a schematic view schematically showing one implementation situation of the production method of the present invention.
【図２】 液状封止樹脂の吸引充填状況を示す説明図で
ある。FIG. 2 is an explanatory diagram showing a suction filling state of a liquid sealing resin.
【図３】 従来法の説明図である。FIG. 3 is an explanatory diagram of a conventional method.
１ 基板 ２ フリップチップ素子 ３ 液状封止樹脂 ４ バンプ ５ 隙間 ６ 貫通孔 ７ テーブル ８ 真空発生装置 ９ スキージ 10 メタルマスク 1 Substrate 2 Flip Chip Element 3 Liquid Sealing Resin 4 Bump 5 Gap 6 Through Hole 7 Table 8 Vacuum Generator 9 Squeegee 10 Metal Mask
Claims (1)
介し搭載した後に、上記基板と素子との間に生ずるバン
プにもとづく隙間内に液状封止樹脂を充填する半導体の
製造方法において、上記基板の上記素子が搭載される位
置の略々中央部に予め貫通孔を形成しておき、該貫通孔
を通じて上記隙間内を減圧状態に保持することにより、
液状封止樹脂を上記隙間内に強制的に吸引充填すること
を特徴とする半導体の製造方法。1. A method for manufacturing a semiconductor, comprising: mounting a flip-chip element on a substrate via bumps, and then filling a liquid sealing resin in a gap formed by the bumps between the substrate and the element. By forming a through hole in advance in the substantially central portion of the position where the element is mounted, and maintaining the inside of the gap in a reduced pressure state through the through hole,
A method for manufacturing a semiconductor, characterized in that a liquid sealing resin is forcibly suction-filled into the gap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5274480A JP2612536B2 (en) | 1993-11-02 | 1993-11-02 | Semiconductor manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5274480A JP2612536B2 (en) | 1993-11-02 | 1993-11-02 | Semiconductor manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07130794A true JPH07130794A (en) | 1995-05-19 |
| JP2612536B2 JP2612536B2 (en) | 1997-05-21 |
Family
ID=17542283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5274480A Expired - Lifetime JP2612536B2 (en) | 1993-11-02 | 1993-11-02 | Semiconductor manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2612536B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL1011949C2 (en) * | 1999-05-03 | 2000-11-06 | Fico Bv | Manufacturing method for electronic chip scale package, uses small opening in chip to allow trapped air bubble to vent during encapsulation |
| US6483190B1 (en) | 1999-10-20 | 2002-11-19 | Fujitsu Limited | Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method |
| JP2011126227A (en) * | 2009-12-21 | 2011-06-30 | Canon Inc | Liquid jet recording head and method for manufacturing the same |
| JP2011244016A (en) * | 2007-10-03 | 2011-12-01 | Fujikura Ltd | Method of manufacturing module |
| JP2014027095A (en) * | 2012-07-26 | 2014-02-06 | Denso Corp | Electronic device and manufacturing method therefor |
| CN107567186A (en) * | 2017-08-28 | 2018-01-09 | 维沃移动通信有限公司 | A kind of attaching method and circuit board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3081632U (en) * | 2001-05-09 | 2001-11-16 | ヒキタ工業株式会社 | Medical infectious wastewater treatment equipment |
-
1993
- 1993-11-02 JP JP5274480A patent/JP2612536B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3081632U (en) * | 2001-05-09 | 2001-11-16 | ヒキタ工業株式会社 | Medical infectious wastewater treatment equipment |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL1011949C2 (en) * | 1999-05-03 | 2000-11-06 | Fico Bv | Manufacturing method for electronic chip scale package, uses small opening in chip to allow trapped air bubble to vent during encapsulation |
| US6483190B1 (en) | 1999-10-20 | 2002-11-19 | Fujitsu Limited | Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method |
| US7436062B2 (en) | 1999-10-20 | 2008-10-14 | Fujitsu Limited | Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method |
| JP2011244016A (en) * | 2007-10-03 | 2011-12-01 | Fujikura Ltd | Method of manufacturing module |
| JP2011126227A (en) * | 2009-12-21 | 2011-06-30 | Canon Inc | Liquid jet recording head and method for manufacturing the same |
| JP2014027095A (en) * | 2012-07-26 | 2014-02-06 | Denso Corp | Electronic device and manufacturing method therefor |
| CN107567186A (en) * | 2017-08-28 | 2018-01-09 | 维沃移动通信有限公司 | A kind of attaching method and circuit board |
| CN107567186B (en) * | 2017-08-28 | 2020-04-24 | 维沃移动通信有限公司 | Surface mounting method and circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2612536B2 (en) | 1997-05-21 |
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