JPH07123428A - Digital convergence corrector and image display device provided with the same - Google Patents

Abstract

PURPOSE:To suppress the increase of memory capacity without complicating the configuration and without damaging the quality of displayed images at the upper and lower parts of a screen by defining a prescribed alternative address as an image memory read address in a picture display outside area. CONSTITUTION:When the number of scanning lines is more than the address of an image memory 1 and the maximum lines are reached, a row address counter 2 stops counting and continuously outputs a maximum row address by using a row address counter stop circuit 4. Then, a downside picture display outside area (SP) corresponding to a lower edge V of this picture raster is read out. Similarly, the upside SP is also read out by the alternative address corresponding to an upper edge V of the picture raster, picture quality can be prevented without extending the memory capacity from being degraded by distorting the scanning lines, and the capacity extension of the image memory can be suppressed without complicating the configuration and without damaging the quality of displayed pictures at the upper and lower parts of the screen.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital convergence correction device used for convergence correction in an image display device such as a color television receiver or a display terminal using a CRT (cathode ray tube). .

[0002]

2. Description of the Related Art A digital convergence correction device is
It is a device that sequentially reads the correction data stored in the memory beforehand according to the display screen position and uses it to perform convergence correction, and makes each correction data suitable for each position on the display screen. Therefore, it is possible to perform the convergence correction with high accuracy.

During normal screen reproduction, for example, NTSC
In the television signal according to the method, one screen is composed of 1
The number of scanning lines in the field is 262.5, of which about 24 are actually used for the visible screen display area.
It is about 0. The remaining 22.5 lines are scanning lines that do not contribute to the display in the upper and lower areas of the screen.

If the vertical memory address of the memory that stores the convergence correction data is 8 bits, the maximum number of addresses that can be represented by 8 bits is 256, so that only 256 scanning lines can be supported. Become. For 6.5 lines, which is a difference from the number of scanning lines in one field of 262.5, the convergence correction data cannot be read because addressing cannot be performed, so that faithful convergence correction cannot be performed. The area where these 6.5 scanning lines are present is an off-screen area outside the visible screen display area. However, if the convergence correction here is extremely inappropriate, this original off-screen area will be displayed. A certain scanning line may be distorted and appear in the screen display area, thus deteriorating the image quality.

In particular, during special reproduction of a VTR or the like, the number of scanning lines increases, the number of addresses corresponding to even scanning lines in the display area is insufficient, and the correction data corresponding to each scanning line cannot be read. There is a risk that it will not be possible to perform proper convergence correction. The simplest way to solve this problem is to make the vertical memory address 9 bits and increase the number of addresses that can be expressed sufficiently.

However, this method requires double the memory capacity, which inevitably increases the cost. Then, as a conventional example which copes with this problem without increasing the memory capacity, for example, a technique described in JP-A-1-192289 can be cited.

[0007]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the technique described in Japanese Patent No. 289, after the second address creating means along the vertical scanning direction on the display screen outputs the final address for reading the convergence correction data, the second address creating means resets it in the vertical scanning direction. The method continues to output the final address until the first address along the line is output (that is, while scanning the invisible area outside the screen).

According to this method, in the lower area of the display screen, even if the convergence correction data corresponding to each scanning line cannot be read out from the memory because the number of addresses is insufficient due to insufficient memory capacity, the second address Since the correction data read out by the final address output by the creating means is substituted, the final address is adjacent to the lower area, so the correction data close to the optimum value is used. There is no possibility that the scanning line that should be in the area is distorted and appears in the screen display area and the image quality is deteriorated.

However, not only in the lower area of the display screen, but also in the upper area of the display screen, the second address creating means resets and outputs the first address in the vertical scanning direction. Since the correction data read out by the final address is used during the interval, the scanning line that should originally be in the off-screen area (upper part) is distorted and appears in the screen display area, which may impair the image quality. . When the correction data read by the final address output by the second address creating means is substituted,
The reason why the image quality cannot be impaired in the lower area of the display screen but the image quality can be impaired in the upper area of the display screen will be described below with reference to FIG.

FIG. 3 is an explanatory view showing the raster shapes before and after the convergence correction on the display screen. In the figure, W is the display screen, U is the raster shape before convergence correction, and V is the raster shape after convergence correction.
Each SP represents an invisible area that does not contribute to the display.

In the lower part of the display screen, the raster shape U before the convergence correction is a scanning line (raster) having an upward convex shape, but this is corrected by the convergence correction so that it becomes a straight line, and after the correction. The raster shape V is obtained. That is, the convergence correction data in the lower part of the display screen is data for correcting the scanning line having the upward convex shape into the linear scanning line.

On the other hand, in the upper part of the display screen, the raster shape U before the convergence correction is a scanning line (raster) having a downward convex shape, which is corrected by the convergence correction to be a straight line. The raster shape V after correction is obtained. That is, the convergence correction data in the upper part of the display screen is data for correcting the scanning line having a downward convex shape into a linear scanning line. In other words, in the lower part of the display screen and the upper part of the display screen, the correction tendencies of the convergence correction data used there are opposite to each other (the tendency is from top to bottom at the bottom of the display screen and from bottom to top at the top of the display screen).
It means that

Therefore, even if the convergence correction data in the lower part of the display screen is applied to the invisible area SP in the lower part of the display screen, the data is used to correct the scanning line having the upward convex shape into the linear scanning line ( Since there is a tendency of correction from top to bottom, there is no risk that the scan line will be distorted and appear in the visible area. However, when the convergence correction data in the lower part of the display screen is applied to the invisible area SP in the upper part of the display screen, it is data for correcting the scanning line having the upward convex shape into the linear scanning line (correction from top to bottom). However, even if it is not, the scanning line has a convex shape downward in the upper part of the display screen, so that it becomes more and more sagging, that is, the scanning line becomes more and more distorted downward and becomes visible. It can happen that it appears.

As described above, the above-mentioned JP-A-1-192 is used.
In the conventional digital convergence correction device as described in Japanese Patent No. 289, there is a problem in that the scanning line originally supposed to be in the outer area of the upper screen is distorted and appears in the screen display area, which may impair the image quality. .

The object of the present invention is to overcome the problems of the prior art as described above, and to display on both the upper and lower portions of the screen regardless of the number of scanning lines appearing during special reproduction such as VTR. An object of the present invention is to provide a digital convergence correction device that does not impair the quality of an image and yet requires a minimum memory capacity, and an image display device including the same.

[0016]

In order to solve the above problems, according to the present invention, in a row address counter (second address creating means) for generating a read address for a memory for storing convergence correction data, a maximum row address (final address) Address) and stop counting, then start the count after stopping the stop period and the timing to reset the row address counter and generate the minimum row address (first address) independently. I made it possible.

That is, the row address counter stops counting when it reaches the maximum row address (final address) and continues to output the final address thereafter, but when the scanning of the scanning line shifts from the lower part of the screen to the upper part, The row address counter resets and generates the first address at the timing, but the count does not start, so the first address continues to be output, and then, when the scanning line advances to the screen display area, the count starts at that timing. Then, the address is sequentially generated thereafter.

[0018]

When the number of scanning lines is larger than the memory row address,
Row address counter is maximum row address (final address)
The counting is stopped at, and as a result, the correction data of the maximum row address is continuously read at the lower part of the screen and its vicinity. Further, in the upper part of the screen and in the vicinity thereof, the row address counter is reset and the address counting is continuously stopped for a certain period, so that the correction data of the minimum row address (first address) is continuously read.

Therefore, the convergence correction data at the bottom of the screen is not read out at the top of the screen, and the correction data close to the optimum value is always read out of the display area of the screen. Therefore, even with the minimum required memory capacity, the scanning lines outside the display area in the upper part of the screen do not appear in the display area and the quality of the displayed image is not impaired.

[0020]

1 is a block diagram showing an address generating circuit and a memory for storing convergence correction data, which is a main part of a first embodiment of the present invention. FIG. 2 is a block diagram showing the overall configuration of the first embodiment of the present invention. An embodiment of the present invention will be described below with reference to these two drawings.

In FIG. 2, reference numeral 14 is a CPU, which controls the entire digital convergence correction apparatus. An address generation circuit 15 supplies a read address to the memory 1 in synchronization with screen scanning. Reference numeral 1 denotes a memory, which stores convergence correction data. A D / A converter 17 converts digital data read from the memory 1 into an analog voltage.

Reference numeral 18 denotes an LPF (Low Pass Filter), which removes high frequency components contained in the output of the D / A converter 17 to form a smooth waveform. 25 is CY (Convergenc
e Yoke), and a current is passed through the coil of the CY 25 to generate a magnetic field, thereby bending the trajectory of the electron beam of the CRT 23 and performing convergence correction. A CY amplifier 19 converts the output voltage of the LPF 18 into a current and drives the CY 25. 23 is a CRT (Cathod Ray Tube),
Converts electrical signals into images.

Reference numeral 20 is a high voltage generating circuit, which is a circuit necessary for accelerating the electron beam of the CRT 23. 24 is DY (De
a deflection yoke, and by applying a deflection current to the DY coil to generate a deflection magnetic field, CR
The trajectory of the electron beam at T23 is bent and scanning is performed. Reference numeral 21 is a deflection circuit, which drives the DY 24 and supplies a necessary deflection current. A video circuit 22 supplies a video signal for driving the cathode of the CRT 23.

Reference numeral 12 is a horizontal convergence correction unit for performing horizontal convergence correction, and 13 is a vertical convergence correction unit for performing vertical convergence correction. Horizontal convergence correction unit 1
2 and the vertical convergence correction unit 13 have basically the same configuration. During normal use, the address generation circuit 15
The correction data of the memory 1 is read out according to the address from, and the convergence correction is performed. The present invention is particularly characterized by the circuit configuration of the address generation circuit 15 among the above configurations. Details of the address generation circuit 15 will be described below with reference to FIG.

In FIG. 1, reference numeral 1 denotes a memory for storing convergence correction data, which has m horizontal and n vertical address lines. Reference numeral 2 is a row address counter, and 3 is a column address counter, each of which performs a counting operation by a clock input to a clock input terminal C and is reset by a reset signal input to a reset input R. The input terminal E of the row address counter 2 is a count enable terminal and is used for controlling the count operation.

Reference numeral 4 is a counter stop circuit, 7 is a counter reset signal generating circuit, 6 is an input video signal, and 9 is a frequency multiplication circuit. The counter reset signal creation circuit 7 is a circuit that creates reset signals 700 and 701 for the row address counter 2 and the column address counter 3, respectively, from the input video signal. Basically, the reset signal 700 is a vertical synchronizing signal included in the input video signal or a signal synchronized therewith, and the reset signal 701 is a horizontal synchronizing signal included in the input video signal or a signal synchronized therewith. The frequency multiplication circuit 9 multiplies the reset signal 701 to generate a clock having a desired frequency. The horizontal reset signal 701 is also used as a clock for counting the row address of the row address counter 2.

The counter stop circuit 4 stops the operation of the row address counter 2 by controlling the count enable terminal E by the route 2 when it detects that the row address counter 2 has sent out the last row address by the route 1. Let After that, when the vertical synchronizing signal detected from the input video signal 6 is sent from the reset signal generating circuit 7 as the vertical reset signal 700, the counter stop circuit 4
Receives this, but controls the count enable terminal E by the route 2 after a lapse of a certain time (that is, after a certain delay) to restart the counting operation of the row address counter 2.

However, in the row address counter 2, the vertical synchronizing signal detected from the input video signal 6 is sent from the reset signal generating circuit 7 as the vertical reset signal 700 at the timing when it is received at the reset terminal R. The contents of the address generated by the reset are changed from the last line address to the first line address.

However, the count of the clock is not started just because the generated address is changed from the last line address to the first line address, and therefore the state of outputting the first line address continues for a while. After a while, the counter stop circuit 4 uses the route 2 to enable the count enable terminal E.
For the first time, the row address counter 2 restarts the counting operation, and thereafter sequentially generates addresses.

Therefore, when the number of vertical scanning lines exceeds the total number of addresses from the first address to the last row address, when the address value generated by the row address counter 2 reaches the last row address, the row address counter 2 causes the last row address to be detected. After the address is transmitted, the last row address is continuously transmitted until the vertical reset signal 700 is input, and after the vertical reset signal 700 is input, the first row address is continuously transmitted instead of the last row address for a certain period of time, and thereafter. , The counting operation is started, counting up is performed for each scanning line, and a row address corresponding to the scanning line position is generated.

The operation of the row address counter 2 described above will be described below in accordance with the vertical scanning of the display screen shown in FIG. The number of vertical scanning lines changes from the top address (upper end of raster shape V) to the last row address (raster shape V
If the address value generated by the row address counter 2 reaches the final row address (the lower edge of the raster shape V) when the total number of addresses up to the lower edge of the raster shape V is exceeded, the row address counter 2
Continues to send the last row address after sending the last row address until the vertical reset signal 700 is input (during the lower SP area), and after the vertical reset signal 700 is input, for a certain period of time (upper SP area). During the period), the first row address (the upper end of the raster shape V) is continuously transmitted instead of the final row address, and thereafter (at the upper end of the raster shape V), the counting operation is started to count up for each scanning line. ,
A row address corresponding to the scan line position is generated.

On the other hand, if the number of vertical scanning lines is less than the total number of addresses from the first address to the last row address,
Since the vertical reset signal is input before the address value of the row address counter 2 reaches the final row address, the counting operation of the row address counter 2 does not stop at the lower part of the screen, and after the vertical reset signal 700 is input, it remains constant. The counter operation is stopped only during the period (in the upper SP area), the first row address is continuously transmitted, and thereafter (at the upper end of the raster shape V), the counting operation is started to count up every scanning line and scan. A row address corresponding to the line position will be generated.

Next, FIG. 4 is a block diagram showing a first specific example of the counter reset signal generating circuit 7 in FIG. As can be seen from FIG. 4, in the counter reset signal generation circuit 7, the sync separation circuit 71 extracts the vertical synchronization signal and the horizontal synchronization signal from the video signal 6, and the reset signals 700,
It is output as 701.

FIG. 5 is a block diagram showing a second specific example of the counter reset signal generating circuit 7 in FIG.
In FIG. 5, 71 is a sync separation circuit, 72 and 74 are waveform shaping circuits respectively, and 73 is an AFC (Automatic Frequency).
Control) circuit, and 21 is a deflection circuit.

The horizontal sync signal output from the sync separation circuit 71 is not directly used as the horizontal reset signal 701, but is synchronized with the horizontal sync signal by the AFC circuit 73.
A horizontal reset signal 701 that faithfully corresponds to scanning is created. It is possible to obtain a stable horizontal reset signal 701 as compared with the method of directly using the synchronization signal.

FIG. 6 is a block diagram showing a concrete example of the frequency multiplication circuit 9 in FIG. 75 is a frequency dividing circuit, 76
Is a phase comparator, and 77 is a VCO (Voltage Controlled Osc).
illator). The clock 900 for the column address counter 3 includes a phase comparator 76, a VCO 77, a frequency dividing circuit 75.
The horizontal reset signal 701 is multiplied by N by a PLL (Phase Locked Loop) configured by.

FIG. 7 is a block diagram showing a first specific example of the row address generator (row address counter stop circuit 4, row address counter 2) of FIG. In FIG. 7, 2
6 is a delay circuit, 700 is a vertical reset signal, 701 is a horizontal reset signal, 29 is an SR latch, 2 is a row address counter, 32 is an address decoder, and 310 is a row address supplied to a memory for storing convergence correction data. .

FIG. 8 is a timing chart showing the operation of each part of the circuit of FIG. The operation will be described below with reference to FIGS. The address decoder 32 detects that the address value output from the counter 2 has become equal to the final row address Ae, and resets the SR latch 29 via the OR circuit. The output of the SR latch 29 is connected to the enable terminal E of the counter 2, and the reset operation of the counter 2 is stopped by the reset of the SR latch 29.

When the vertical reset signal 700 is input,
The SR latch 29 is reset again through the OR circuit and the counter 2 continues to stop operating, but at the same time, the vertical reset signal 7 is also applied to the reset terminal R of the counter 2.
Since 00 is input, the counter value of the counter 2 changes to the top row address As. Vertical reset signal 70
Since 0 is further connected to the set terminal S of the SR latch via the delay circuit 26, the vertical reset signal 700
The SR latch 29 is set after a lapse of a certain time from the input of, and the enable terminal E of the counter 2 is controlled to restart the counting operation of the counter 2.

FIG. 9 is a block diagram showing a second specific example of the row address generator of FIG. Basically, the circuit has the same configuration as that of FIG. 7, except that the counter 2 is of a preset type and that a preset address register 30 is provided. Since the counter 2 is of the preset type, it is possible to set an arbitrary top row address As. Similarly, the decoder 32 can also be of a preset type by having a configuration of an address register and a comparator.

According to this embodiment, when the number of vertical scanning lines exceeds the total number of addresses from the first address to the last line address, the correction data of the last line address is displayed at the bottom of the screen and the correction data of the top line is displayed at the top of the screen. Since the correction data of the row address is continuously output, the shape of the scanning line outside the screen area is not distorted and appears on the screen without impairing the display image quality. Further, even if the number of scanning lines in the display area is increased by special reproduction such as VTR, the display image quality is not significantly deteriorated. Furthermore, the memory capacity can be minimized.

FIG. 10 is a block diagram showing the essential parts of the second embodiment of the present invention. The only difference from that shown in FIG. 1 is the row address generator. In FIG. 10, reference numeral 410 is a lower row address control circuit, 450 is an upper row address control circuit, and 360 is an address switching circuit.
Further, in FIG. 10, the same numbers as in FIG. 1 represent the same items.

The output of the lower row address control circuit 410 is
The row address counter 2 is set when the final address is transmitted, and reset when the vertical reset signal 700 is input. The upper row address control circuit 450 is
The vertical reset signal 700 is internally delayed and output as a reset signal for the row address counter 2, while the delay period from the input of the vertical reset signal 700 until the reset pulse is supplied to the row address counter 2 is set as a pulse. It is supplied to the address switching circuit 360.

Address switching circuit 360 switches the output address according to the output level of lower row address control circuit 410 and the output level of upper row address control circuit 450. When the output of the lower row address control circuit 410 becomes high level, the address switching circuit 36
0, the first specific address set inside 0, and when the output of the upper row address control circuit 450 becomes high level, the second specific address set inside the address switching circuit 360, otherwise. Row address counter 2
The outputs of the above are switched and output and supplied to the memory 1.

FIG. 11 is a block diagram showing a specific example of the row address generator (lower row address control circuit 410, upper row address control circuit 450, row address counter 2, address switching circuit 360) of FIG.

In FIG. 11, reference numeral 26 denotes a delay circuit, 700
Is a vertical reset signal, 701 is a horizontal reset signal, 40
0 and 410 are SR latches, 2 is a counter, 32
Is an address decoder. The SR latch 410 is shown in FIG.
0 is the lower row address control circuit 410 itself. Three
0 is an upper row address setting register, 31 is a lower row address setting register, 310 is an output row address of the counter 2, 320 is an upper row address, and 330 is a lower row address.

An address selector 350 is a combination of the output levels of the SR latches 400 and 410, and selectively supplies the counter address 310, the upper row address 330 and the lower row address 320 to the memory as the row address 340.

In this embodiment, when the number of vertical scanning lines exceeds the total number of addresses from the first address to the last line address, the off-screen area at the upper part of the screen and the off-screen area at the lower part of the screen are independent of each other. The row address can be set and the correction data of any desired row can be continuously output.

[0049]

As described above, according to the present invention,
If the number of vertical scanning lines exceeds the total number of addresses from the start address to the end line address, the correction data of the start line address is displayed in the off-screen area at the top of the screen and the correction data of the end line address is displayed in the off-screen area at the bottom of the screen. The shape of the scan line outside the screen area is distorted and appears on the screen in order to continue to output,
There is no loss of display quality. Further, even if the number of scanning lines in the display area is increased by special reproduction such as VTR, the display image quality is not significantly deteriorated. Furthermore, the memory capacity can be kept to the minimum required, which is the same as the conventional one.

[Brief description of drawings]

FIG. 1 is a block diagram showing an address generating circuit and a memory for storing convergence correction data, as an essential part of a first embodiment of the present invention.

FIG. 2 is a block diagram showing an overall configuration of a first exemplary embodiment of the present invention.

FIG. 3 is an explanatory diagram showing raster shapes before and after convergence correction on a display screen of an image display device.

FIG. 4 is a counter reset signal generation circuit 7 in FIG.
3 is a block diagram showing a first specific example of FIG.

5 is a counter reset signal generation circuit 7 in FIG.
It is a block diagram showing the 2nd specific example of.

FIG. 6 is a block diagram showing a specific example of a frequency multiplication circuit 9 in FIG.

7 is a block diagram showing a first specific example of the row address generation unit (row address counter stop circuit 4, row address counter 2) in FIG. 1. FIG.

8 is a timing chart showing the operation of each part of the circuit of FIG.

9 is a block diagram showing a second specific example of the row address generation unit in FIG.

FIG. 10 is a block diagram showing a main part of a second embodiment of the present invention.

11 is a block diagram showing a specific example of the row address generator (lower row address control circuit 410, upper row address control circuit 450, row address counter 2, address switching circuit 360) of FIG.

[Explanation of symbols]

1 ... Memory, 2 ... Row address counter, 3 ... Column address counter, 4 ... Row address counter stop circuit, 6 ... Input video signal, 7 ... Reset signal generation circuit, 9 ... Frequency multiplication circuit, 15 ... Address generation circuit, 17 ... D / A converter, 18 ... LPF (low-pass filter), 19 ... CY
Amplifier, 23 ... CRT, 25 ... CY (convergence yoke)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kuninori Matsumi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi Imaging Information Systems Co., Ltd.

Claims (3)

[Claims] 1. A correction data storage memory for storing convergence correction data on a cathode ray tube screen in correspondence with positions on horizontal and vertical scanning lines on the screen, and a clock count in synchronization with scanning in the horizontal scanning direction on the screen. And a first address generating means for outputting the count output as a first address signal for reading correction data corresponding to each position on the horizontal scanning line from the memory, and a vertical scanning direction in the screen. Second address generation means for counting clocks in synchronization with scanning and outputting the count output as a second address signal for reading correction data corresponding to each position on the vertical scanning line from the memory. , And with the horizontal and vertical scanning on the cathode ray tube screen, In a digital convergence correction device that reads out required correction data using a dress signal to perform convergence correction on a cathode ray tube screen, the second address generation means generates and outputs a final address signal in the vertical scanning direction. When detected,
When the clock count operation in the second address generation means is stopped, and thereafter the address count stop means for maintaining the generation and output of the final address signal and the vertical synchronization signal in the video signal to be the target of the convergence correction are detected. , In synchronism with this, the address value to be generated and output by the second address generating means is reset, and the generation and output of the first address signal from the generation and output of the final address signal in the vertical scanning direction until then Address resetting means for returning the counting operation to a stop state, and address counting starting means for restarting the counting operation in the second address generating means at a specific timing after a certain time has elapsed after the address resetting. , A digital convergent characterized in that Correction device. 2. A correction data storage memory for storing convergence correction data on a cathode ray tube screen in correspondence with positions on horizontal and vertical scanning lines on the screen, and clock counting in synchronization with scanning in the horizontal scanning direction on the screen. And a first address generating means for outputting the count output as a first address signal for reading correction data corresponding to each position on the horizontal scanning line from the memory, and a vertical scanning direction in the screen. Second address generation means for counting clocks in synchronization with scanning and outputting the count output as a second address signal for reading correction data corresponding to each position on the vertical scanning line from the memory. , And with the horizontal and vertical scanning on the cathode ray tube screen, In a digital convergence correction device that reads out required correction data using a dress signal and performs convergence correction on a cathode ray tube screen, a first specific row address sending means, a second specific row address sending means, and the second When the address generating means detects the generation and output of the final address signal in the vertical scanning direction,
The first specific row address sending means is selected, and the first
In place of the address signal from the second address generating means, the specific row address signal is continuously output as an address signal for reading the correction data from the memory thereafter, and an image to be subjected to convergence correction is displayed. When a vertical synchronizing signal in the signal is detected, in synchronization therewith, the selection of the first specific row address transmitting means is stopped, and the first control means for stopping the output of the first specific row address signal, and the convergence. When the vertical synchronizing signal in the video signal to be corrected is detected, the second specific row address sending means is selected in synchronization with the vertical synchronizing signal, and the second specific row address signal is subsequently corrected data from the memory. Is continuously output as an address signal for reading, and after the vertical synchronization signal is detected, at a specific timing after a certain time has passed, The selection of the second specific row address transmitting means is stopped, the output of the second specific row address signal is stopped, and the second address generating means is reset to generate and output the first address signal. And a second control means for starting the counting operation from the second address selection means and for selecting and outputting the address signal from the second address generation means, the digital convergence correction apparatus. 3. An image display device comprising the digital convergence correction device according to claim 1.