JPH07123184B2 - High-density mounting circuit board manufacturing method - Google Patents
High-density mounting circuit board manufacturing methodInfo
- Publication number
- JPH07123184B2 JPH07123184B2 JP3353235A JP35323591A JPH07123184B2 JP H07123184 B2 JPH07123184 B2 JP H07123184B2 JP 3353235 A JP3353235 A JP 3353235A JP 35323591 A JP35323591 A JP 35323591A JP H07123184 B2 JPH07123184 B2 JP H07123184B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- solder bump
- circuit board
- board manufacturing
- density mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子を内装した
高密度実装回路基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a high-density packaging circuit board containing semiconductor elements.
【０００２】[0002]
【従来の技術】図３は従来例の説明図で、実装回路基板
の製造を次のような手順で行っていた。内装基板１の一
部に座ぐり加工等でくぼみ部分２を設け、内部に収容し
た半導体素子３を金ワイヤ４でサーモソニック法により
回路パターンのボンディングパッド５に接続する。2. Description of the Related Art FIG. 3 is an explanatory view of a conventional example, in which a mounted circuit board is manufactured by the following procedure. A recessed portion 2 is provided in a part of the inner substrate 1 by counter boring, and the semiconductor element 3 housed inside is connected to a bonding pad 5 of a circuit pattern by a gold wire 4 by a thermosonic method.
【０００３】ボンディングパッド５は、例えば１８μｍ
の厚さの銅箔の表面にボンディングするため軟質の金め
っきを少なくとも１．４μｍ以上被覆する。また、実装
した半導体素子３を保護するため、チップコート用エポ
キシ樹脂６を塗布し、例えば１６０℃、４時間の熱処理
を行って硬化させる。The bonding pad 5 is, for example, 18 μm.
In order to bond to the surface of the copper foil having the thickness of at least 1.4 μm, at least soft gold plating is coated. Further, in order to protect the mounted semiconductor element 3, an epoxy resin 6 for chip coating is applied and cured by, for example, heat treatment at 160 ° C. for 4 hours.
【０００４】銅箔をエッチング加工した内装基板１の半
田バンプランド７と表装基板８の半田バンプランド７´
を半田９を介して接合する。この接合は圧力を加えなが
ら昇温し半田を溶融して行う。Solder bump lands 7 of the inner substrate 1 and the solder bump lands 7'of the mounting substrate 8 obtained by etching a copper foil.
Are joined via the solder 9. This joining is performed by raising the temperature while applying pressure and melting the solder.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら接合を行
う際、チップコート用エポキシ樹脂６を硬化するときに
発生した有機系付着物１０が半田バンプランド７の表面
に被着し、半田９と半田バンプランド７の界面において
良好な接合が行われず接合強度の低下をきたした。この
ため、熱衝撃試験等を実施すると、半田バンプ接合部分
に剥離を生じるような不具合があった。However, at the time of bonding, the organic deposit 10 generated when the epoxy resin 6 for chip coating is cured adheres to the surface of the solder bump land 7, and the solder 9 and the solder bump. Good bonding was not performed at the interface of the land 7, resulting in a decrease in bonding strength. Therefore, when a thermal shock test or the like is performed, there is a problem that peeling occurs at the solder bump joint portion.
【０００６】なお、この種の被着物は、複合基板間の狭
い領域に発生するため、洗浄による除去やプラズマ現象
を利用する清浄化処理が有効に作用できないという背景
がある。Since this kind of adherend is generated in a narrow region between the composite substrates, there is a background that the removal by cleaning and the cleaning treatment utilizing the plasma phenomenon cannot effectively work.
【０００７】[0007]
【課題を解決するための手段】本発明はこれらの課題を
解決することを目的とし、目的を達成するために半田バ
ンプランド表面に半田材料と拡散性の良好な材料による
僅少量の厚さの被覆層を設け、特に金により厚さ０．１
μｍから０．５μｍの被覆層としたことを特徴とするも
ので、以下実施例につき図面により詳細に説明する。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and in order to achieve the object, the solder bump land surface is made of a solder material and a material having a good diffusibility, and a small amount of thickness. Providing a coating layer, especially gold with a thickness of 0.1
The present invention is characterized in that the coating layer has a thickness of from 0.5 μm to 0.5 μm, and examples will be described in detail below with reference to the drawings.
【０００８】[0008]
【実施例】図１は本発明の実施例で、内装基板１の一部
に座ぐり加工等でくぼみ部分２を設け半導体素子３を収
容し、金ワイヤ４をサーモソニック法により回路パター
ンのボンディングパッド５に接続する。あらかじめボン
ディングパッド５の表面は電解めっきによる軟質金めっ
きを少なくとも１．４μｍ以上行っておく。さらに半田
バンプランド７の表面には、例えば無電解金めっき１１
を厚さ０．３μｍで被覆しておく。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention in which a recessed portion 2 is provided in a part of an interior substrate 1 by a counterboring process to accommodate a semiconductor element 3 and a gold wire 4 is bonded to a circuit pattern by a thermosonic method. Connect to pad 5. The surface of the bonding pad 5 is preliminarily electroplated with a soft gold plating of at least 1.4 μm or more. Further, on the surface of the solder bump land 7, for example, electroless gold plating 11
To have a thickness of 0.3 μm.
【０００９】実装した半導体素子３の保護のためにチッ
プコート用エポキシ樹脂６を塗布し、１６０℃、４時間
の熱処理を行って硬化させる。内装基板１と表装基板８
に設けた半田バンプランド７、７´を半田９（重量比錫
６０％、鉛４０％の共晶半田）を用い、基板上下から圧
力を加えながら２３０℃で６０秒半田を溶融して接合す
る。To protect the mounted semiconductor element 3, a chip coat epoxy resin 6 is applied and heat-treated at 160 ° C. for 4 hours to be hardened. Interior board 1 and exterior board 8
The solder bump lands 7 and 7'provided in the above are joined by using solder 9 (eutectic solder having a weight ratio of 60% tin and 40% lead) at 230 ° C. for 60 seconds while applying pressure from above and below the substrate. .
【００１０】半田バンプ接合界面において、半田バンプ
ランド７の僅少な厚さの無電解金めっき１１は、昇温に
伴い被着した有機系付着物１０を介して半田の錫と相互
拡散現象を起こし、溶融し、半田バンプランド７から消
失する。その際、有機系付着物１０はこれら金属の拡散
現象に伴い破壊され、比重が金属より小さいため溶融半
田の表面へ抽出される。At the solder bump bonding interface, the electroless gold plating 11 with a small thickness of the solder bump land 7 causes a mutual diffusion phenomenon with tin of the solder through the organic deposit 10 deposited as the temperature rises. , Melts and disappears from the solder bump land 7. At that time, the organic deposit 10 is destroyed along with the diffusion phenomenon of these metals, and is extracted to the surface of the molten solder because the specific gravity is smaller than that of the metals.
【００１１】したがって、半田バンプランド７は有機系
付着物が介在しない良好な接合体となり得る。Therefore, the solder bump land 7 can be a good bonded body with no organic deposit.
【００１２】さらに付け加えると、チップコート用エポ
キシ樹脂６の硬化時に発生する有機系付着物１０の量
は、使用する材料系によっても変動するが、カルボキシ
ル酸を硬化剤とした２液性の無溶剤型エポキシ樹脂を使
用した場合は、１６０℃、４時間の硬化処理で半田バン
プランド７のすべての表面に僅少な厚さの有機物を確認
した。この有機物は樹脂硬化時に発生した被着物層と考
えられ、次のような結果を得た。In addition, although the amount of the organic deposit 10 generated during the curing of the epoxy resin 6 for chip coating varies depending on the material system used, a two-component solventless solvent using carboxylic acid as a curing agent. When the type epoxy resin was used, a slight amount of organic matter was confirmed on all the surfaces of the solder bump lands 7 by the curing treatment at 160 ° C. for 4 hours. This organic substance is considered to be the adherend layer generated during resin curing, and the following results were obtained.
【００１３】半田バンプランドの金めっきの厚さと前記
の効果には関係があり、金めっきが厚い場合、使用する
半田材料との相互拡散による表面処理の金めっきの消失
が低下し、拡散に伴う瞬時的有機物被着層の破壊現象と
半田溶融面外への排出現象とが低下する傾向が認められ
た。There is a relation between the thickness of the gold plating of the solder bump land and the above-mentioned effect. When the gold plating is thick, the disappearance of the gold plating in the surface treatment due to the mutual diffusion with the solder material to be used is reduced, which is accompanied by the diffusion. It was confirmed that the phenomenon of instantaneous destruction of the organic material coating layer and the phenomenon of discharge to the outside of the solder melting surface were reduced.
【００１４】また薄い場合には、このような効果が認め
られなかった。この現象は薄い場合には半田との相互拡
散を発生せず、被着物の破壊と排出効果が伴わないため
と考えられる。In the case of a thin film, no such effect was observed. This phenomenon is considered to be because when it is thin, mutual diffusion with solder does not occur, and the destruction and discharge effect of the adherend is not accompanied.
【００１５】図２に半田バンプランドへ被覆した金めっ
きの厚さと、錫６０％、鉛４０％（重量比）の共晶半田
による接合試料の接合部分の引張り強度との関係を示
す。この図から金の厚さが０．１μｍから０．５μｍの
範囲で良好な引張り強度が得られることがわかる。FIG. 2 shows the relationship between the thickness of the gold plating coated on the solder bump lands and the tensile strength of the joint portion of the joint sample made of eutectic solder containing 60% tin and 40% lead (weight ratio). It can be seen from this figure that good tensile strength can be obtained when the gold thickness is in the range of 0.1 μm to 0.5 μm.
【００１６】[0016]
【発明の効果】以上説明したように、半田接合時に半田
と大きな相互拡散を行う薄層を半田バンプランド面に設
けたので、チップコート樹脂の硬化時に発生する有機系
付着物が半田接合界面に介在することがなくなる。した
がって良好な機械的接合力を得ることができ、高い信頼
性を有する半導体素子内装の高密度実装回路基板を製作
することができる。As described above, since the thin layer that causes large mutual diffusion with the solder at the time of solder joining is provided on the solder bump land surface, the organic deposits generated when the chip coat resin is cured are present at the solder joining interface. There is no intervening. Therefore, a good mechanical joining force can be obtained, and a high-density mounting circuit board with a semiconductor element embedded therein having high reliability can be manufactured.
【図１】本発明の実施例を示す断面説明図。FIG. 1 is a sectional explanatory view showing an embodiment of the present invention.
【図２】金めっき被覆の厚さと接合部の引張り強度との
関係を示す図。FIG. 2 is a diagram showing the relationship between the thickness of the gold plating coating and the tensile strength of the joint.
【図３】従来例の断面説明図。FIG. 3 is a cross-sectional explanatory view of a conventional example.
１ 内装基板 ２ くぼみ部分 ３ 半導体素子 ６ チップコート用エポキシ樹脂 ７、７´ 半田バンプランド ８ 表装基板 ９ 半田 １０ 有機系付着物 １１ 無電解金めっき 1 Interior Board 2 Recessed Area 3 Semiconductor Element 6 Epoxy Resin for Chip Coat 7, 7'Solder Bump Land 8 Mounting Board 9 Solder 10 Organic Adhesion 11 Electroless Gold Plating
Claims (1)
くぼみ部分に半導体素子を収容しそれを樹脂により被覆
して成る内装基板と、回路パターンを有する表装基板と
を錫を含む半田を介して加圧・昇温下で貼り合わせる製
造方法において、 あらかじめ基板の半田バンプランドの表面を０．１μｍ
から０．５μｍの厚さで金を被覆したことを特徴とする
高密度実装回路基板の製造方法。1. An internal substrate having a circuit pattern and a recessed portion, a semiconductor element being housed in the recessed portion and covered with a resin, and a mounting board having a circuit pattern via a solder containing tin. In the manufacturing method of bonding under pressure and temperature rise, the surface of the solder bump land of the substrate is 0.1 μm in advance.
To 0.5 μm of gold is coated on the high density packaging circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3353235A JPH07123184B2 (en) | 1991-12-17 | 1991-12-17 | High-density mounting circuit board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3353235A JPH07123184B2 (en) | 1991-12-17 | 1991-12-17 | High-density mounting circuit board manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05167263A JPH05167263A (en) | 1993-07-02 |
| JPH07123184B2 true JPH07123184B2 (en) | 1995-12-25 |
Family
ID=18429471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3353235A Expired - Fee Related JPH07123184B2 (en) | 1991-12-17 | 1991-12-17 | High-density mounting circuit board manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07123184B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4137659B2 (en) * | 2003-02-13 | 2008-08-20 | 新光電気工業株式会社 | Electronic component mounting structure and manufacturing method thereof |
-
1991
- 1991-12-17 JP JP3353235A patent/JPH07123184B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05167263A (en) | 1993-07-02 |
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