JPH07123124A - Radio reception equipment - Google Patents

Abstract

PURPOSE:To detect a specific pattern such as a preamble pattern by a circuit of a simple configuration in the radio reception equipment such as a portable telephone. CONSTITUTION:The radio reception equipment which receives a transmitted signal wherein a preamble consisting of successive data of one predetermined pattern is added to data and detects the data included in the received signal in synchronism with the output of a PLL circuit whose phase is locked to the synchronizing signal included in the received signal is provided with detecting means 103-116 which detect the predetermined pattern and a counter 118 which counts the frequency of succession of detection frequencies of the detecting means 103 and 116; when the counted value of the counter 118 reaches a specific value, it is considered that the preamble is detected, and phase lead-in control over the PLL circuit is started.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio receiver suitable for application to a radio receiver for receiving burst data, for example.

[0002]

2. Description of the Related Art In a digital cordless telephone such as a telepoint system or a personal handyphone, the same frequency is used for transmission and reception, and TDD method (time division duplex method) in which burst data is transmitted in a time division manner, that is, ping-pong transmission. ) Or a TDMA / TDD system (time division multiple access / time division duplex system) is adopted.

FIG. 5 shows an example of the configuration of a digital cordless telephone that performs communication by such a communication system. As a configuration of the receiving system, the signal (π /
4 shift QPSK modulated signal) is supplied to the reception system of the transmission / reception processing circuit 10 via an antenna changeover switch (not shown), and in this reception system, it is supplied to the mixer 13 via the band pass filter 11 and the low noise amplifier 12. To do. Then, the mixer 13 mixes the frequency signals for receiving channel selection supplied from the frequency synthesizer 14,
Let it be the first intermediate frequency signal f _i1 . Then, the first intermediate frequency signal f _i1 is supplied to the mixer 16 via the bandpass filter 15, and the predetermined frequency signal supplied from the oscillator 17 is mixed to form a second intermediate frequency signal f _i2 . .

Then, the second intermediate frequency signal f _i2 is supplied to the detection circuit 19 via the limiter amplifier 18 to detect the received signal. Then, the baseband signal obtained by the detection of the detection circuit 19 is supplied to the TDMA / TDD processing circuit 30, and the reception timing is controlled in this TDMA / TDD processing circuit 30. As the control of the reception timing, a process of extracting the burst data received at the specified timing is performed. Then, the extracted reception data is supplied to the compression / expansion circuit 40 to be expanded, and the expanded reception data is supplied to the PCM codec circuit 50 to be subjected to digital audio processing into an analog audio signal. To the speaker 2 in the handset for output.

The transmission system is configured so that the sound picked up by the microphone 3 in the handset is the PCM codec circuit 5
0 to convert it to digital audio data, supply this digital audio data to the compression / expansion circuit 40 for compression, and supply the compressed audio data to the TDMA / TDD processing circuit 30 for transmission at a timing burst. Let it be data. Then, the burst data at this transmission timing is supplied to the transmission system of the transmission / reception processing circuit 10, and the binary orthogonal transformation circuit 21 performs orthogonal modulation. In the quadrature modulation at this time, the transmission data is 2-channel data, that is, I-channel and Q-channel data. And this I
The channel and Q channel data are orthogonally modulated in synchronization with the modulation wave supplied from the oscillator 22. Here, the frequency f _L of the modulated wave output from the oscillator 22 is made equal to the first intermediate frequency signal f _i1 . Further, as quadrature modulation in the quadrature modulator 22 in this case, π / 4 shift QPSK modulation is performed.

Then, the quadrature-modulated transmission data is supplied to the mixer 23, and the frequency signal for transmission channel selection output from the frequency synthesizer 14 is mixed to obtain a signal of a predetermined transmission channel. Then, the output of the mixer 23 is supplied to the antenna 1 through the bandpass filter 24, the power amplifier 25, and the antenna changeover switch (not shown) to be wirelessly transmitted.

[0007] Note that such processing of reception and transmission is
Central control unit (CP
U) 60, and control of transmission timing and reception timing is also performed by the central control unit 60. In addition, the central controller 60 is provided with a key 4 for performing various operations.
And the display panel 5 that displays the communication status such as the dial number is connected.

Here, the format of the data transmitted and received by the cordless telephone will be described. The configuration of one slot of the control data transmitted from the base station (master) side is as shown in FIG. Is composed of 240 bits, and a portion corresponding to 4 bits at the beginning is a transient response ramp time R, and the following 2 bits are a start symbol SS, which are hereinafter a preamble pattern PR (62 bits), a synchronization word UW (32 bits), Correction code CRC
Control data I (124 bits). Then, the last 16-bit equivalent part (about 41.7 μsec) is
It is used as a guard band. Here, the preamble pattern PR is a pattern in which constant data "1001" is repeated, and the 32-bit synchronization word UW following this preamble pattern PR is a specific pattern determined by the communication method.

Further, the configuration of one slot of communication data for transmitting voice data and the like when making a call is shown in FIG.
As shown in, one slot consists of 240 bits,
A portion corresponding to 4 bits at the beginning is a transient response ramp time R, the following 2 bits are a start symbol SS, and audio data including a preamble pattern PR (6 bits), a synchronization word UW (16 bits), and a correction code CRC. I (196 bits). The last 16-bit portion (about 41.7 μsec) is used as a guard band.

When the burstless data having a slot structure is received by the cordless telephone,
The detection circuit 19 detects the preamble pattern PR of each slot.
When the preamble is detected by the internal preamble detection circuit and the preamble is detected, the phase of the data detection clock is adjusted by the synchronization word UW transmitted following this preamble, and various types are transmitted subsequent to this synchronization word UW. The data I is sampled in synchronization with the phase-adjusted clock to detect high-level or low-level binary data, and the detected data is supplied to the TDMA / TDD processing circuit 30 to be received data. Perform necessary processing. Therefore, accurate detection of the preamble pattern PR is important in setting the timing for detecting the reception data transmitted in bursts.

Next, the detection circuit 1 detects the preamble PR.
FIG. 8 shows a conventional circuit configuration detected by 9. This circuit is a circuit for detecting the preamble pattern PR when receiving the control data having the slot structure shown in FIG. 6, and as described above, 32 bits of the preamble pattern PR composed of 64 bits are continuously and accurately detected. If the preamble is detected, it is determined that the preamble has been detected. The structure will be described. In the figure, 81 is a reception data input terminal and 82
Indicates a clock input terminal, and receives data received from the circuit (limiter amplifier 18) in the previous stage to the input terminal 81,
32 D flip-flops 83 ₁ to 8 connected in series
3 ₃₂ are sequentially supplied to each D flip-flop 83.
The clock obtained at the input terminal 82 is supplied to the clock input terminals of _{1 to} 83 ₃₂ , and the respective D flip-flops 83 _{1 to} 83
_{At 32} , the data supplied bit by bit is latched at the timing synchronized with this clock.

Specifically, the reception obtained at the input terminal 81
The data is transferred to the D flip-flop 83 ₁Data input end D
To the D flip-flop 83₁At the Q output end of
The obtained data is transferred to the D flip-flop 83 of the next stage.₂De
Data input terminal D, and each D flip in the following order.
The data obtained at the Q output terminal of the flop is transferred to the D flip-flop of the next stage.
It is supplied to the flip-flop data input terminal D, and 32 D
Up flop 83₁~ 83₃₂32-bit continuous data
Latch the data. Then, each D flip-flop 8
Three₁~ 83₃₂32 bits of data latched by
It is supplied to the 32-input AND gate 84. 32 pieces
Instead of configuring the force AND gate 84,
It may be configured so that it functions in the same manner in a gate circuit.

Since the preamble pattern to be detected is a pattern in which "1001" is repeated,
The AND gate 84 detects that the 4-bit pattern "1001" is repeated eight times. That is, the output of the Q output terminal is supplied to the AND gate 84 in order to detect that the first bit is at the high level “1” in the D flip-flop 83 ₃₂ at the final stage. Then, in order to detect that the next bit in the D flip-flop 83 ₃₁ before one stage is at the low level "0", the output of the inverted Q output terminal AN
Supply to the D gate 84. Similarly, the output from the Q output terminal or the inverted Q output terminal of each D flip-flop 83 is set to A
The AND gate 84 is supplied to the ND gate 84, and the AND gate 84 outputs the high level signal "1" when "1001" is repeated eight times.

Then, the logical product output of the AND gate 84 is supplied to the switching signal output terminal 85. The signal output from the switching signal output terminal 85 is supplied to a PLL circuit (phase locked loop circuit: not shown) in the detection circuit 19, and a high level signal “1” is output from this terminal 85. At this time, control is performed so as to start the phase adjustment operation of the PLL circuit. That is, when the preamble pattern is detected by the circuit of FIG. 8, the phase adjustment of the PLL circuit is performed based on the received data such as the synchronization word, and the clock synchronized with the received data is reproduced by the PLL circuit. Then, in synchronization with the clock output from this PLL circuit,
A detection process of detecting the received data bit by bit is performed, and the detected received data is supplied to a circuit in the subsequent stage.

[0015]

By the way, in the preamble pattern detecting circuit configured as described above, it is necessary to connect D flip-flops in series by the number of bit data forming the preamble pattern to be detected.
3 in the case of the above-mentioned circuit for detecting 32-bit continuity
Two D flip-flops are required, and the structure of the preamble pattern detection circuit is complicated accordingly. In addition, if the configuration of the detection circuit is complicated, the operating power of the detection circuit is correspondingly increased, and the power consumption of the circuit is increased.

In view of the above point, the present invention is to enable detection of a specific pattern such as a preamble pattern with a circuit having a simple structure in this type of radio receiver.

[0017]

According to the present invention, for example, as shown in FIG. 1, a transmission signal in which a preamble consisting of continuous data of a certain predetermined pattern is added to the data is received and included in the received signal. In a wireless receiver for detecting data to be detected in synchronization with an output of a PLL circuit that is phase-matched with a synchronization signal included in a reception signal, detection means 103 to 116 for detecting a certain predetermined pattern, and this detection A counter 118 for counting the number of consecutive detections by the means 103 to 116 is provided, and when the count value of the counter 118 reaches a predetermined value, it is determined that the preamble is detected, and the phase pull-in control of the PLL circuit is started. It is the one.

Further, in this case, as the start of the phase pull-in control of the PLL circuit, the rough phase adjustment is switched to the fine phase adjustment.

[0019]

According to the present invention, when the data to be detected is continuous data of a certain fixed pattern, it is necessary to detect only the fixed pattern itself and the number of times of continuous detection of this pattern. It is possible to significantly reduce the number of D flip-flops and the like that configure the detection circuit, as compared with a conventional circuit that requires D flip-flops corresponding to the number of detected bits, and simplify the circuit configuration. it can.

In this case, the phase pull-in control of the PLL circuit is switched from the rough phase pull-in control to the fine phase pull-in control based on the detection of the continuous data of the pattern. The pull-in control can be switched.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 4, parts corresponding to those in FIGS. 5 to 8 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this example, the TDMA /
It is applied to the receiving system of a cordless telephone that transmits and receives in the TDD system, and a detection circuit for the received data (see FIG. 5).
(Corresponding to the circuit 19 in FIG. 1) is shown in FIG.
It is configured as shown in. First, before explaining this preamble detection circuit, the configuration of the detection circuit of this example is shown in FIG. 4. In this example, the received data supplied from the circuit at the preceding stage to the input terminal 71 is detected by the preamble detection circuit 72. The preamble included in the received data is detected by this circuit 72. When the preamble detection circuit 72 detects the preamble, it outputs a switching signal.

Then, the received data obtained at the input terminal 71 is supplied to the digital PLL circuit 73, and this digital P
The LL circuit 73 reproduces a clock that is phase-synchronized with the received data. In this case, when the switching signal is supplied from the preamble detection circuit 72 to the digital PLL circuit 73, the digital PLL circuit 73 switches the phase adjustment state. The digital PL is used to switch the phase adjustment state.
The phase pull-in control of the L circuit is switched from the rough phase pull-in adjustment to the fine phase pull-in adjustment. In addition,
The digital PLL circuit 73 is a phase locked loop circuit that performs clock reproduction by digital processing.

Then, in synchronization with the clock reproduced by the digital PLL circuit 73 whose phase is controlled in this way,
The discrimination circuit 74 discriminates the received data obtained at the input terminal 71 to detect the received data, and supplies the detected data to the output terminal 75.

Next, the configuration of the preamble detection circuit 72 of the detection circuit configured as described above will be described with reference to FIG. 1. In FIG. 1, 101 is a reception data input terminal and 1 is a reception data input terminal.
Reference numeral 02 denotes a clock input terminal. Then, the input terminal 10
The received data obtained in 1 is transferred to the D flip-flop 103
Is supplied to the D input terminal of. Then, the Q output of the D flip-flop 103 is supplied to the D input terminal of the D flip-flop 104. In the following order, the D flip-flop 104
To the D input terminal of the D flip-flop 105
The Q output of the flip-flop 105 is supplied to the D input terminal of the D flip-flop 106. Then, the input terminal 102
The clock obtained at the D flip-flops 103,
It is supplied to the clock input terminals of 104, 105 and 106.

In this example, the D flip-flops 103, 104, 105, 10 connected in four stages are connected.
The output of 6 is used to detect the next four 4-bit patterns. "1001", "1100", "0110", "001"
1 "

The four 4-bit patterns differ only in their bit positions. When the pattern of "1001" is continuous, no matter which position the 4-bit is detected, any one of these patterns will be detected. To be detected. The logic circuit for detecting these four 4-bit patterns will be described below. The Q output of the D flip-flop 105 and the Q output of the D flip-flop 106 are supplied to the Ex-OR gate 107 and the D flip-flop 104 outputs. Ex-NO the Q output and the Q output of the D flip-flop 105.
The Q output of the D flip-flop 103 and the Q output of the D flip-flop 106 are supplied to the R gate 108 and Ex-
Supply to the NOR gate 109. Then, the logical output of the Ex-OR gate 107 (exclusive OR) and the logical output of the Ex-NOR gate 108 (inversion of exclusive OR) and Ex-NO
The logical output of the R gate 109 (inversion of exclusive OR) is supplied to the 3-input AND gate 110.

The Q output of the D flip-flop 103 and the Q output of the D flip-flop 106 are supplied to the Ex-OR gate 111, and the Q output of the D flip-flop 103 and the Q output of the D flip-flop 104 are supplied. Ex-NO
The Q output of the D flip-flop 105 and the Q output of the D flip-flop 106 are supplied to the R gate 112 and Ex-
It is supplied to the NOR gate 113. Then, the logical output of the Ex-OR gate 111 (exclusive OR) and the logical output of the Ex-NOR gate 112 (inversion of exclusive OR) and Ex-NO
The logical output of the R gate 113 (inversion of exclusive OR) is supplied to the 3-input AND gate 114.

The logical product output of the AND gate 110 and the logical product output of the AND gate 114 are connected to the OR gate 1
15 and supplies the OR output of the OR gate 115 to D
It is supplied to the flip-flop 116. According to the logic circuit configured as described above, any of the above-mentioned four 4-bit patterns has four stages of D flip-flops 103 to 106.
, The high level signal “1” is output from the OR gate 115. Also, the four four mentioned above
When none of the bit patterns is detected, the OR gate 115 outputs the low level signal “0”.

In the D flip-flop 116 to which the OR output of the OR gate 115 is supplied, the clock obtained at the input terminal 102 is the inverter gate 117.
It is inverted by and then supplied to the clock input terminal. Then, the Q output latched by the D flip-flop 116 is supplied to the reset terminal of the counter 118. The counter 118 counts this clock while the obtained clock is supplied to the input terminal 102 and the high level signal “1” is continuously supplied to the reset terminal.

When the count value of the counter 118 reaches a predetermined value set in advance, a pulse of high level is output. This output pulse is supplied to the output terminal 119 as a switching signal. In this example, the initial value of the counter 118 is set to [230], and by supplying the high level signal “1” to the reset terminal, the clock is counted and the count value is incremented by 1, and the count value is [ Two
58], a switching signal is output.

Then, the switching signal obtained at the output terminal 119 is supplied to the digital PLL circuit 73 shown in FIG. 4 to switch the phase pull-in state. That is, by supplying this switching signal, the phase pull-in control of the digital PLL circuit is switched from the rough phase pull-in adjustment to the fine phase pull-in adjustment. The rough phase pull-in adjustment here is control of a loop that makes the frequency of the clock output from the digital PLL circuit substantially match the frequency of the clock component of the received data, and the fine phase pull-in adjustment is the fine phase pull-in adjustment. This is a loop control that causes the phase of the clock output by the circuit to almost completely match the phase of the clock component of the received data.

The other parts are constructed similarly to the conventional cordless telephone shown in FIG.

Next, the operation of the cordless telephone configured as described above will be described focusing on the preamble detection circuit. The preamble detection circuit shown in FIG. 1 has a preamble pattern PR (see FIG. 6) included in a control slot. ) Is formed by repeating a 4-bit pattern “1001”, this 4-bit pattern is 8
When repeated, the circuit determines that the preamble is detected, and the detection operation is performed at the timing shown in FIG.

That is, first, it is assumed that the input terminal 102 is supplied with the clock shown in FIG. 2A and the received data supplied to the input terminal 101 is the waveform data shown in FIG. 2B. At this time, the D flip-flops 103 to 106 connected in four stages latch the received data at the timing when the clock rises. Then, from the latch outputs of the four-stage D flip-flops 103 to 106, the following four 4-bit patterns “1001”, “1100”,
Either "0110" or "0011" is the logic gate 1
07-115, the output of the D flip-flop 116 (C in FIG. 2) goes high,
The counter 118 displays the count value [23
0].

In the example of FIG. 2, the preamble pattern PR starts at the timing t ₀ (however, the first 2 bits are actually the start symbol SS), and the 4-bit pattern “0110” is the timing at which 4 bits have elapsed from the timing t _0. It is detected at t ₁ , and at this time, the count value of the counter 118 is counted up from [230]. Then, when the preamble pattern PR is correctly received, timings t ₂ and t at which 4 bits elapse thereafter
_3, it is detected the same pattern "0110" repetition in ‥‥, although to determining that the preamble has been detected in eight detected timing t _8, in state where the continuous and be accurately detected , "1001", "110"
Any of the 0 "," 0110 ", and" 0011 "patterns is sequentially detected, the output of the D flip-flop 116 continues to be at the high level, and the counter 118 continues to count up.

Then, the timing t detected eight times
₈(This timing t₈Is timing t ₀From 32 bits
When the point has passed), it is shown in Fig. 2D.
As described above, the count value of the counter 118 becomes [258].
It At this time, as shown in E of FIG.
The switching signal that changes to high level is output, and this switching signal
Fine phase pull-in operation of the digital PLL circuit 73 by
The work is started.

Then, a fine phase pull-in operation is performed in the digital PLL circuit 73, so that the digital P
The LL circuit 73 outputs a clock that is accurately synchronized with the received data, and the received data is detected in synchronization with this clock. Therefore, the preamble pattern P
Data I transmitted after R or the synchronization word UW (see FIG. 6).
Of the data processing circuit (T)
Accurate reception data is supplied to the DMA / TDD processing circuit 30 and the like, and accurate reception processing of transmission data having a slot configuration is possible.

Here, the preamble pattern can be detected.
An example of the case where it is not possible is shown in FIG.
At timing t₀The preamble section starts from
Imming t₁The counter 118 starts counting up
Suppose At this time, the pattern "0110" is repeated three times.
Immediately after that, there is some reception error in section e.
The four 4-bit patterns mentioned above are no longer detected
To do. At this time, the output of the D flip-flop 116 is
Change from high level to low level as shown in C of 3
Then, as shown in D of FIG. 3, the count value of the counter 118
Returns to the initial value [230], and the switching signal is sent from the counter 118.
Issue is not output. However, the next
Timing t is supplied₀From ’
Since it becomes an amble pattern, this timing t₀′
4 bits after the timing t ₁‘Recount from
Start up, and the 4-bit pattern is repeated 8 times.
For example, the switching signal is output from the counter 118.

As described above, when the preamble detection circuit of this example is used, it is found that the preamble pattern can be accurately received in 32 bits, and the reception processing of the digital cordless telephone can be performed accurately with the preamble pattern of each slot as a reference. become. The amble detection circuit configured as in this example has four stages of D connected in series.
The flip-flops 103 to 106 and the logic gate 10 that determines the outputs of the D flip-flops 103 to 106
7 to 115 and a counter 118 that counts based on the outputs of the logic gates 107 to 115 as main components, and 32 D flip-flops are connected in series when 32 bits of continuity are detected as in the conventional case. The preamble detection circuit can be easily configured without the need for a complicated circuit for connection. Further, since the circuit configuration is simplified, the power consumption of the circuit can be suppressed to that extent.

Although the case of receiving the slot containing the control data has been described here, the same control can be performed on the slot for receiving other data based on the detection of the preamble. However, since the number of bits of the preamble is different, it is necessary to change the control of the number of detections.

Further, although the preamble detection signal is used for switching the phase pull-in operation of the PLL circuit in the above-mentioned embodiment, it may be used for other control.

Further, in the above-mentioned embodiment, the present invention is applied to the detection circuit of the preamble pattern, but it is also applicable to the detection circuit of other data in which the specific pattern of several bits is continuously formed.

Further, in the above-mentioned embodiment, the invention is applied to the receiving system of the cordless telephone for digital communication, but it is also applicable to the wireless telephone constituted by other system.
Of course, it can be applied to a specific pattern detection circuit of a data processing device other than the telephone.

[0045]

According to the present invention, when the data to be detected is continuous data of a certain fixed pattern, only the detection of the fixed pattern itself and the number of consecutive detections of this pattern are detected. The number of D flip-flops and the like forming the detection circuit can be significantly reduced as compared with the conventional circuit that requires D flip-flops corresponding to the number of bits to be detected. Can be simplified.

In this case, the phase pull-in control of the PLL circuit is switched from the rough phase pull-in adjustment to the fine phase pull-in adjustment based on the detection of the continuous data of the pattern. The pull-in control can be favorably switched.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a preamble detection circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing a preamble detection state (when a preamble is detected) according to an embodiment.

FIG. 3 is a timing diagram showing a preamble detection state (when a preamble is not detected) according to an embodiment.

FIG. 4 is a configuration diagram of a detection circuit according to an embodiment.

FIG. 5 is a system configuration diagram of a cordless telephone.

FIG. 6 is an explanatory diagram showing an example of a configuration of wirelessly transmitted control data.

FIG. 7 is an explanatory diagram showing an example of a data structure for communication wirelessly transmitted.

FIG. 8 is a configuration diagram of a conventional preamble detection circuit.

[Explanation of symbols]

72 Preamble Detection Circuit 73 Digital PLL Circuit (Digital Phase Locked Loop Circuit) 74 Discrimination Circuit 103-106, 116 D Flip-Flop 107-115 Logic Gate 118 Counter

Claims (2)

[Claims] 1. A transmission signal in which a preamble consisting of continuous data of a certain predetermined pattern is added to the data is received, and the detection of the data included in the reception signal is phased with the synchronization signal included in the reception signal. In a wireless receiver which performs the output in synchronization with the output of the PLL circuit, a detection means for detecting the certain predetermined pattern and a counter for counting the number of continuous detection times by the detection means are provided. A radio receiver configured to start the phase pull-in control of the PLL circuit when the preamble is detected when the count value of the counter reaches a predetermined value. 2. The radio receiver according to claim 1, wherein the phase pull-in control of the PLL circuit is started by switching from rough phase adjustment to fine phase adjustment.