JPH07122664A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE:To provide a high performance Bi-CMOS semiconductor device by differentiating the impurity concentration in the vicinity of base-collector junction between a bipolar transistor requiring high speed operation and a bipolar transistor requiring high amplitude operation. CONSTITUTION:The semiconductor device 10 comprises at least two types of bipolar transistors and an insulated gate FET transistor formed on one semiconductor substrate 12. N type impurity ions are implanted in the vicinity of base- collector junction of a region 24 for forming a transistor requiring a narrow base width. N type impurity ions are also implanted into a well in a region 22 for forming a P channel insulated gate FET transistor. The ion implantations are effected in one step.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to at least two types of bipolar transistors and insulated gate field effect transistors (MO).
SFET) formed on the same semiconductor substrate, so-called Bi-
The present invention relates to a CMOS semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, due to the features of high integration and low power consumption, C-MOS (Complementary Metal-Oxide Semico)
LSI is the mainstream of LSI devices. On the other hand, bipolar LSIs are often used in analog circuits and the like because of their characteristics such as high speed and high gain. Furthermore, recently, a Bi-CM with a shape that combines the features of both
An LSI having an OS structure has been proposed. Bi-CMOS
Is a combination of a bipolar transistor having a high current drive capability and a highly integrated and low power consumption CMOS. Particularly, in a memory for storage, a memory cell that occupies most of the circuit is formed by MOS, and high speed is required. Bi-CMOS gates are used for the peripheral circuits used to realize an ultra-high speed and highly integrated memory.

[0003]

However, in the past, about 5V was mainly used as a power source for these semiconductor devices, but recently, about 3.3V tends to be used. Bi-CM due to voltage drop, etc.
The superiority of OS over C-MOS is decreasing. In this case, regarding the MOS transistor,
Although lowering the speed can be suppressed by lowering the threshold voltage, since the V _BE (base-emitter voltage) of the bipolar transistor is constant, the ratio of V _BE itself to the power supply voltage increases, and it remains unchanged. Then, the decrease in speed is inevitable.

In view of the above problems, the object of the present invention is Bi
-A high performance Bi-CMOS semiconductor device by changing the impurity concentration in the vicinity of the base-collector junction of a bipolar transistor that needs to operate at a high speed and a bipolar transistor that needs to operate at a large amplitude among the bipolar transistors of CMOS LSI To provide.

[0005]

In order to achieve the above object, a semiconductor device according to the present invention comprises a plurality of bipolar transistors having different base widths and an insulated gate field effect transistor on the same semiconductor substrate. Of the transistors, the one with the narrow base width
The impurity concentration in the region near the base-collector junction is
The feature is that it is higher than that of a transistor with a wide base.

In order to increase the impurity concentration, for example, N-type impurities are introduced in the vicinity of the base-collector junction by the ion implantation method. Here, a bipolar transistor having a different base width is a bipolar transistor in which the base width is intentionally made different. For example, since a large amplitude operation is required, the base width is widened and the collector and the base are different. The two types of transistors are one that requires a high withstand voltage between the two and one that requires a narrow base width because high-speed operation is required.

According to another aspect of the semiconductor device of the present invention, the impurity concentration in the region near the base-collector junction of a transistor having a narrow base width becomes higher than that of a transistor having a wide base width due to the introduction of N-type impurities. Among the insulated gate field effect transistors, the P-channel transistor is characterized in that an N-type impurity is introduced into the well.

Furthermore, the present invention provides a method of manufacturing a semiconductor device, wherein a bipolar transistor having a different base width and an insulated gate field effect transistor are formed on the same semiconductor substrate. The step of introducing the N-type impurity into the region near the base-collector junction to narrow the base width and the step of introducing the N-type impurity into the well of the P-channel transistor of the insulated gate field effect transistor are performed by the same step. It is characterized by being performed.

[0009]

Since it is constructed as described above, as shown in the graph of FIG. 3, for example, the base of a bipolar transistor in which an N-type impurity (corresponding to N ₂ ) is introduced by ion implantation into a region near the base-collector junction. The width W ₂ is narrower than the base width W _{1 of the} non-ion-implanted one (equivalent to N ₁ ). Note that FIG. 3 is a graph in which the ordinate represents the impurity concentration and the abscissa represents the depth (width of the base, etc.), and shows that the width of the base is reduced by increasing the concentration of the impurity. This is because when the impurity concentration in the region near the base-collector junction is increased from N ₁ to N ₂ , the base width becomes W _1.
Is reduced to W ₂ and at the same time, the collector resistance is also reduced. Further, assuming that the power supply voltage is 3.3V, a bipolar transistor performing a large amplitude operation needs a withstand voltage characteristic of 3.3V between the collector and the emitter and between the base and the emitter. On the other hand, the withstand voltage of the bipolar transistor that operates at high speed is equal to or lower than the power supply voltage (often 2V or less, although it depends on the circuit).
Good.

That is, since there is a trade-off between the withstand voltage and the high-speed performance, the base width of the bipolar transistor that needs to operate at high speed is narrowed by such a structure to lower the withstand voltage, and a bipolar transistor with higher speed performance is obtained. can do. As described above, desired high-speed performance can be achieved for a specific transistor by merely increasing the impurity concentration in the vicinity of the base-collector junction without changing the base and emitter structures of the bipolar transistor.

In addition, a step of introducing an N-type impurity into the vicinity of the base-collector junction of a transistor required to have a narrow base width by ion implantation, and a well of a P-channel transistor of the insulated gate field effect transistor (MOSFET). Since the step of introducing the N-type impurity into the substrate by ion implantation is performed in the same step, it is possible to add a new step to the semiconductor manufacturing step without adding a new step.
By narrowing the base width, high speed performance can be given to a specific transistor, and MOS punch through can be suppressed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 (a)-(c) and 2 (d)-(e)
Shows an example of a manufacturing process of the semiconductor device 10 according to the present invention, which will be described in order.

(A): First, a P-type silicon substrate 12 is prepared, its surface is oxidized, and then an oxide film is selectively removed by a photolithography technique to obtain antimony (Sb).
N ⁺ buried layer 1 by deposit diffusion
4 is formed. The n ⁺ buried layer 14 becomes a part of the collector of the bipolar transistor. Next, the remaining oxide film is removed, silicon (Si) is epitaxially grown on the entire surface, and the resistivity of 1 to 1.3 μm is obtained.
An n-type Si layer 16 of 2 Ω · cm is formed.

(B): Subsequently, the n-type Si layer 16 excluding the element formation region is formed by a well-known selective oxidation technique using a silicon nitride (Si ₃ N ₄ ) film as a selective oxidation mask.
A thick field oxide film 18 of 400 nm is formed on the surface of. After that, the selective oxidation mask is removed to expose the n-type Si layer 16 in the element formation region. Next, a thermal oxide film 20 is formed on the surface, and then the thermal oxide film 20 in the p-type (channel) MOS transistor formation region 22 and the bipolar transistor formation region 24 that requires high-speed operation is removed by photolithography. Then, phosphorus (P), which is an N-type impurity, is ion-implanted into the portion in the same step. As a result, as shown in the graph of FIG. 3, for example, the base width W ₂ of a bipolar transistor in which an N-type impurity (corresponding to N ₂ ) is introduced into the region near the base-collector junction by the ion implantation method is not ion-implanted (N ₁
It can be made narrower than the base width W ₁ of (corresponding).

Similarly, boron (B) which is a P-type impurity is ion-implanted into the n-type (channel) MOS formation region 26. Then, thermal diffusion is performed at 1000 ° C. for 30 minutes. Reference numeral 28 denotes a bipolar transistor formation region which requires a large amplitude operation, and the impurity concentration near the base-collector junction has an n-type Si layer 1 formed by epitaxial growth.
Equal to 6.

(C): Next, after removing the thermal oxide film 20, a thin gate oxide film 30 of 15 nm is formed on the exposed surface by thermal oxidation again, and the MOS transistor formation region 2 is formed.
Boron ion implantation for threshold value adjustment is selectively performed on the layers 2 and 26 by the photolithography technique. Then
A 620 polysilicon film 32 is formed on that portion by the CDV method.
Deposit 100 nm at ° C. Further, phosphorus (P) is contained in the polysilicon film 32 by a well-known technique using a POCl ₃ source.
Dope. After removing the phosphorus glass formed on the surface, WS is deposited on the entire surface of the polysilicon film 32 by the CVD method.
The i film 34 is deposited to 100 nm. Then selectively W
The Si film 34 and the polysilicon film 32 are anisotropically etched to form the gate electrode 36 of the MOS transistor.

Next, 5 × 1 is formed in the n-type MOS formation region 26.
Arsenic (As) of 0 ¹⁵ / cm ² is ion-implanted at 50 keV to form the N ⁺ high-concentration diffusion layer 38, and p-type M
The base region of the OS transistor forming region 22 and the bipolar transistor, a BF ₂ of 3 × 10 ¹⁵ / cm ² by ion implantation to form a P ⁺ high concentration diffusion layer 40. next,
Phosphorus (P) of 5 × 10 ¹⁵ / cm ² is ion-implanted at 500 keV into the collector extraction portions of the two types of bipolar transistors to form the collector extraction layer 42. Then 2
B in the base forming portion 44 of the bipolar transistor of the kind
F ₂ was ion-implanted at 70 keV and 3 × 10 ¹³ / cm ² 9
Heat treatment is performed at 00 ° C. for 20 minutes.

(D): Next, an oxide film 46 of about 100 nm is deposited on the entire surface by the CVD method, the emitter contact hole is patterned by the photolithography technique, and the emitter contact hole 48 is formed by anisotropic etching. Next, 62 polysilicon is applied to the entire surface.
Deposit 150 nm at 0 ° C., and arsenic (As) 70 keV
1 × 10 ¹⁶ / cm ² ions are implanted. Further, the polysilicon emitter 50 is formed by using photolithography and dry etching.

(E): Next, an oxide film 52 is deposited to a thickness of 150 nm on the entire surface by the CVD method, and BP is deposited thereon.
SG (Boro-Phospho-Silicateglass) film 54 at 430 ° C.
At 400 ° C. and then reflowed at 900 ° C. for planarization. At this time, arsenic (As) is simultaneously diffused from the polysilicon emitter 50 to the Si surface to form an emitter. Next, the contact hole 56 is formed by the photolithography technique and the anisotropic etching technique of the oxide film.
Next, titanium (Ti) layer 58, titanium nitride (TiN)
The layer 60 and the Al-Cu-Si alloy layer 62 are respectively 3
Sputter deposition is performed at 0, 70, and 800 nm, a desired wiring pattern 64 is formed by using a photolithography technique and an Al dry etching technique, and annealing is performed at 400 ° C. in a forming gas. Next, plasma C
After the nitride film 66 is deposited on the entire surface by the VD method, a hole for a bonding pad is opened by using the photolithography technique and dry etching to complete the semiconductor device.

As described above, in this semiconductor device, the impurity concentration in the vicinity of the base-collector junction of the bipolar transistor which is required to operate at high speed among the bipolar transistors is increased, so that the base width is narrowed and the power supply voltage used is reduced. It operates at high speed even if it drops, and has better performance than a memory composed of only C-MOS.

In the manufacturing process, phosphorus (P) is ion-implanted into the p-type MOS transistor formation region 22 and the bipolar transistor formation region 24 that needs to operate at high speed in the same process. Without doing so, the base width can be narrowed to increase the speed of the transistor, and MOS punch through can be suppressed.

[0022]

As described above, according to the invention of claim 1, among the bipolar transistors, among the bipolar transistors, the transistor having a narrow base width is
The impurity concentration in the region near the base-collector junction is
By making the width higher than that of a transistor having a wide base, it is possible to easily make a bipolar transistor operating at a high speed and a bipolar transistor operating at a large amplitude separately, and a Bi transistor having two types of bipolar transistors coexisting. -A CMOS can be realized. In other words, by changing the collector concentration, it is possible to realize a semiconductor device in which a large-amplitude bipolar transistor having a high breakdown voltage and a bipolar transistor for high-speed operation are separately manufactured.

According to the second aspect of the present invention, the collector concentration of the bipolar transistor having a high breakdown voltage is set to the n-type epitaxial substrate concentration, and the collector concentration of the high performance bipolar transistor is set to the n-type epitaxial substrate concentration + N.
Bi-CM if set by well implantation
It is possible to realize a high-performance and high-performance Bi-CMOS semiconductor device in which two types of transistors are separately formed without adding an OS process.

According to the invention of claim 3, the step of introducing N-type impurities into the p-channel transistor forming region of the insulated gate field effect transistor by ion implantation, and the base-collector of the bipolar transistor requiring high speed operation. Since the step of introducing the N-type impurity into both the vicinity of the junction by ion implantation is performed in the same step, the method for manufacturing a semiconductor device according to the present invention narrows the base width without adding the number of steps. Thus, it is possible to provide a semiconductor device capable of increasing the speed of a transistor and suppressing punch-through of a p-channel transistor.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing the manufacturing process of the semiconductor device according to the present invention subsequent to FIG. 1;

FIG. 3 is a diagram for explaining a relationship between an impurity concentration and a base width.

[Explanation of symbols]

10 semiconductor device 12 semiconductor substrate 14 n ⁺ buried layer 16 n-type Si layer 18 oxide film 20 thermal oxide film 22 p-type MOS transistor formation region 24 bipolar transistor formation region 26 for high-speed operation n-type MOS transistor formation region 28 large amplitude Operational bipolar transistor formation region 30 Gate oxide film 32 Polysilicon film 34 WSi film 36 Gate electrode 38 N ⁺ High concentration diffusion layer 40 P ⁺ High concentration diffusion layer 42 Collector extraction layer 44 Base formation portion 46 Oxide film 48 Emitter contact hole 50 Polysilicon emitter 52 Oxide film 54 BPSG film 56 Contact hole 58 Titanium film 60 Titanium nitride film 62 Al-Cu-Si alloy layer 64 Wiring pattern 66 Nitride film

Claims (3)

[Claims] 1. A plurality of bipolar transistors having different base widths and an insulated gate field effect transistor are provided on the same semiconductor substrate. Among the bipolar transistors, a transistor having a narrow base width has an impurity concentration in a region near a base-collector junction. Is higher than that of a transistor having a wide base, a semiconductor device. 2. The impurity concentration of a region near the base-collector junction of the transistor having a narrow base width is higher than that of a transistor having a wide base width due to the introduction of N-type impurities, and the insulated gate field effect transistor includes: 2. The semiconductor device according to claim 1, wherein the P-channel transistor has an N-type impurity introduced into the well. 3. A method of manufacturing a semiconductor device, wherein a bipolar transistor having a different base width and an insulated gate field effect transistor are formed on the same semiconductor substrate, wherein the bipolar transistor is near the base-collector junction of the transistor. The step of introducing the N-type impurity into the region to narrow the base width and the step of introducing the N-type impurity into the well of the P-channel transistor of the insulated gate field effect transistor are performed in the same step. And a method for manufacturing a semiconductor device.