JPH07121467B2 - Method for soldering Si semiconductor element to Cu-based alloy lead frame with little residual thermal strain - Google Patents
Method for soldering Si semiconductor element to Cu-based alloy lead frame with little residual thermal strainInfo
- Publication number
- JPH07121467B2 JPH07121467B2 JP61038525A JP3852586A JPH07121467B2 JP H07121467 B2 JPH07121467 B2 JP H07121467B2 JP 61038525 A JP61038525 A JP 61038525A JP 3852586 A JP3852586 A JP 3852586A JP H07121467 B2 JPH07121467 B2 JP H07121467B2
- Authority
- JP
- Japan
- Prior art keywords
- based alloy
- semiconductor element
- lead frame
- soldering
- thermal strain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Landscapes
- Die Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置の組立て（アッセンブリー）に
おいて、Si半導体素子をCu基合金製リードフレームに少
ない残留熱歪ではんだ付けする方法に関するものであ
る。The present invention relates to a method for soldering a Si semiconductor element to a Cu-based alloy lead frame with a small residual thermal strain in the assembly (assembly) of a semiconductor device. is there.
従来、一般に、半導体装置として、トランジスタやIC、
さらにLSIなどが知られているが、この中で、例えばIC
は、 （ａ） まず、リードフレーム素材として板厚:0.1〜0.
3mmを有するCu基合金条材を用意し、 （ｂ） 上記リードフレーム素材よりプレス打抜き加工
により製造せんとするICの形状に適合したリードフレー
ムを形成し、 （ｃ） ついで、上記Cu基合金製リードフレームの所定
個所に高純度のSi半導体素子を、必要に応じて金属Moな
どの薄板をはさみ込んだ状態で、Agペーストなどの導電
性樹脂を用いて加熱接着するか、あるいは上記Si半導体
素子をAu−Si合金ろう材などを介して上記リードフレー
ムの片面にろう付けし、 （ｄ） 上記Si半導体素子と上記Cu基合金製リードフレ
ームとに渡ってAu極細線などによるワイヤボンディング
を施し、 （ｅ） 引続いて、上記Si半導体素子、結線、およびSi
半導体素子が取付けられた部分のCu基合金製リードフレ
ームを、これらを保護する目的で、プラスチックで封止
し、 （ｆ） 最終的に、上記Cu基合金製リードフレームにお
ける相互に連なる部分を切除してICを形成する、 以上（ａ）〜（ｆ）の主要工程によって製造されてい
る。Conventionally, generally, as a semiconductor device, a transistor, an IC,
Further, LSI and the like are known. Among them, for example, IC
(A) First, the thickness of the lead frame material is 0.1 to 0.
Prepare a Cu-based alloy strip having 3 mm, and (b) form a lead frame conforming to the shape of the IC to be manufactured by press punching from the above lead frame material, and (c) then make the Cu-based alloy A high-purity Si semiconductor element at a predetermined place of the lead frame, with a thin plate of metal Mo or the like sandwiched as necessary, by heat bonding using a conductive resin such as Ag paste, or the above Si semiconductor element Is brazed to one surface of the lead frame via an Au-Si alloy brazing material or the like, and (d) is wire-bonded with an Au ultrafine wire or the like across the Si semiconductor element and the Cu-based alloy lead frame, (E) Subsequently, the above-mentioned Si semiconductor element, connection, and Si
The Cu-based alloy lead frame of the portion to which the semiconductor element is attached is sealed with plastic for the purpose of protecting them. (F) Finally, the mutually continuous portions of the Cu-based alloy lead frame are cut off. It is manufactured by the main steps of (a) to (f).
このように半導体装置の製造に際し、Si半導体素子のCu
基合金製リードフレームへの接合に、AgペーストやAu−
Si合金ろう材が結合材として使用されているが、これら
の結合材は、主要成分がAuやAgで構成されているために
高価にならざるを得ず、一方半導体装置の低コスト化に
対する要求は、近年増々厳しくなるのが現状であり、前
記結合材においても、より安価な材料の開発が強く望ま
れている。In this way, when manufacturing semiconductor devices, Cu of Si semiconductor element
For joining to a lead alloy made of base alloy, Ag paste or Au-
Although Si alloy brazing filler metals are used as binders, these binders are inevitably expensive because their main components are Au and Ag, while there is a demand for lower cost semiconductor devices. In recent years, it is becoming more and more severe, and it is strongly desired to develop a cheaper material for the above-mentioned binder.
かかることから、半導体装置の組立てに、高価なAgペー
ストやAu−Si合金ろう材に代って、安価な従来良く知ら
れているSn基合金はんだ材や、Pb基合金はんだ材を用い
る試みもなされたが、これらのはんだ材を用いた場合、
Si半導体素子とCu基合金製リードフレームとの間に存在
する大きな熱膨脹差によって、特に接合後のSi半導体素
子には大きな熱歪が残留するようになり、この結果Si半
導体素子に著しい反りが生じ、これが割れに発展する場
合がしばしば発生し、この傾向は、最近の64KDRAMや256
KDRAMなどの超LSIなどの大型の半導体装置において顕著
に現われるものであり、信頼性に問題があることから、
実用に供することができないものである。Therefore, in the assembly of the semiconductor device, in place of the expensive Ag paste or Au-Si alloy brazing material, an inexpensive well-known Sn-based alloy solder material or an attempt to use a Pb-based alloy solder material is also available. However, when using these solder materials,
Due to the large thermal expansion difference existing between the Si semiconductor element and the lead frame made of Cu-based alloy, a large thermal strain is left in the Si semiconductor element after joining, resulting in a significant warp in the Si semiconductor element. , This often develops into cracks, this trend has been seen in recent 64KDRAM and 256
Since it appears remarkably in large semiconductor devices such as VLSI such as KDRAM, and there is a problem in reliability,
It cannot be put to practical use.
そこで、本発明者等は、上述のような観点から、上記の
安価な従来Sn基合金およびPb基合金はんだ材に着目し、
これらはんだ材に生ずる残留熱歪の低減化をはかるべく
研究を行なった結果、従来はんだ材として知られている
Sn基合金またはPb基合金からなる素地中に、0.1〜５μ
ｍの平均粒径を有し、かつ熱膨脹係の小さい、望ましく
は熱膨脹係数が10-5/K以下のMo,W,Nb、およびTiの炭化
物（以下、それぞれMo2C,WC,NbC、およびTiCで示す）の
うちの１種以上からなる炭化物粒子を、前記炭化物粒子
に対する割合で１〜10重量％のSnまたはAgからなる炭化
物粒子めっき被覆層を介して、５〜50容量％の割合で分
散含有してなるはんだ材を用いると、このはんだ材は、
すぐれたはんだ付け性を保持すると共に、はんだ付け時
におけるSi半導体素子とCu基合金製リードフレームの大
きな熱膨脹差を十分に吸収する高いクリープ変形能を有
することから、はんだ付け後のSi半導体素子における残
留熱歪は著しく少なくなって、半導体装置の作動中に発
生する熱付加が起る繰り返しの膨脹と収縮によっても、
Si半導体素子に発生する反りや割れが著しく抑制される
ようになるという研究結果を得たのである。Therefore, the present inventors, from the above viewpoint, pay attention to the above-mentioned inexpensive conventional Sn-based alloy and Pb-based alloy solder material,
As a result of conducting research to reduce the residual thermal strain generated in these solder materials, it has been known as a conventional solder material
0.1 to 5μ in the base made of Sn-based alloy or Pb-based alloy
Carbides of Mo, W, Nb and Ti having an average particle size of m and a small coefficient of thermal expansion, preferably having a coefficient of thermal expansion of 10 -5 / K or less (hereinafter Mo 2 C, WC, NbC, and (Indicated by TiC), at least 5 to 50% by volume of carbide particles consisting of one or more of the above, through a carbide particle plating coating layer made of Sn or Ag in an amount of 1 to 10% by weight relative to the carbide particles. If you use a solder material that contains dispersed, this solder material,
While maintaining excellent solderability, it has high creep deformability that sufficiently absorbs the large thermal expansion difference between the Si semiconductor element and the lead frame made of Cu-based alloy during soldering, so in the Si semiconductor element after soldering. The residual thermal strain is significantly reduced, and due to repeated expansion and contraction caused by heat addition generated during the operation of the semiconductor device,
We obtained the research results that the warpage and cracks that occur in Si semiconductor devices are significantly suppressed.
この発明は、上記の研究結果にもとづいてなされたもの
であって、Si半導体素子をCu基合金製リードフレームに
はんだ付けするに際して、はんだ材として、従来はんだ
材と同じSn基合金またはPb基合金からなる素地中に、0.
1〜５μｍの平均粒径を有する熱膨脹係数の小さいMo2C,
WC,NbC、およびTiCのうちの１種以上からなる炭化物粒
子が、前記炭化物粒子に対する割合で１〜10重量％のSn
またはAgからなる炭化物粒子めっき被覆層を介して５〜
50容量％の割合で分散含有してなるはんだ材を用いるこ
とにより、Si半導体素子をCu基合金製リードフレームに
少ない残留熱歪ではんだ付けする方法に特徴を有するも
のである。This invention has been made based on the above research results, when soldering a Si semiconductor element to a Cu-based alloy lead frame, as a solder material, the same Sn-based alloy or Pb-based alloy as the conventional solder material In the base consisting of 0.
Mo 2 C having an average particle size of 1 to 5 μm and a small coefficient of thermal expansion,
Carbide particles composed of at least one of WC, NbC, and TiC are contained in an amount of 1 to 10% by weight of Sn with respect to the carbide particles.
Or 5 through a carbide particle plating coating layer made of Ag
It is characterized by a method of soldering a Si semiconductor element to a Cu-based alloy lead frame with a small residual thermal strain by using a solder material dispersedly contained at a ratio of 50% by volume.
なお、この発明の方法において、はんだ材を構成する炭
化物粒子の平均粒径を0.1〜５μｍと限定したのは、原
料として用いられる粉末の平均粒径が0.1μｍ未満の粉
末を製造することは、現時点ではきわめて困難であり、
またその平均粒径が５μｍを越えると、はんだ付け界面
ではんだ付け性を損なうように作用するようになるとい
う理由にもとづくものであり、またその分散割合を５〜
50容量％と限定したのは、その割合が５容量％未満では
所望の残留熱歪低減効果が得られず、一方その割合が50
容量％を越えると、はんだ付け性が低下するようになる
という理由にもとづくものである。In the method of the present invention, the average particle size of the carbide particles constituting the solder material is limited to 0.1 to 5 μm because the average particle size of the powder used as a raw material is less than 0.1 μm. It ’s extremely difficult at the moment,
This is also based on the reason that when the average particle size exceeds 5 μm, the soldering interface acts to impair the solderability, and the dispersion ratio is 5 to 5.
The limit of 50% by volume is that if the ratio is less than 5% by volume, the desired residual thermal strain reduction effect cannot be obtained, while the ratio is 50% by volume.
It is based on the reason that when the capacity% is exceeded, the solderability is deteriorated.
さらに、炭化物粒子となる原料粉末のSn基合金またはPb
基合金からなる素地に対するぬれ性を向上させる目的
で、前記原料粉末の表面に、前記原料粉末に対する割合
で１〜10重量％のSnまたはAgでめっき被覆層を形成する
が、この場合、その割合が１重量％未満では所望のぬれ
性が得られず、一方その割合が10重量％を越えてもぬれ
性により一層の向上効果が得られないという理由でめっ
き被覆層の割合を前記の通りに定めたのである。In addition, the Sn-based alloy or Pb of the raw material powder that becomes the carbide particles
For the purpose of improving the wettability to the base made of a base alloy, on the surface of the raw material powder, a plating coating layer is formed with 1 to 10% by weight of Sn or Ag relative to the raw material powder, in this case, the proportion Is less than 1% by weight, the desired wettability cannot be obtained. On the other hand, even if the ratio exceeds 10% by weight, the wettability cannot be further improved, so that the proportion of the plating coating layer is as described above. I have set it.
つぎに、この発明の方法を実施例により具体的に説明す
る。Next, the method of the present invention will be specifically described by way of Examples.
それぞれ第1,2表に示される平均粒径をもった各種炭化
物の原料粉末の表面に、ぬれ性を向上させる目的で同じ
く第1,2表に示される材質および割合のめっき被覆層を
無電解めっき法にて形成して、はんだ材において炭化物
粒子となる表面被覆原料粉末を調製し、この表面被覆原
料粉末を、従来はんだ材として知られているSn−25％Ag
−10％Sbの組成をもったSn基合金またはPb−５％Snの組
成（以上重量％）をもったPb基合金のはんだ素材と共
に、所定の配合割合のもとにるつぼ内に封入し、アルゴ
ン雰囲気中で高周波加熱により溶解し、撹拌を行ないな
がら、前記るつぼの下部に設けたノズルを通して、同じ
くアルゴン雰囲気中で、その下方に配置した１個の回転
する鋼ロールの表面に吹付けることによって、同じく第
1,2表に示される平均粒径および割合の炭化物粒子が均
一に分散含有し、かつ幅:3mm×厚さ:50μｍの寸法をも
ったリボン状はんだ材を製造し、ついでこれらはんだ材
を用い、平面:5mm×6mm、厚さ:0.3mmの寸法をもった半
導体素子としてのSiチップを、AgめっきされたCu合金
（CDA194）製リードフレームにはんだ付けすることによ
り本発明法１〜12をそれぞれ実施した。Electroless plating coating layers of the same materials and proportions shown in Tables 1 and 2 were also formed on the surface of the raw material powders of various carbides having the average particle diameters shown in Tables 1 and 2 to improve the wettability. Formed by a plating method to prepare a surface coating raw material powder that becomes carbide particles in a solder material, and the surface coating raw material powder is Sn-25% Ag which is conventionally known as a solder material.
With Sn-based alloy having a composition of -10% Sb or Pb-based alloy having a composition of Pb-5% Sn (above wt%), it is enclosed in a crucible at a predetermined mixing ratio, It is melted by high frequency heating in an argon atmosphere, and is sprayed on the surface of one rotating steel roll arranged thereunder through a nozzle provided in the lower part of the crucible while being stirred. , Likewise
Ribbon-shaped solder materials having the average particle size and ratio shown in Tables 1 and 2 uniformly dispersed and contained, and having the dimensions of width: 3 mm × thickness: 50 μm were manufactured. , Plane: 5 mm × 6 mm, thickness: 0.3 mm as a semiconductor element having a Si chip as a semiconductor element, the method 1 to 12 of the present invention by soldering the lead frame made of Cu alloy (CDA194) plated with Ag Each was carried out.
また、比較の目的で、上記の表面被覆原料粉末の配合を
行なわず、上記組成と同じ組成をもったSn基合金および
Pb基合金の従来はんだ材、さらに重量％で、Au−3.25％
Siの組成をもったAu基合金の従来ろう材を用いる以外は
同一の条件で比較法1,2および従来法をそれぞれ行なっ
た。Further, for the purpose of comparison, without blending the surface coating raw material powder, a Sn-based alloy having the same composition as the above composition and
Conventional solder material of Pb-based alloy, further by weight%, Au-3.25%
Comparative methods 1 and 2 and the conventional method were performed under the same conditions except that the conventional brazing material of Au-based alloy having the composition of Si was used.
ついで、この結果のはんだ付け後の上記Siチップの上面
に発生した反りを表面粗さ計にて測定し、さらに、残留
熱歪を評価する目的で、前記リードフレームの下面を水
冷し、一方前記Siチップの上面に交流アークを付加し、
これによって10秒間でSiチップの上面温度を室温から30
0℃に加熱し、この状態から室温に冷却する加熱サイク
ルを１サイクルとし、この加熱サイクルを繰り返し行な
い、Siチップに剥離が発生するまでの加熱サイクル数を
測定した。これらの測定結果を第1,2表に示した。 Then, the warp generated on the upper surface of the Si chip after soldering of the result is measured by a surface roughness meter, and for the purpose of evaluating residual thermal strain, the lower surface of the lead frame is water-cooled, while the An AC arc is added to the upper surface of the Si chip,
As a result, the temperature of the top surface of the Si chip can be increased from room temperature to 30
A heating cycle of heating to 0 ° C. and cooling from this state to room temperature was defined as one cycle, and this heating cycle was repeated to measure the number of heating cycles until peeling occurred on the Si chip. The results of these measurements are shown in Tables 1 and 2.
第1,2表に示される結果から、本発明法１〜12において
は、いずれの場合も比較法1,2および従来法に比して、
残留熱歪の発生が僅かであることから、Siチップに発生
する反りも４μｍ以下と相対的に小さく、この程度の反
りならば実用上何らの問題もないものであり、また半導
体装置の作動中に発生する熱付加で起る膨脹と収縮の繰
り返しによってもSiチップが剥離し難いはんだ付けを行
なうことができることが明らかである。From the results shown in Tables 1 and 2, in the methods 1 to 12 of the present invention, in any case, compared with the comparative methods 1 and 2 and the conventional method,
Since the residual thermal strain is small, the warpage of the Si chip is relatively small, 4 μm or less, and there is no problem in practical use with such warpage. It is clear that it is possible to carry out soldering in which the Si chip is difficult to peel off even by repeated expansion and contraction caused by the heat addition generated.
上述のように、この発明の方法によれば、半導体装置の
組立てに際して、はんだ付け時に発生するSi半導体素子
とCu基合金製リードフレーム間の大きな熱膨脹差を十分
に吸収し、はんだ付け後のSi半導体素子における残留熱
歪を著しく低減することができるので、Si半導体素子に
反りや割れ、さらに剥離の発生を著しく抑制することが
でき、しかもすぐれたはんだ付け接合強度および熱伝導
性を保持するなど工業上有用な効果がもたらされるので
ある。As described above, according to the method of the present invention, in assembling the semiconductor device, the large thermal expansion difference between the Si semiconductor element and the Cu-based alloy lead frame generated during soldering is sufficiently absorbed, and the Si after soldering is Since the residual thermal strain in the semiconductor element can be significantly reduced, it is possible to significantly suppress the occurrence of warpage, cracking, and peeling of the Si semiconductor element, and yet to maintain excellent solder joint strength and thermal conductivity. Industrially useful effects are brought about.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 田中 忠治 埼玉県大宮市北袋町１丁目297 三菱金属 株式会社中央研究所内 (56)参考文献 特開 昭55−126396（ＪＰ，Ａ) 特公 昭47−28307（ＪＰ，Ｂ１) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tadaharu Tanaka 1-chome, Kitabukuro-cho, Omiya-shi, Saitama 297 Central Research Laboratory, Mitsubishi Metals Co., Ltd. (56) Reference JP-A-55-126396 (JP, A) JP-B 47 -28307 (JP, B1)
Claims (1)
ムにはんだ付けするに際して、はんだ材として知られて
いるSn基合金またはPb基合金からなる素地中に、0.1〜
５μｍの平均粒径を有する熱膨脹係数の小さいMo,W,N
b、およびTiの炭化物のうちの１種以上からなる炭化物
粒子が、前記炭化物粒子に対する割合で１〜10重量％の
SnまたはAgからなる炭化物粒子めっき被覆層を介して、
５〜50容量％の割合で分散含有してなるはんだ材を用い
ることを特徴とするSi半導体素子をCu基合金製リードフ
レームに少ない残留熱歪ではんだ付けする方法。1. When a Si semiconductor element is soldered to a lead frame made of a Cu-based alloy, 0.1 to 0.1% is added to a base material made of a Sn-based alloy or a Pb-based alloy known as a solder material.
Mo, W, N with a small coefficient of thermal expansion having an average particle size of 5 μm
b, and carbide particles composed of at least one of Ti carbides, in an amount of 1 to 10% by weight relative to the carbide particles.
Via a carbide particle plating coating layer made of Sn or Ag,
A method of soldering a Si semiconductor element to a Cu-based alloy lead frame with a small residual thermal strain, which comprises using a solder material dispersedly contained at a rate of 5 to 50% by volume.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61038525A JPH07121467B2 (en) | 1986-02-24 | 1986-02-24 | Method for soldering Si semiconductor element to Cu-based alloy lead frame with little residual thermal strain |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61038525A JPH07121467B2 (en) | 1986-02-24 | 1986-02-24 | Method for soldering Si semiconductor element to Cu-based alloy lead frame with little residual thermal strain |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62197292A JPS62197292A (en) | 1987-08-31 |
| JPH07121467B2 true JPH07121467B2 (en) | 1995-12-25 |
Family
ID=12527692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61038525A Expired - Lifetime JPH07121467B2 (en) | 1986-02-24 | 1986-02-24 | Method for soldering Si semiconductor element to Cu-based alloy lead frame with little residual thermal strain |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07121467B2 (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01149378A (en) * | 1987-12-04 | 1989-06-12 | Shinko Electric Ind Co Ltd | Lead mounting mechanism for ceramic base substance |
| JPH0417994A (en) * | 1990-05-10 | 1992-01-22 | Asahi Chem Ind Co Ltd | Solder composition |
| JP2810285B2 (en) * | 1993-01-20 | 1998-10-15 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
| JP3226213B2 (en) * | 1996-10-17 | 2001-11-05 | 松下電器産業株式会社 | Solder material and electronic component using the same |
| EP0856376B1 (en) * | 1996-12-03 | 2000-02-09 | Lucent Technologies Inc. | Article comprising fine-grained solder compositions with dispersoid particles |
| US5973405A (en) * | 1997-07-22 | 1999-10-26 | Dytak Corporation | Composite electrical contact structure and method for manufacturing the same |
| TWI230104B (en) * | 2000-06-12 | 2005-04-01 | Hitachi Ltd | Electronic device |
| CN1255563C (en) | 2001-05-24 | 2006-05-10 | 弗莱氏金属公司 | Thermal interface material and heat sink configuration |
| WO2007055308A1 (en) * | 2005-11-11 | 2007-05-18 | Senju Metal Industry Co., Ltd. | Soldering paste and solder joints |
| DE102006039339A1 (en) * | 2006-08-24 | 2008-03-06 | Bayerische Motoren Werke Ag | Hard solder joining components in solid oxide fuel cells used e.g. in electric vehicles, contains ceramic particles, fibers or intermediate layer with reduced coefficient of thermal expansion |
| JP5397415B2 (en) * | 2011-05-27 | 2014-01-22 | 新日鐵住金株式会社 | Solar cell module |
| WO2012165348A1 (en) * | 2011-05-27 | 2012-12-06 | 新日鐵住金株式会社 | Interconnector for solar cells, and solar cell module |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55126396A (en) * | 1979-03-24 | 1980-09-30 | Tokuriki Honten Co Ltd | Brazing material |
-
1986
- 1986-02-24 JP JP61038525A patent/JPH07121467B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62197292A (en) | 1987-08-31 |
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