JPH07120798B2 - Vertical MOSFET - Google Patents
Vertical MOSFETInfo
- Publication number
- JPH07120798B2 JPH07120798B2 JP63066328A JP6632888A JPH07120798B2 JP H07120798 B2 JPH07120798 B2 JP H07120798B2 JP 63066328 A JP63066328 A JP 63066328A JP 6632888 A JP6632888 A JP 6632888A JP H07120798 B2 JPH07120798 B2 JP H07120798B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate electrode
- source
- diffusion region
- conductivity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000009792 diffusion process Methods 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 19
- 230000015556 catabolic process Effects 0.000 description 10
- 239000012535 impurity Substances 0.000 description 8
- 230000005684 electric field Effects 0.000 description 5
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は縦型MOSFETの耐圧向上とオン抵抗低減に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvement of breakdown voltage and reduction of on-resistance of a vertical MOSFET.
（ロ）従来の技術 縦型DSA（Diffusion Self Alignment）構造の縦型MOSFE
Tは一平面上に多数の素子（セル）を等間隔に並べるこ
とにより高耐圧化と大電流化が図られ、高電圧高速スイ
ッチング用として使用されている（特開昭61−80859、H
01L 29/78）。(B) Conventional technology Vertical MOSFE with vertical DSA (Diffusion Self Alignment) structure
T has a high withstand voltage and a large current by arranging a large number of elements (cells) on a plane at equal intervals, and is used for high voltage and high speed switching (Japanese Patent Laid-Open No. 61-80859, H
01L 29/78).
斯る構造の縦型MOSFETは、第５図及び第６図に示す如
く、底部に高濃度N+型層（１）を有するN-型シリコン基
体（２）をドレインとして、その表面上に所定の間隔で
ゲート電極（ポリSiゲート）（３）が配置され、このゲ
ート電極（３）の下にチャンネル部を作るように基体
（２）表面にＰ型拡散領域（４）とN+型ソース領域
（５）を形成したもので、ゲートへの電圧印加によって
ゲート下のＰ型拡散領域（４）（チャンネル部）を通る
ドレイン電流IDSを制御するようにMOSFETを動作させる
ものである。As shown in FIGS. 5 and 6, the vertical MOSFET having such a structure has an N − -type silicon substrate (2) having a high-concentration N + -type layer (1) at the bottom as a drain, and has a predetermined surface on the surface thereof. A gate electrode (poly-Si gate) (3) is arranged at an interval of, and a P-type diffusion region (4) and an N + -type source are formed on the surface of the substrate (2) so as to form a channel portion under the gate electrode (3). The region (5) is formed, and the MOSFET is operated so as to control the drain current I DS passing through the P-type diffusion region (4) (channel portion) under the gate by applying a voltage to the gate.
従来の縦型MOSFETの各セル（６）の形状は、第６図に示
すように四角形となって等間隔で縦横方向に配列され、
四角形の中心からソース電極を取出し、ゲート電極
（３）からはその上の絶縁膜のスルーホールを通して共
通のゲート電極を取出すようになっている。As shown in FIG. 6, the shape of each cell ( 6 ) of the conventional vertical MOSFET is a quadrangle, which is arranged at equal intervals in the vertical and horizontal directions.
The source electrode is taken out from the center of the quadrangle, and the common gate electrode is taken out from the gate electrode (3) through the through hole of the insulating film thereabove.
そして、各セル（６）のチャンネル部形成にあたって
は、ゲート電極（３）を利用したセルフアライン技術に
よりＰ型拡散領域（４）とソース領域（５）を形成する
が、ゲート電極（３）によるセル（６）形状が四角形を
成すことにより、セル（６）のコーナー部（７）への不
純物拡散が他の部分（辺部）への不純物拡散に比べて少
なく、従ってコーナー部（７）のチャンネル部は凸型の
球面形状のPN接合を形成し、逆バイアス時の電界強度が
他よりも大きくなる。その為、セル（６）のコーナー部
（７）で電界集中を発生し、この部分における耐圧が縦
型MOSFETの耐圧を決定していた。尚、（８）はチャンネ
ル部の輪郭を示す。そのうえ、不純物濃度が薄くなるの
で、コーナー部（７）が他の辺部より早くオンし、リー
クが発生したり、動作上電流分布が不均一となる為低V
GS（off）化の妨げになっていた。When forming the channel portion of each cell ( 6 ), the P-type diffusion region (4) and the source region (5) are formed by the self-alignment technique using the gate electrode (3), but the gate electrode (3) is used. Since the shape of the cell ( 6 ) is a quadrangle, the impurity diffusion into the corner portion (7) of the cell ( 6 ) is smaller than that into the other portion (side portion), so that the corner portion (7) of the cell ( 6 ) is diffused. The channel portion forms a convex spherical PN junction, and the electric field strength at the time of reverse bias is higher than the others. Therefore, electric field concentration occurs in the corner portion (7) of the cell ( 6 ), and the breakdown voltage in this portion determines the breakdown voltage of the vertical MOSFET. Incidentally, (8) shows the contour of the channel portion. In addition, since the impurity concentration becomes low, the corner (7) turns on earlier than the other sides, causing a leak or non-uniform current distribution during operation, resulting in a low V
It was a hindrance to GS (off).
（ハ）発明が解決しようとする課題 このように、従来の縦型MOSFETはセル（６）のコーナー
部（７）で耐圧が決定されてしまう欠点があった。ま
た、コーナー部（７）のPN接合の曲率を緩和する為チャ
ンネル部を浅くすることができず、従ってセル（６）の
微細化が難しい欠点があった。更には微細化が困難であ
る為、MOSFETのチャンネル幅GW（セルの周囲長の総和）
を増大してオン抵抗RDS（on）を減少することも困難で
ある欠点があった。(C) Problem to be Solved by the Invention As described above, the conventional vertical MOSFET has a drawback that the breakdown voltage is determined at the corner portion (7) of the cell ( 6 ). Further, since the curvature of the PN junction of the corner portion (7) is relaxed, the channel portion cannot be made shallow, and thus there is a drawback that it is difficult to miniaturize the cell ( 6 ). Furthermore, since miniaturization is difficult, MOSFET channel width GW (total cell perimeter)
It is also difficult to increase the on-state resistance R DS (on) by decreasing.
（ニ）課題を解決するための手段 本発明は斯上した欠点に鑑み、チャンネル部のコーナー
部（23）が形成するPN接合が凹型の曲面を形成するよう
にＰ型拡散領域（13）を格子状に形成し、ゲート電極
（15）は夫々が独立するようアイランド状に形成するこ
とにより、コーナー部（23）での耐圧劣化を防止した縦
型MOSFETを提供するものである。(D) Means for Solving the Problems In view of the above drawbacks, the present invention provides a P-type diffusion region (13) so that a PN junction formed by a corner portion (23) of a channel portion forms a concave curved surface. (EN) A vertical MOSFET in which the gate electrode (15) is formed in an island shape so that the gate electrodes (15) are independent of each other, thereby preventing breakdown voltage deterioration at the corner portion (23).
（ホ）作 用 本発明によれば、コーナー部（23）のPN接合が凹型の曲
面形状を成すので、電界が分散され、集中は起らない。
また、チャンネルのコーナー部（７）は他の部分より不
純物濃度が高くなる為、リーク電流源にはならず、低V
GS（off）化が容易である。(E) Operation According to the present invention, since the PN junction of the corner portion (23) has a concave curved surface shape, the electric field is dispersed and concentration does not occur.
In addition, since the impurity concentration of the corner portion (7) of the channel is higher than that of other portions, it does not serve as a leak current source and a low V
Easy GS (off) conversion.
（ヘ）実施例 以下、本発明の一実施例を図面を参照しながら詳細に説
明する。(F) Embodiment Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図及び第２図は本発明の縦型MOSFETを示す平面図及
びAA線断面図を示す。（11）は裏面にドレイン電極が設
けられる比較的低比抵抗のN+型シリコン半導体基板、
（12）は基板（11）表面に設けられ共通のドレイン領域
となる比較的高比抵抗のＮ型エピタキシャル層、（13）
はＰ型拡散領域、（14）はN+型拡散領域（ソース領
域）、（15）はポリシリコンから成るゲート電極、（1
6）はCVD酸化膜、（17）は共通ゲート電極、（18）は共
通ソース電極、（19）はＰ型拡散領域（13）とN+型拡散
領域（14）とでゲート電極（15）下に形成されるチャン
ネル部を示す。1 and 2 are a plan view and a sectional view taken along line AA showing a vertical MOSFET of the present invention. (11) is an N + type silicon semiconductor substrate having a relatively low specific resistance with a drain electrode provided on the back surface,
(12) is an N-type epitaxial layer having a relatively high specific resistance, which is provided on the surface of the substrate (11) and serves as a common drain region, (13)
Is a P-type diffusion region, (14) is an N + -type diffusion region (source region), (15) is a gate electrode made of polysilicon, (1
6) is a CVD oxide film, (17) is a common gate electrode, (18) is a common source electrode, (19) is a P-type diffusion region (13) and an N + -type diffusion region (14), and a gate electrode (15). The channel part formed below is shown.
Ｐ型拡散領域（13）は、本願の特徴とする如く格子状に
形成され、残るエピタキシャル層（12）表面上を覆うよ
うにゲート酸化膜（20）を介してゲート電極（15）が配
設される。ゲート電極（15）の形状は一例として四角形
状を成し、夫々がエピタキシャル層（12）上に単独で独
立して配置される。その為、本願のMOSFETはアイランド
状のゲート電極（15）が所望の大きさと間隔で縦横方向
に配列されたパターンとなり、前記四角形の外側にＰ型
拡散領域（13）とN+型拡散領域（14）の両方にオーミッ
クコンタクトする共通ソース電極（18）が配設される。
ゲート電極（15）はそのままでは電気的に独立してしま
う為、ゲート電極（15）上の酸化膜（16）を開孔したコ
ンタクトホール（21）を介してソース電極（18）と平行
に延在する共通ゲート電極（15）が各ゲート電極（15）
とコンタクトすることにより、全てのゲート電極（15）
を電気的に同電位にする。尚、共通ゲート電極（17）と
共通ソース電極（18）とは同層の配線層で形成される
為、両者は図示せぬ外部接続用電極パッドから櫛歯状に
形成され、且つ交互に相対向して延在するようにパター
ニングされる。The P-type diffusion region (13) is formed in a lattice shape as the feature of the present invention, and the gate electrode (15) is arranged so as to cover the surface of the remaining epitaxial layer (12) via the gate oxide film (20). To be done. The shape of the gate electrode (15) is, for example, a quadrangular shape, and each is individually and independently arranged on the epitaxial layer (12). Therefore, the MOSFET of the present application has a pattern in which the island-shaped gate electrodes (15) are arranged in the vertical and horizontal directions with a desired size and interval, and the P-type diffusion region (13) and the N + -type diffusion region ( A common source electrode (18) is provided which makes ohmic contact with both of them.
Since the gate electrode (15) is electrically independent as it is, it extends in parallel with the source electrode (18) through the contact hole (21) formed by opening the oxide film (16) on the gate electrode (15). Existing common gate electrode (15) is each gate electrode (15)
All gate electrodes by contact with (15)
To the same electric potential. Since the common gate electrode (17) and the common source electrode (18) are formed in the same wiring layer, both of them are formed in a comb shape from an external connection electrode pad (not shown), and are alternately arranged. It is patterned so as to extend toward.
ゲート電極（15）下のチャンネル部（19）形成にあたっ
ては、先ずエピタキシャル層（12）表面にＰ型拡散領域
（13）のうちの深い領域を形成する為のＰ型不純物（ボ
ロン等）を選択的にデポジットした後、エピタキシャル
層（12）表面に膜厚1000Å程度のゲート酸化膜（20）と
膜厚5000乃至8000Åのポリシリコン層を生成し、このポ
リシリコン層をアイランド状にパターニングすることで
ゲート電極（15）を形成し、ゲート電極（15）をマスク
としたセルフアライン技術により全面にＰ型不純物（ボ
ロン等）をイオン注入し、先に導入したＰ型不純物と共
にこのＰ型不純物を熱拡散してＰ型拡散領域（13）を形
成し、今度はゲート電極（15）とパターニングしたホト
レジスト膜をマスクとしたセルフアライン技術によりＮ
型不純物（リン等）をイオン注入してソースとなるN+型
拡散領域（14）を形成し、その結果Ｐ型拡散領域（13）
とN+型拡散領域（14）が規定するゲート電極（15）下の
Ｐ型拡散領域（13）がチャンネル部（19）となる。そし
て、ゲート電極（15）を覆う様にCVD酸化膜（16）を生
成し、ゲート電極（15）上とＰ型拡散領域（13）上に夫
々コンタクトホール（21）（22）を形成した後全面に電
極配線層を形成し、この電極配線層をパターニングして
共通ベース電極（17）と共通ソース電極（18）を形成す
ることにより本願のMOSFETを得る。尚、電極配線層材料
としてはアルミニウム（Al）、アルミニウム・シリコン
（Al−Si）、タングステン（Ｗ）等が選択される。In forming the channel portion (19) under the gate electrode (15), first, a P-type impurity (boron or the like) for forming a deep region of the P-type diffusion region (13) on the surface of the epitaxial layer (12) is selected. After the selective deposition, a gate oxide film (20) with a film thickness of about 1000Å and a polysilicon layer with a film thickness of 5000 to 8000Å are formed on the surface of the epitaxial layer (12), and this polysilicon layer is patterned into an island shape. The gate electrode (15) is formed, P-type impurities (boron, etc.) are ion-implanted into the entire surface by the self-alignment technique using the gate electrode (15) as a mask, and the P-type impurity is thermally heated together with the P-type impurity introduced previously. A P-type diffusion region (13) is formed by diffusion, and this time, the gate electrode (15) and the patterned photoresist film are used as a mask to perform N
Type impurities (phosphorus, etc.) are ion-implanted to form an N + type diffusion region (14) serving as a source, and as a result, a P type diffusion region (13)
The P-type diffusion region (13) under the gate electrode (15) defined by the N + -type diffusion region (14) serves as a channel portion (19). Then, after forming a CVD oxide film (16) so as to cover the gate electrode (15) and forming contact holes (21) and (22) on the gate electrode (15) and the P-type diffusion region (13), respectively. The MOSFET of the present application is obtained by forming an electrode wiring layer on the entire surface and patterning the electrode wiring layer to form a common base electrode (17) and a common source electrode (18). Aluminum (Al), aluminum-silicon (Al-Si), tungsten (W), or the like is selected as the electrode wiring layer material.
斯る構成によれば、チャンネル部（19）がアイランド状
に形成されたゲート電極（15）の内側へ形成される為、
四角形状のコーナー部（23）のPN接合は内側へ折れ曲っ
た形状を成し、従って第１図に示す如く、前記PN接合か
らエピタキシャル層（12）側へ形成される空乏層（24）
も前記PN接合の形状に沿ったものとなる。この様な形状
では、エピタキシャル層（12）からＰ型拡散領域（13）
への電界は集中せず、前記空乏層（24）の凹曲面状に沿
って分散することになる。その為、本願のMOSFETの耐圧
は純粋に側辺のチャンネル部（19）でのパンチスルー又
はツェナー降伏電圧で決まり、コーナー部（23）での耐
圧劣化は無い。According to this structure, since the channel part (19) is formed inside the island-shaped gate electrode (15),
The PN junction of the quadrangular corner portion (23) is bent inward, and therefore, as shown in FIG. 1, the depletion layer (24) formed from the PN junction to the epitaxial layer (12) side.
Also follows the shape of the PN junction. With such a shape, from the epitaxial layer (12) to the P-type diffusion region (13)
An electric field to the depletion layer (24) is not concentrated but is dispersed along the concave curved surface of the depletion layer (24). Therefore, the withstand voltage of the MOSFET of the present application is purely determined by punch-through or Zener breakdown voltage in the channel portion (19) on the side, and there is no deterioration in withstand voltage in the corner portion (23).
尚、本実施例はゲート電極（15）も含めて２層電極構造
を採る為、共通ゲート電極（17）下のチャンネル部（1
9）へのソース電流供給はN+型拡散領域（14）を介して
行なわれる。その為、共通ゲート電極（17）の下部はチ
ャンネル部（19）を除いたＰ型拡散領域（13）の全面に
N+型拡散領域（14）を設けても良く、この場合は共通ソ
ース電極（18）からの電流供給がよりスムーズに行なわ
れる。Since the present embodiment has a two-layer electrode structure including the gate electrode (15), the channel portion (1) under the common gate electrode (17) is
Source current is supplied to 9) through the N + type diffusion region (14). Therefore, the lower part of the common gate electrode (17) is on the entire surface of the P type diffusion region (13) excluding the channel part (19).
An N + type diffusion region (14) may be provided, and in this case, current supply from the common source electrode (18) can be performed more smoothly.
第３図及び第４図は夫々本願の第２の実施例を示す平面
図及びBB線断面図である。先の実施例としては共通ソー
ス電極（18）の取出し方法が異なる。即ち、Ｐ型拡散領
域（13）の表面にその形状に対応した格子状のソース電
極（30）を配設し、再度SiN,ポリイミド系絶縁膜等の層
間絶縁膜（31）で覆った後、櫛歯状の共通ゲート電極
（17）と共通ソース電極（18）を配設したものである。
ソース電極（30）材料としては、タングステン（Ｗ）等
の高融点金属やアルミニウム・シリコン（Al−Si）が選
択される。本実施例によれば、Ｐ型拡散領域（13）の全
部に格子状のソース電極（30）が延在するので、共通ソ
ース電極（18）からチャンネル部（19）への電流供給が
より一層スムーズに且つ平均的に行なわれる。また各チ
ャンネル領域までのチャンネル抵抗が低減し、寄生バイ
ポーラトランジスタ動作を防ぎ破壊耐畳の増大が図れ
る。FIG. 3 and FIG. 4 are a plan view and a sectional view taken along the line BB showing a second embodiment of the present application, respectively. The method of extracting the common source electrode (18) is different from that of the previous embodiment. That is, a lattice-shaped source electrode (30) corresponding to the shape is provided on the surface of the P-type diffusion region (13), and after being covered again with an interlayer insulating film (31) such as SiN or a polyimide-based insulating film, A common gate electrode (17) and a common source electrode (18) having a comb shape are arranged.
A refractory metal such as tungsten (W) or aluminum-silicon (Al-Si) is selected as the source electrode (30) material. According to this embodiment, since the lattice-shaped source electrode (30) extends over the entire P-type diffusion region (13), the current supply from the common source electrode (18) to the channel portion (19) is further enhanced. Smooth and average. Further, the channel resistance up to each channel region is reduced, the operation of the parasitic bipolar transistor is prevented, and the breakdown resistance can be increased.
（ト）発明の効果 以上説明した如く、本発明によれば電界集中による耐圧
劣化を防止したので、耐圧を向上した縦型MOSFETが得ら
れる利点を有する。また、耐圧劣化が無いので、チャン
ネル部（19）の拡散深さを浅くしてパターンの微細化が
図れる利点を有する。さらに微細化することでMOSFETの
チャンネル幅GWを増大し、オン抵抗RDS（on）を低減で
きる利点をも有する。また低VGS（off）化、高gm化した
場合にもコーナー部でのショートチャンネル効果等を抑
えることができる。(G) Effect of the Invention As described above, according to the present invention, the breakdown voltage deterioration due to the electric field concentration is prevented, so that there is an advantage that a vertical MOSFET having an improved breakdown voltage can be obtained. Further, since there is no deterioration in breakdown voltage, there is an advantage that the pattern portion can be miniaturized by making the diffusion depth of the channel portion (19) shallow. Further miniaturization has the advantages that the channel width GW of the MOSFET can be increased and the on-resistance R DS (on) can be reduced. Further, even when the V GS (off) and the gm are increased, the short channel effect at the corner can be suppressed.
第１図及び第２図は夫々本発明の一実施例を説明する為
の平面図及びAA線断面図、第３図及び第４図は夫々本発
明の第２の実施例を説明する為の平面図及びBB線断面
図、第５図及び第６図は従来例を説明する為の平面図及
び断面図である。 （11）はN+型半導体基板、（13）はＰ型拡散領域、（1
4）はN+型拡散領域、（15）はゲート電極、（17）は共
通ゲート電極、（18）は共通ソース電極、（19）はチャ
ンネル部、（23）は四角形状のコーナー部、（24）は空
乏層である。1 and 2 are plan views and sectional views taken along the line AA for explaining an embodiment of the present invention, and FIGS. 3 and 4 are respectively for explaining a second embodiment of the present invention. A plan view and a sectional view taken along line BB, and FIGS. 5 and 6 are a plan view and a sectional view for explaining a conventional example. (11) is an N + type semiconductor substrate, (13) is a P type diffusion region, (1
4) is an N + type diffusion region, (15) is a gate electrode, (17) is a common gate electrode, (18) is a common source electrode, (19) is a channel part, (23) is a rectangular corner part, ( 24) is the depletion layer.
Claims (3)
その一主表面の一部に第２導電型の拡散領域が形成さ
れ、この拡散領域の表面の一部に第１導電型のソース領
域が形成され、前記第２導電型拡散領域周辺部上に絶縁
膜を介してゲート電極が形成され、前記ゲート電極への
電圧印可によってソース・ドレイン間電流を制御する縦
型MOSFETにおいて、 前記第２導電型領域は前記ゲート電極に隣接する浅い領
域と前記浅い領域よりも拡散深さが深い高濃度領域とを
有し、 前記第２導電型領域を縦方向に延在する部分と横方向に
延在する部分とを有する格子状パターンに形成し、前記
ゲート電極は前記格子パターンの網目の位置に各々が独
立するようにアイランド状に縦横に配列し、 前記ソース領域は前記ゲート電極の各々を環状に取り囲
み、前記第２導電型領域の深い部分は前記ゲート電極を
格子状に取り囲み、 前記各々のゲート電極をストライプ状のアルミゲート電
極で電気的に接続し、且つ前記アルミゲート電極と平行
に延在するソース電極が前記格子状パターンの縦方向に
のみ前記ソース領域と前記第２導電型拡散領域の深い部
分にコンタクトしながらストライプ状に延在する事を特
徴とする縦型MOSFET。1. A semiconductor substrate of the first conductivity type as a drain,
A second-conductivity-type diffusion region is formed on a part of the one main surface, and a first-conductivity-type source region is formed on a part of the surface of the diffusion region. In a vertical MOSFET in which a gate electrode is formed via an insulating film and a source-drain current is controlled by applying a voltage to the gate electrode, the second conductivity type region is a shallow region adjacent to the gate electrode and the shallow region. A high-concentration region having a diffusion depth larger than that of the region, and the second conductivity type region is formed in a lattice pattern having a portion extending in a vertical direction and a portion extending in a horizontal direction, and the gate is formed. The electrodes are vertically and horizontally arranged in an island shape so that they are independent of each other in a mesh pattern of the lattice pattern, the source region annularly surrounds each of the gate electrodes, and a deep portion of the second conductivity type region is the gate. Grid with electrodes And each of the gate electrodes is electrically connected by a striped aluminum gate electrode, and a source electrode extending parallel to the aluminum gate electrode is provided only in the vertical direction of the lattice pattern with the source region and the source region. A vertical MOSFET characterized in that it extends in stripes while contacting the deep portion of the second conductivity type diffusion region.
と、その一主表面に格子状に形成した第２導電型の拡散
領域と、この拡散領域の表面に選択的に形成した第１導
電型のソース領域と、前記第２導電型拡散領域で囲まれ
た領域上に絶縁膜を介してアイランド状に配設したゲー
ト電極と、前記第２導電型拡散領域と前記ソース領域の
両方にオーミックコンタクトし前記第２導電型拡散領域
の表面に沿つて格子状に配設した下層のソース電極と、
縦横に配列された前記ゲート電極の夫々を共通接続する
ストライプ状の共通ゲート電極と、この共通ゲート電極
と平行に延在し前記下層のソース電極とコンタクトする
ソース電極とを具備することを特徴とする縦型MOSFET。2. A first-conductivity-type semiconductor substrate to serve as a drain, a second-conductivity-type diffusion region formed in a lattice shape on one main surface thereof, and a first-conductivity selectively formed on the surface of the diffusion region. Type source region, a gate electrode arranged in an island shape on the region surrounded by the second conductivity type diffusion region via an insulating film, and an ohmic contact on both the second conductivity type diffusion region and the source region. A lower layer source electrode which is in contact with and is arranged in a lattice shape along the surface of the second conductivity type diffusion region;
A stripe-shaped common gate electrode commonly connecting each of the gate electrodes arranged vertically and horizontally, and a source electrode extending in parallel with the common gate electrode and in contact with the source electrode of the lower layer. Vertical MOSFET that does.
歯状形状を有し、且つ交互に延在する事を特徴とする請
求項１又は２に記載の縦型MOSFET。3. The vertical MOSFET according to claim 1, wherein the common gate electrode and the source electrode have a comb-like shape and extend alternately.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63066328A JPH07120798B2 (en) | 1988-03-18 | 1988-03-18 | Vertical MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63066328A JPH07120798B2 (en) | 1988-03-18 | 1988-03-18 | Vertical MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01238174A JPH01238174A (en) | 1989-09-22 |
| JPH07120798B2 true JPH07120798B2 (en) | 1995-12-20 |
Family
ID=13312665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63066328A Expired - Lifetime JPH07120798B2 (en) | 1988-03-18 | 1988-03-18 | Vertical MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07120798B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106104806A (en) * | 2013-09-20 | 2016-11-09 | 莫诺利斯半导体有限公司 | High-voltage MOSFET device and manufacture method thereof |
| CN107636835A (en) * | 2015-12-11 | 2018-01-26 | 富士电机株式会社 | Semiconductor device and manufacture method |
| US9991376B2 (en) | 2013-09-20 | 2018-06-05 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665996A (en) * | 1994-12-30 | 1997-09-09 | Siliconix Incorporated | Vertical power mosfet having thick metal layer to reduce distributed resistance |
| US5767546A (en) * | 1994-12-30 | 1998-06-16 | Siliconix Incorporated | Laternal power mosfet having metal strap layer to reduce distributed resistance |
| JP6416142B2 (en) * | 2016-03-11 | 2018-10-31 | 株式会社東芝 | Semiconductor device |
| WO2018003064A1 (en) * | 2016-06-30 | 2018-01-04 | 株式会社日立製作所 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57153468A (en) * | 1981-03-18 | 1982-09-22 | Toshiba Corp | Insulated gate type field effect transistor |
| JPS5889864A (en) * | 1981-11-24 | 1983-05-28 | Hitachi Ltd | Insulated gate type semiconductor device |
| JPS59149058A (en) * | 1983-02-15 | 1984-08-25 | Matsushita Electric Works Ltd | Metal oxide semiconductor type transistor |
-
1988
- 1988-03-18 JP JP63066328A patent/JPH07120798B2/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106104806A (en) * | 2013-09-20 | 2016-11-09 | 莫诺利斯半导体有限公司 | High-voltage MOSFET device and manufacture method thereof |
| EP3047523A4 (en) * | 2013-09-20 | 2017-10-18 | Monolith Semiconductor Inc. | High voltage mosfet devices and methods of making the devices |
| US9853147B2 (en) | 2013-09-20 | 2017-12-26 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
| US9991376B2 (en) | 2013-09-20 | 2018-06-05 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
| US10361302B2 (en) | 2013-09-20 | 2019-07-23 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
| US10692999B2 (en) | 2013-09-20 | 2020-06-23 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
| CN107636835A (en) * | 2015-12-11 | 2018-01-26 | 富士电机株式会社 | Semiconductor device and manufacture method |
| CN107636835B (en) * | 2015-12-11 | 2021-03-19 | 富士电机株式会社 | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01238174A (en) | 1989-09-22 |
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