JPH0687506B2 - Power MOSFET - Google Patents
Power MOSFETInfo
- Publication number
- JPH0687506B2 JPH0687506B2 JP63066327A JP6632788A JPH0687506B2 JP H0687506 B2 JPH0687506 B2 JP H0687506B2 JP 63066327 A JP63066327 A JP 63066327A JP 6632788 A JP6632788 A JP 6632788A JP H0687506 B2 JPH0687506 B2 JP H0687506B2
- Authority
- JP
- Japan
- Prior art keywords
- cell
- channel region
- region
- power mosfet
- corner portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000009792 diffusion process Methods 0.000 description 14
- 239000008186 active pharmaceutical agent Substances 0.000 description 8
- 230000005684 electric field Effects 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 239000012535 impurity Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明はパワーMOSFETの耐圧向上とオン抵抗低減に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvement of breakdown voltage and reduction of on-resistance of a power MOSFET.
（ロ）従来の技術 縦型DSA（Diffosion Self Alignment）構造のパワーMOS
FETは一平面上に多数の素子（セル）を等間隔に並べる
ことにより高耐圧化と大電流化が図られ、高電圧高速ス
イッチング用として使用されている（特開昭61−80859,
H01L29/78）。(B) Conventional technology Power MOS with vertical DSA (Diffosion Self Alignment) structure
The FET is used for high-voltage and high-speed switching by increasing the withstand voltage and current by arranging a large number of elements (cells) on a plane at equal intervals (Japanese Patent Laid-Open No. 61-80859).
H01L29 / 78).
斯る構造のパワーMOSFETは、底部に高濃度N+型層を有す
るN-型シリコン基体をドレインとして、その表面上にソ
ース電極用の開孔部を有するゲート電極（ポリSiゲー
ト）が配置され、このゲート電極下にチャンネル領域を
作るようにＰ型層とN+型層（ソース領域）を形成したも
ので、ゲートへの電圧印加によってチャンネル領域を通
るドレイン電流IDSを制御するものである。In the power MOSFET having such a structure, an N - type silicon substrate having a high-concentration N + type layer at the bottom is used as a drain, and a gate electrode (poly Si gate) having an opening for a source electrode is arranged on the surface thereof. A P-type layer and an N + -type layer (source region) are formed so as to form a channel region under the gate electrode, and a drain current I DS passing through the channel region is controlled by applying a voltage to the gate. .
従来のパワーMOSFETにおいては、各MOSセルのチャンネ
ル領域（１）の輪郭は第６図に示すように四角形（又は
六角形）となって等間隔で縦横方向に配列され、四角形
の中心からソース電極を取出し、ゲート電極からは、そ
の上の絶縁膜のスルーホールを通してゲート電極を取出
す様になっている。尚、（２）はゲート電極の輪郭、
（３）はＰ型領域、（４）はソース領域である。In the conventional power MOSFET, the contour of the channel region (1) of each MOS cell is a quadrangle (or hexagon) as shown in FIG. 6 and arranged at equal intervals in the vertical and horizontal directions. The gate electrode is taken out from the gate electrode through the through hole of the insulating film thereabove. Incidentally, (2) is the outline of the gate electrode,
(3) is a P-type region, and (4) is a source region.
このようなパワーMOSFETのチャンネル領域（１）形成に
あたっては、ゲート電極（２）を利用したセルフアライ
ン技術によりＰ型層（３）とN+型層（４）を形成する
が、ゲート電極（２）によるセル(5)形状が四角形状を
成すことにより、チャンネル領域（１）のコーナー部
（６）への不純物拡散が他の部分（辺部）への拡散に比
べて少なく、従ってコーナー部（６）のチャンネル部は
凸型の球面形状のPN接合を形成し、逆バイアス時の電界
強度が他よりも大きくなる。その為、セル(5)のコーナ
ー部（６）で電界集中を発生し、この部分における耐圧
がパワーMOSFETの耐圧を決定していた。そのうち、不純
物濃度が薄くなるのでコーナー部（６）が他よりも早く
オンし、リークが発生したり、動作上電流分布が不均一
となる為低VGS（off）化の妨げになっていた。In forming the channel region (1) of such a power MOSFET, the P-type layer (3) and the N + -type layer (4) are formed by the self-alignment technique using the gate electrode (2), but the gate electrode (2 Since the cell ( 5 ) formed by) has a square shape, the diffusion of impurities into the corner portion (6) of the channel region (1) is smaller than that of diffusion into other portions (side portions). The channel portion of 6) forms a convex spherical PN junction, and the electric field strength at the time of reverse bias becomes larger than the others. Therefore, electric field concentration occurs at the corner portion (6) of the cell ( 5 ), and the breakdown voltage in this portion determines the breakdown voltage of the power MOSFET. Among them, the impurity concentration becomes thin, so the corner (6) turns on earlier than the others, and leakage occurs, and the current distribution becomes non-uniform during operation, which hinders lowering V GS (off). .
（ハ）発明が解決しようとする課題 この様に、従来のパワーMOSFETにはセル(5)コーナー部
（６）で耐圧が劣化する欠点があった。また、コーナー
部（６）のPN接合の曲率を緩和する為チャンネル領域
（１）の拡散深さを浅くすることができず、従ってセル
(5)の微細化が難しい欠点があった。更には微細化が難
しい為、チャンネル幅GW（セルの周囲長の総和）を増大
してオン抵抗RDS（on）を下げることも困難である欠点
があった。(C) Problem to be Solved by the Invention As described above, the conventional power MOSFET has a drawback that the breakdown voltage is deteriorated at the corner portion (6) of the cell ( 5 ). Further, since the curvature of the PN junction at the corner portion (6) is relaxed, the diffusion depth of the channel region (1) cannot be made shallow, and therefore the cell
( 5 ) had a drawback that it was difficult to miniaturize it. Furthermore, since it is difficult to miniaturize, it is difficult to increase the channel width GW (total cell perimeter) and lower the on-resistance R DS (on).
（ニ）課題を解決するための手段 本発明は斯上した欠点に鑑み、セル(17)で囲まれた領域
にチャンネル領域（18）のコーナー部（20）と重畳する
第２のチャンネル領域（19）を設け、且つ第２のチャン
ネル領域（19）表面にもソース領域（22）とソース電極
を設けて第２のセル(23)とすることにより、微細化した
オン抵抗RDS（on）を低減せしめたパワーMOSFETを提供
するものである。(D) Means for Solving the Problems In view of the above drawbacks, the present invention provides a second channel region (a) that overlaps a corner portion (20) of a channel region (18) in a region surrounded by cells ( 17 ). 19) and by providing the source region (22) and the source electrode also on the surface of the second channel region (19) to form the second cell ( 23 ), the miniaturized on-resistance R DS (on) It is intended to provide a power MOSFET with reduced power consumption.
（ホ）作用 本発明によれば、チャンネル領域（18）のコーナー部
（20）に第２のチャンネル領域（19）が重畳するので、
セル(17)から第２のセル(23)までＰ型の拡散領域が連続
して形成され、この部分での電界集中が緩和できる。そ
の為パワーMOSFETの耐圧を維持しつつチャンネル領域
（18）を浅く形成してセル(17)を微細化し、チャンネル
幅GWを増大できる。また、第２のチャンネル領域（19）
も第２のセル(23)として活用するので、その分だけチャ
ンネル幅GWを更に増大できる。また、チャンネルのコー
ナー部（20）はドレイン電流IDSが流れないので、リー
ク電流を防止し、低VGS（off）化が容易である。(E) Action According to the present invention, since the second channel region (19) is superposed on the corner portion (20) of the channel region (18),
A P-type diffusion region is continuously formed from the cell ( 17 ) to the second cell ( 23 ), and electric field concentration in this portion can be relaxed. Therefore, while maintaining the breakdown voltage of the power MOSFET, the channel region (18) can be formed shallow and the cell ( 17 ) can be miniaturized to increase the channel width GW. Also, the second channel area (19)
Since it is also used as the second cell ( 23 ), the channel width GW can be further increased by that amount. Further, since the drain current I DS does not flow in the corner portion (20) of the channel, it is possible to prevent a leak current and easily reduce V GS (off).
（ヘ）実施例 以下、本発明の第１の実施例を図面を参照しながら詳細
に説明する。(F) Embodiment Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.
第１図及び第２図は本発明のパワーMOSFETの平面図及び
AA線断面図を示す。（11）は裏面にドレイン電極が設け
られる低比抵抗のN+型シリコン半導体基板、（12）は基
板（11）表面に設けられ共通のドレイン領域となる高比
抵抗のＮ型エピタキシャル層、（13）はＰ型拡散領域、
（14）はN+型拡散領域（ソース領域）、（15）はゲート
電極、（16）は酸化膜、(17)はゲート電極（15）の開孔
部を示すゲートセル、（18）はＰ型拡散領域（13）とN+
型ソース領域（14）とで規定するチャンネル領域で図中
の点線がその輪郭を示す。ゲート電極（15）が規定する
ゲートセル(17)形状は１例として四角形状を成し、等間
隔で縦横に配列され、セル(17)の中央からＰ型拡散層
（13）とソース領域（14）の両方にオーミックコンタク
トする図示せぬソース電極が酸化膜（16）によってゲー
ト電極（15）と絶縁されて取出される。ゲート電極（1
5）はポリシリコン、ソース電極はアルミニウムから成
る。1 and 2 are a plan view of a power MOSFET of the present invention and
A sectional view taken along the line AA is shown. (11) is a low-resistivity N + type silicon semiconductor substrate having a drain electrode on the back surface, (12) is a high-resistivity N-type epitaxial layer provided on the surface of the substrate (11) and serving as a common drain region, ( 13) is a P-type diffusion region,
(14) is an N + type diffusion region (source region), (15) is a gate electrode, (16) is an oxide film, ( 17 ) is a gate cell showing an opening of the gate electrode (15), and (18) is P. Type diffusion region (13) and N +
In the channel region defined by the mold source region (14), the dotted line in the figure shows its outline. The shape of the gate cell ( 17 ) defined by the gate electrode (15) is, for example, a quadrangular shape and arranged vertically and horizontally at equal intervals, and the P-type diffusion layer (13) and the source region (14) are arranged from the center of the cell ( 17 ). Source electrode (not shown) which makes ohmic contact with both of the gate electrodes is isolated from the gate electrode (15) by the oxide film (16) and is taken out. Gate electrode (1
5) is made of polysilicon and the source electrode is made of aluminum.
そして、ゲートセル(17)に囲まれた部分、即ちセル(17)
ピッチとは半ピッチだけずれた位置に、本願の特徴とす
る第２のチャンネル領域（19）がチャンネル領域（18）
のコーナー部（20）と四隅で重畳するように設けてい
る。第２のチャンネル領域（19）はセル(17)の間に形成
したＰ型拡散領域（21）とN+型ソース領域（22）とで規
定され、表面のゲート電極（15）を開孔してソース電極
を配設することにより、ここを第２のセル(23)としてMO
SFETの動作に活用する。第２のセル(23)の形状・寸法は
問わないが、セル(17)と同形状・同寸法とすれば最も効
率的である。結果、表面はセル(17)と第２のセル(23)が
タイル状に配列されたパターンとなる。The gate cells surrounded by part (17), or cell (17)
The second channel region (19), which is a feature of the present invention, is located at a position shifted from the pitch by a half pitch, and the second channel region (19) is the channel region (18).
It is provided so as to overlap the corners (20) of the four corners. The second channel region (19) is defined by the P-type diffusion region (21) and the N + -type source region (22) formed between the cells ( 17 ) and opens the gate electrode (15) on the surface. By arranging the source electrode as a second cell ( 23 )
Used for SFET operation. The shape and size of the second cell ( 23 ) are not limited, but it is most efficient if the second cell ( 23 ) has the same shape and size as the cell ( 17 ). As a result, the surface has a pattern in which cells ( 17 ) and second cells ( 23 ) are arranged in a tile.
チャンネル領域（18）と第２のチャンネル領域（19）と
が重畳した部分の断面構造は第３図の如くになる。第３
図は第１図のBB線断面図を示す。同図から明らかな様
に、セル(17)と第２のセル(23)両方向からの不純物拡散
（横方向拡散）によりチャンネル領域（18）から第２の
チャンネル領域（19）までＰ型の拡散領域が連続し、こ
の部分はMOSFET動作に寄与しない、つまりドレイン・ソ
ース間電流が流れない領域となる。尚、チャンネル領域
（18）と第２のチャンネル領域（19）はゲート電極（1
5）を利用したセルフアライン技術によりボロン（Ｂ）
をイオン注入することで同時に形成され、前記重畳部分
上のゲート電極（15）が電気的接続の為に除去できない
ことから、両者はゲート電極（15）側端部からの横方向
拡散によってのみ重畳する。The cross-sectional structure of the portion where the channel region (18) and the second channel region (19) overlap is as shown in FIG. Third
The figure shows a cross-sectional view taken along the line BB of FIG. As is clear from the figure, P-type diffusion from the channel region (18) to the second channel region (19) by impurity diffusion (lateral diffusion) from both directions of the cell ( 17 ) and the second cell ( 23 ). The region is continuous and this part does not contribute to the MOSFET operation, that is, the region where the drain-source current does not flow. The channel region (18) and the second channel region (19) are connected to the gate electrode (1
Boron (B) by self-alignment technology using 5)
Are formed at the same time by ion implantation, and the gate electrode (15) on the overlapping portion cannot be removed due to electrical connection, so that both are overlapped only by lateral diffusion from the end portion on the gate electrode (15) side. To do.
斯る構成によれば、チャンネル領域（18）のコーナー部
（20）に第２のチャンネル領域（19）が重畳するので、
表面付近のPN接合の一部が実質的に消滅し、チャンネル
領域（18）から第２のチャンネル領域（19）まで途切れ
ること無くPN接合が連続する。その際、重畳部分のPN接
合の形状は、チャンネル領域（18）のコーナー部（20）
が形成する凸型の球面形状と第２のチャンネル領域（1
9）のコーナー部分が形成する凸型の球面形状とが相対
向して重畳した形状となる。According to such a configuration, the second channel region (19) is superposed on the corner portion (20) of the channel region (18),
A part of the PN junction near the surface is substantially eliminated, and the PN junction continues without interruption from the channel region (18) to the second channel region (19). At that time, the shape of the PN junction in the overlapping portion is determined by the corner portion (20) of the channel region (18).
Formed by the convex spherical surface and the second channel region (1
The convex spherical shape formed by the corner portion of 9) is opposed to and overlaps.
この様な形状のPN接合に逆方向電圧（ゲート電圧）を加
えると、空乏層は第４図の様に拡がる。即ち、チャンネ
ル領域（18）と第２のチャンネル領域（19）が形成する
PN接合からエピタキシャル層（12）側へ前記逆方向電圧
の大きさに応じた一定の厚みで拡がるものである。とこ
ろが、前記重畳部分では対向するPN接合の両方からPN接
合の曲率に沿って拡がる為、空乏層（24）はより平坦に
拡がり易くなる。すると、PN接合に加わる電界は図中矢
印で示す如くになり、前記重畳部分からはPN接合面に対
して直角方向に加わることができずに分散してしまう。
その為、PN接合の湾曲部分に加わる電界強度が弱まり、
PN接合への電界集中を緩和することができる。When a reverse voltage (gate voltage) is applied to the PN junction having such a shape, the depletion layer expands as shown in FIG. That is, the channel region (18) and the second channel region (19) are formed.
It spreads from the PN junction to the epitaxial layer (12) side with a constant thickness according to the magnitude of the reverse voltage. However, in the overlapping portion, the depletion layer (24) easily spreads more flatly because it spreads from both of the facing PN junctions along the curvature of the PN junction. Then, the electric field applied to the PN junction becomes as shown by the arrow in the figure, and cannot be applied in the direction perpendicular to the PN junction surface from the superposed portion and is dispersed.
Therefore, the electric field strength applied to the curved part of the PN junction weakens,
The electric field concentration on the PN junction can be reduced.
従って本願発明によれば、セル(17)のコーナー部分（2
0）における電界集中を緩和し、この部分での耐圧劣化
を防止してセル(17)全体の耐圧を向上することができ
る。その為、チャンネル領域（18）を浅くすることでセ
ル（17）の微細化が図れる。Therefore, according to the present invention, the corner portions of the cell (17) (2
It is possible to alleviate the electric field concentration in 0), prevent the breakdown voltage from degrading in this portion, and improve the breakdown voltage of the entire cell ( 17 ). Therefore, the cell (17) can be miniaturized by making the channel region (18) shallow.
本願はまた、第２のチャンネル領域（19）を形成するＰ
型拡散領域（21）表面にもN+型ソース領域（22）とソー
ス電極を設け、この領域をも第２のセル(23)として活用
するので、セル(17)周囲のチャンネルの他に第２のセル
(23)周囲のチャンネルもMOSFET動作に寄与させることが
できる。その為、第２のセル(23)が形成するチャンネル
幅GWの分だけ全体のチャンネル幅GWが増大し、単位面積
当りのドレイン電流IDS容量が増すので、パワーMOSFET
のオン抵抗RDS（on）を減少できる。The present application also includes P which forms the second channel region (19).
-Type diffusion region (21) is also provided with a N + type source region (22) and a source electrode on the surface, since used as also the region second cell (23), first the other cells (17) surrounding the channel 2 cells
( 23 ) The surrounding channels can also contribute to the MOSFET operation. Therefore, the entire channel width GW is increased by the amount of the channel width GW formed by the second cell ( 23 ), and the drain current I DS capacity per unit area is increased.
The on-resistance R DS (on) of can be reduced.
第５図に本願の第２の実施例を示す。本実施例は前記セ
ルの微細化を強力に押し進めたもので、チャンネル領域
（18）と第２のチャンネル領域（19）との重畳部分を残
したままセル(17)と第２のセル(23)を縮小したものであ
る。結果、セル(17)と第２のセル(23)のコーナー部分に
一定線幅の突出部（25）が残り、突出部（25）と突出部
（25）とが近接して対向するパターンとなる。チャンネ
ル領域（18）はゲート電極（15）をマスクとしたセルフ
アライン技術により形成される為、セル(17)の辺部の他
に突出部（25）の側面に沿っても形成され、突出部（2
5）先端でチャンネル領域（18）と第２のチャンネル領
域（19）とが重畳する。FIG. 5 shows a second embodiment of the present application. In this embodiment, the miniaturization of the cell is strongly promoted, and the cell ( 17 ) and the second cell ( 23 ) are left with the overlapping portion of the channel region (18) and the second channel region (19) left. ) Is a reduced version. As a result, a protrusion (25) having a constant line width remains at the corner portion of the cell ( 17 ) and the second cell ( 23 ), and the protrusion (25) and the protrusion (25) closely oppose each other. Become. Since the channel region (18) is formed by the self-alignment technique using the gate electrode (15) as a mask, it is formed not only on the side of the cell ( 17 ) but also along the side surface of the protrusion (25). (2
5) The channel region (18) and the second channel region (19) overlap at the tip.
斯る構成によれば、突出部（25）側部にもチャンネルが
形成されるので、第１の実施例より更にチャンネル幅GW
を増加できる。その為、より一層オン抵抗RDS（on）を
低減したパワーMOSFETを提供できる。尚、突出部（25）
はセル(17)又は第２のセル(23)どちらか一方だけに設け
ても良い。According to this structure, since the channel is formed on the side of the protrusion (25) as well, the channel width GW is further increased as compared with the first embodiment.
Can be increased. Therefore, it is possible to provide a power MOSFET with a further reduced on-resistance R DS (on). The protruding part (25)
May be provided in only one of the cell ( 17 ) and the second cell ( 23 ).
（ト）発明の効果 以上説明した如く、本発明によればチャンネル領域（1
8）のコーナー部（20）における電界集中を緩和してセ
ル(17)を微細化し、更には第２のセル(23)もMOSFET動作
に活用するので、チャンネル幅GWを増大し、オン抵抗R
DS（on）を大幅に低減したパワーMOSFETを提供できる利
点を有する。(G) Effect of the Invention As described above, according to the present invention, the channel region (1
The cell ( 17 ) is miniaturized by relaxing the electric field concentration in the corner part (20) of 8), and the second cell ( 23 ) is also used for MOSFET operation. Therefore, the channel width GW is increased and the on-resistance R
It has the advantage of providing a power MOSFET with significantly reduced DS (on).
第１図は本発明の第１の実施例を説明する為の平面図、
第２図は第１図のAA線断面図、第３図は第１図のBB線断
面図、第４図は拡大断面図、第５図は本発明の第２の実
施例を説明する為の平面図、第６図は従来例を説明する
為の平面図である。 （12）はＮ型エピタキシャル層、（15）はゲート電極、
(17)はゲートセル、（18）はチャンネル領域、（19）は
第２のチャンネル領域、（20）はコーナー部、(23)は第
２のセルである。FIG. 1 is a plan view for explaining the first embodiment of the present invention,
2 is a sectional view taken along line AA of FIG. 1, FIG. 3 is a sectional view taken along line BB of FIG. 1, FIG. 4 is an enlarged sectional view, and FIG. 5 is for explaining a second embodiment of the present invention. And FIG. 6 is a plan view for explaining a conventional example. (12) is an N-type epitaxial layer, (15) is a gate electrode,
( 17 ) is a gate cell, (18) is a channel region, (19) is a second channel region, (20) is a corner portion, and ( 23 ) is a second cell.
Claims (5)
MOSFETにおいて、前記セルのコーナー部で囲まれた領域
に前記セルのチャンネル領域のコーナー部分と重畳する
第２のチャンネル領域を設け、且つ前記第２のチャンネ
ル領域表面にもソース領域とソース電極を設けてこれを
第２のセルとしたことを特徴とするパワーMOSFET。1. A vertical power system in which a plurality of cells are arrayed vertically and horizontally.
In the MOSFET, a second channel region that overlaps with a corner portion of the channel region of the cell is provided in a region surrounded by the corner portion of the cell, and a source region and a source electrode are also provided on the surface of the second channel region. Power MOSFET characterized by making this the second cell.
請求項第１項に記載のパワーMOSFET。2. The power MOSFET according to claim 1, wherein the cell has a rectangular shape.
ャンネル領域形成と同時に作り込んだことを特徴とする
請求項第１項に記載のパワーMOSFET。3. The power MOSFET according to claim 1, wherein the second channel region is formed at the same time when the channel region of the cell is formed.
記第２のセル又はセルの方向へ突出する突出部を設け、
前記突出部に沿う様にチャンネル領域を設けたことを特
徴とする請求項第１項に記載のパワーMOSFET。4. A projecting portion projecting toward the second cell or the cell is provided at a corner portion of the cell or the second cell,
The power MOSFET according to claim 1, wherein a channel region is provided along the protrusion.
第２のセルのコーナー部の両方に対向するように設けた
ことを特徴とする請求項第４項に記載のパワーMOSFET。5. The power MOSFET according to claim 4, wherein the protruding portion is provided so as to face both the corner portion of the cell and the corner portion of the second cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63066327A JPH0687506B2 (en) | 1988-03-18 | 1988-03-18 | Power MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63066327A JPH0687506B2 (en) | 1988-03-18 | 1988-03-18 | Power MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01238173A JPH01238173A (en) | 1989-09-22 |
| JPH0687506B2 true JPH0687506B2 (en) | 1994-11-02 |
Family
ID=13312635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63066327A Expired - Lifetime JPH0687506B2 (en) | 1988-03-18 | 1988-03-18 | Power MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0687506B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0821714B2 (en) * | 1988-12-06 | 1996-03-04 | サンケン電気株式会社 | Insulated gate field effect transistor |
| JP3016298B2 (en) * | 1992-02-26 | 2000-03-06 | 日本電気株式会社 | Semiconductor device |
| JP3099917B2 (en) * | 1992-03-09 | 2000-10-16 | 日本電気株式会社 | Field effect transistor |
| JP2910489B2 (en) * | 1993-03-22 | 1999-06-23 | 日本電気株式会社 | Vertical double diffusion MOSFET |
| TW290735B (en) * | 1994-01-07 | 1996-11-11 | Fuji Electric Co Ltd | |
| JPH11204781A (en) | 1998-01-07 | 1999-07-30 | Nec Yamagata Ltd | Semiconductor device |
| EP1387408A1 (en) | 2002-06-12 | 2004-02-04 | Motorola, Inc. | Power semiconductor device and method of manufacturing the same |
| US8004049B2 (en) | 2004-08-31 | 2011-08-23 | Freescale Semiconductor, Inc. | Power semiconductor device |
| JP2011258635A (en) * | 2010-06-07 | 2011-12-22 | Mitsubishi Electric Corp | Semiconductor device |
| JP6687476B2 (en) * | 2016-07-25 | 2020-04-22 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
| CN117038708B (en) * | 2023-09-28 | 2024-01-23 | 绍兴中芯集成电路制造股份有限公司 | Trench type field effect transistor and preparation method thereof |
-
1988
- 1988-03-18 JP JP63066327A patent/JPH0687506B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01238173A (en) | 1989-09-22 |
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