JP2003101023A - Vertical insulated gate field-effect transistor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vertical insulated gate field-effect transistor which has superior characteristics. SOLUTION: An N-type drift region 13 is formed on an N<+> -type drain region 12 using an epitaxial growth method. P-type base regions 14 are formed in the surface region of the drift region 13, and further, N<+> -type source regions 5 are formed in the surface regions of the base regions 14. Narrow N<+> -type high concentration drift regions 17 are formed between the adjacent base regions 14. The impurity concentration of the high concentration drift region is higher than the impurity concentration of the drift region 13 but not lower than 1/5 of it on the channel region (ch) of the base region 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical insulated gate field effect transistor having good device characteristics and a method for manufacturing the same.

[0002]

2. Description of the Related Art A vertical insulated gate field effect transistor (Metal Insulated Semiconductor Field Effect transistor) is used as a power device for an industrial power switch or the like.
Transistor: MISFET) is used. The vertical MISFET is formed from the front surface side of the semiconductor substrate using the planar diffusion technique and has a main current path in the thickness direction of the substrate.

The vertical MISFET is provided, for example, in an N ⁺ -type drain region having a relatively high impurity concentration, an N-type drift region having a relatively low impurity concentration, and a drift region provided in the drain region. The semiconductor substrate is provided with a P-type base region provided and an N-type source region provided in the base region and having an impurity concentration higher than that of the drift region. A source electrode electrically connected to the base region and the source region is formed on one surface of the semiconductor substrate, and a drain electrode electrically connected to the drain region is formed on the other surface of the semiconductor substrate, In addition, a base region (channel region) between the source region and the drift region
A gate electrode is formed above the gate electrode via an insulating film.

The vertical MISFET having the above structure has an advantage that a relatively large current can flow because a current flows in the thickness direction of the substrate. But in general,
There is a problem that it is difficult to obtain a sufficiently low operating resistance (ON resistance).

Vertical MISFET with reduced operating resistance
As an example, a drift region sandwiched between adjacent base regions (channel regions) has an increased impurity concentration in the surface region, and an N-type drift region having a relatively high concentration is provided. Here, in the case of a MISFET having a breakdown voltage of 50 to 60 V, the impurity concentration of the drift region having a relatively high concentration is set to be about twice as high as that of the drift layer, but lower than that of the base channel region by one digit or more. There is. By providing the drift region having a relatively high concentration adjacent to the channel region, the resistance of the main current path is reduced and the operating resistance is reduced. Such a vertical MISFET is disclosed in, for example, Japanese Patent Publication No. 3-70387.

[0006]

However, although the operating resistance can be reduced by increasing the impurity concentration in the surface region of the drift region as described above, the impurity concentration is excessively increased or the depth thereof is increased. If the depth is too deep, the breakdown voltage of the device will be reduced. Therefore, normally, the impurity concentration of the drift region having a relatively high concentration must be set to about twice the drift concentration of the drift region and about 1/20 of the impurity concentration of the base channel region as described above. As described above, in the conventional vertical MISFET including the drift region having a relatively high concentration, it is difficult to sufficiently increase the impurity concentration in the region having a relatively high concentration to obtain a sufficiently low operating resistance. It was

In view of the above circumstances, it is an object of the present invention to provide a vertical insulated gate field effect transistor having good device characteristics and a method for manufacturing the same. Also,
An object of the present invention is to provide a vertical insulated gate field effect transistor having a low operating resistance and a method for manufacturing the same.

[0008]

In order to achieve the above object, a vertical insulated gate field effect transistor according to a first aspect of the present invention is provided with a drain region of a first conductivity type and on the drain region. A drift region of a first conductivity type having an impurity concentration lower than that of the drain region, a plurality of second conductivity type base regions provided in the drift region, and a plurality of second conductivity type base regions provided in the base region, Is provided in a surface region of the drift region sandwiched between the first conductivity type source region having a high impurity concentration and the base region adjacent to each other, and the impurity concentration is higher than that of the drift region, and the base region And a high-concentration drift region having an impurity concentration substantially equal to or higher than the order.

In order to achieve the above object, a vertical insulated gate field effect transistor according to a second aspect of the present invention is provided on a drain region of a first conductivity type and on the drain region. Is provided in the first conductivity type drift region having a low impurity concentration, a plurality of second conductivity type base regions provided in the drift region, and a channel region is formed when a gate voltage is applied, and in the base region. Provided in a surface region of the drift region sandwiched between a first conductivity type source region having an impurity concentration higher than that of the drift region and the base region adjacent to each other, and having an impurity concentration higher than that of the drift region, And,
And a high-concentration drift region having an impurity concentration substantially equal to or higher than that of the channel region.

In the above structure, it is desirable that the high concentration drift region has an impurity concentration that is ⅕ or more of the impurity concentration of the channel region.

In the above structure, it is preferable that the high concentration drift region is provided in contact with the drift regions on both sides.

In the above structure, the width of the high concentration drift region is, for example, 1/8 of the width of the base region.
It is set below. Further, the depth of the high concentration drift region is, for example, 0.
It is set in the range of 9 to 1.4. The width of the high concentration drift region is set to, for example, 1 / 2.5 or less of the depth of the base region. The width of the high concentration drift region is, for example, 0.5 μm or less.

In the above structure, a stripe-shaped gate electrode, which is provided above the channel region and applies a gate voltage to the channel region, is provided, and the width of the gate electrode is 5 times the depth of the base region. It may be set to / 3 or less.

In order to achieve the above object, a method of manufacturing a vertical insulated gate field effect transistor according to a third aspect of the present invention is provided with a first conductivity type drain region, the drain region being provided on the drain region. A first conductivity type drift region having an impurity concentration lower than that of the drain region, a second conductivity type base region provided in the drift region, and an impurity concentration lower than that of the drift region provided in the base region. A method of manufacturing a high-conductivity-type source region and an insulated gate field-effect transistor, wherein impurities of the same conductivity type are selectively introduced into a first-conductivity-type semiconductor region forming the drift region. A high-concentration drift region forming step of forming a high-concentration drift region, and introducing a second conductivity type impurity between the high-concentration drift regions adjacent to each other, And forming a band, and characterized in that.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A vertical insulated gate field effect transistor (MetalInsulated S) according to an embodiment of the present invention.
emiconductor field effect transistor: MISFE
T) will be described below with reference to the drawings.

FIG. 1 shows a sectional structure of a vertical MISFET 11 according to an embodiment of the present invention. As shown in FIG. 1, the MISFET 11 has a drain region 12, a drift region 13, a base region 14, a source region 15,
And a semiconductor substrate 16 having.

The drain region 12 is composed of an N ⁺ type semiconductor region in which impurities are introduced at a relatively high concentration. The drain region 12 is, for example, 1 × 10 ¹⁹ cm
The impurity concentration is set to about ^-3 . At this time, the resistivity (or conductivity) of the drain region 12 is 5.2Ω.
・ It is about cm.

The drift region 13 is an N-type semiconductor region formed on the drain region 12 by epitaxial growth and having impurities introduced at a relatively low concentration. The drift region 13 has, for example, a depth (thickness) of about 4.3 μm and an impurity concentration of about 6.2 × 10 ¹⁵ cm ⁻³ . At this time, the resistivity (or conductivity) of the drift region 13 is about 0.8 Ω · cm.

A plurality of base regions 14 are formed in the surface region of the drift region 13. The base region 14 is composed of a P-type semiconductor region formed by introducing P-type impurities. Base region 14 is formed of, for example, of about 1.5μm depth, it is set to an impurity concentration of about 4 × ^{10 1} 7 ^{cm -3.} At this time, the minimum value of the resistivity (or conductivity) of the base region 14 is about 0.2 Ω · cm. Here, the depth of the base region 14 refers to the distance from the deepest position of the PN junction formed at the interface between the base region 14 and the drift region 13 to the exposed surface of the base region 14.

In the surface region of the base region 14, a source region 15 made of an N ⁺ type semiconductor region having a relatively high impurity concentration is formed. Two source regions 15 are formed in each base region 14 so as to be separated from each other. The source region 15 is formed to have a depth of, for example, about 0.25 μm, and has an impurity concentration of, for example, about 1 × 10 ²⁰ cm ⁻³ . At this time, the sheet resistance of the source region 15 is
It is about 60Ω / □.

Here, between the adjacent base regions 14, a narrow N ⁺ -type high-concentration drift region 17 in which N-type impurities are introduced into the drift region 13 is formed.
It is arranged adjacent to No. 4. That is, the surface region of the N-type drift region 13 includes the plurality of base regions 14 and the N ⁺ -type high-concentration drift region 17 between the base regions 14.
And are covered by.

The N ⁺ type high concentration drift region 17 is formed in the N type drift region 13 by ion implantation. The impurity concentration of the high-concentration drift region 17 is set to be about 20 times higher than that of the drift region 13, and is a portion having the highest impurity concentration, for example, 1.7 × 10 ¹⁷
The impurity concentration is about cm ⁻³ . That is, the impurity concentration of the high concentration drift region 17 is
The impurity concentration is about the same as or higher than that of
It is set to be 5 or more. Here, “equal to or higher than the same order” means 1/10 times or higher. At this time, the resistivity of the high concentration drift region 17 is about 72 mΩ · cm in the region where the impurity concentration is low.

FIG. 2 shows a top view of the semiconductor substrate 16 which constitutes the MISFET 11. As shown in FIG. 2, on the surface of the semiconductor substrate 16, P-type base regions 14 are arranged in stripes at substantially equal intervals. The width of the base region 14 is, for example, about 4 μm. Where base region 1
The width of 4 means the widest width in the lateral direction on the exposed surface of the base region 14.

In each base region 14, an N ⁺ type source region 15 is formed in a stripe shape substantially parallel to the base region 14. The source region 15 has, for example, 0.8 μm
It is formed with a certain width. The source region 15 is
It may be provided in a dot shape.

The N ⁺ type high-concentration drift region 17 between the base regions 14 is formed in a stripe shape substantially parallel to the base region 14. The high-concentration drift region 17 is provided with a width of, for example, 0.5 μm or less, for example, about 0.3 μm and a narrow width. The width of the high concentration drift region 17 is
The width is set to be 1: 8 with respect to the width of the base region 14 and is 1 / 2.5 or less of the depth of the base region 14. Here, the width of the high-concentration drift region 17 refers to the widest lateral width of the portion that is sandwiched between the base regions 14 and exposed to the main surface of the semiconductor substrate 16.

Returning to FIG. 1, the depth of the high concentration drift layer is
The width is set to be 0.9 times to 1.4 times the width of the base region 14, for example, 3.6 μm to 5.6 μm. Here, the depth of the high concentration drift region 17 refers to the distance from the position where the impurity concentration is increased by 20% with respect to the impurity concentration of the drift region 13 to the main surface of the semiconductor substrate 16.

In forming the base region 14 and the high-concentration drift region 17, the lateral diffusion of the base region 14 cancels out the lateral diffusion of the N-type diffusion layer forming the high-concentration drift region 17. . As a result, a high-concentration drift region 17 having a narrow width and a channel region (ch) sufficiently shorter than the depth of the base region 14 are formed.

Further, since the base region 14 and the high-concentration drift region 17 have a two-dimensional spread in the depth direction lateral direction and the oblique direction, the impurities in the both regions 14 and 17 cancel each other out. As a result, the high concentration drift region 1
The impurity distribution in the vertical direction of 7 shows a sufficiently gentle impurity concentration distribution as compared with the Gaussian distribution obtained by impurity diffusion of a single substance.

Returning to FIG. 1, a drain electrode 18 made of aluminum or the like is provided on the exposed surface of the drain region 12. The drain electrode 18 is electrically connected to the drain region 12.

Two source regions 15 in the base region 14
A source electrode 19 is provided on a part of each of the above and the base region 14 sandwiched between the two source regions 15. The source electrode 19 is made of aluminum or the like,
It is electrically connected to the two source regions 15.

One source region 15 in the base region 14
Above, a part of one source region 15 of another base region 14 adjacent thereto, and a high-concentration drift region 17 sandwiched between the two base regions 14, a silicon oxide film, etc. A gate electrode 21 is provided via the insulating film 20 of FIG. The gate electrode 21 is made of polysilicon or the like having impurities introduced therein. The width of the gate electrode 21 is set to be 5/3 or less of the depth of the base region 14, and in this case, it is 2.5 μm or less.

The insulating film 20 under the gate electrode 21 functions as a gate insulating film. When the gate voltage is applied,
In the base region 14 located below the gate electrode 21,
A channel region (ch) that connects the source region 15 and the drift region 13 is formed. The current flowing from the source electrode 19 to the drift region 13 through the channel region (ch) flows to the drain region 12.

Here, the high concentration drift region 17 is connected to the source region 15 via the channel region (ch).
Is. The high-concentration drift region 17 is, as described above,
The impurity concentration is set to about 20 times higher than that of the drift region 13. That is, the impurity concentration is approximately equal to or higher than the impurity concentration of the base region 14 including the channel region (ch), and particularly 1/5 or higher. By experiment,
The gate electrode 21 in which the high concentration drift region 17 does not exist
The resistance per unit area of the main current path connecting the source region 15 to the drain region 12 is significantly reduced as compared with the MISFET having a large width.
It has been found that a low operating resistance (ON resistance) can be obtained.

The high-concentration drift region 17 is provided with a width of 0.5 μm or less by the ion implantation technique and the offset due to the above-described lateral expansion of the base region 14. By being provided in such a narrow width, a decrease in breakdown voltage in the high-conductivity high-concentration drift region 17 is compensated. Further, the gate electrodes 21 are opposed to each other via the narrow high-concentration drift region 17, the gate-drain capacitance is substantially small, and high-speed switching characteristics can be obtained.

Furthermore, when a relatively large current is applied with a high drain voltage applied, a narrow N ⁺
An appropriate JFET formed by the high-concentration drift region 17 and the P-type base regions 14 adjacent to both sides thereof
(Junction FET) effect is obtained and excessive current is suppressed. As a result, element breakdown is less likely to occur. Also,
The high-concentration drift region 17 disposed immediately below the gate electrode 21 has a so-called resurf electric field relaxation function in the vertical direction with the base region 14, and can maintain a high breakdown voltage.

Further, in the MISFET 11 of FIG. 1, diffusion of the high concentration drift region 17 in the horizontal and vertical directions,
The impurity distribution is two-dimensionally offset from the lateral and vertical diffusion of the base region 14, and the concentration of the base region 14 is set to be significantly higher than the concentration of the channel region. Further, the width of the high concentration drift region 17 is extremely narrow. Therefore, a surge voltage is applied,
Even when the avalanche breakdown of the PN junction occurs, the breakdown current has a relatively small component flowing under the source region 15 and flows directly from the source electrode 19 in the vertical direction of the MISFET 11. As a result, it is possible to favorably prevent the parasitic transistor operation from occurring even without forming a deep base structure (a structure in which the center side of the base region 14 is selectively formed deep).

Hereinafter, a method of manufacturing the MISFET 11 having the above structure will be described with reference to the drawings. First, N ⁺ which constitutes the drain region 12 and has a relatively high impurity concentration.
A mold semiconductor substrate 16 is prepared. On the semiconductor substrate 16, the N-type semiconductor layer 22 forming the drift region 13 and having a relatively low impurity concentration is formed by the epitaxial growth method. Next, heat treatment is applied to the upper surface of the N-type semiconductor layer 22 to form a thin insulating film (silicon oxide film) 23 as shown in FIG.

Next, a polysilicon film is formed on the upper surface of the insulating film 23 by the chemical vapor deposition method. Impurities are introduced into the formed polysilicon film to impart conductivity. Then, the polysilicon film is etched into a predetermined pattern by using a photolithography technique to form the gate electrode 21. Subsequently, N-type impurities are selectively ion-implanted into the N-type semiconductor layer 22 through the gate electrode 21 and the insulating film 23. As a result, as shown in FIG.
An N ⁺ type high concentration drift region 17 having a relatively high impurity concentration is formed.

Subsequently, P-type impurities and N-type impurities are sequentially ion-implanted into the surface region of the N-type semiconductor layer 22 through the insulating film 23 between the adjacent gate electrodes 21 and diffused. . As a result, as shown in FIG. 4C, the P-type base region 1 inverted to the surface region of the N-type semiconductor layer 22 is formed.
4 is formed, and then an N ⁺ type source region 15 is formed in the surface region of the formed base region 14.

Here, the gate electrode 2 which is a mask for introducing a P-type impurity for forming the adjacent base region 14 is formed.
1 has a sufficiently narrow width that the adjacent base regions 14
It is smaller than the lateral diffusion of the P-type impurity from. However, before the impurity diffusion step, there is a step of forming the N ⁺ -type high-concentration drift region 17, and the presence of the high-concentration drift region 17 prevents the adjacent P-type base regions 14 from being bonded to each other.

Subsequently, an interlayer insulating film (silicon oxide film) is formed so as to cover the base region 14, the polysilicon film and the like. Further, the interlayer insulating film and the insulating film 23 are etched by the photolithography technique to form the base region 1
4 and the source region 15 are formed as openings 24.

Subsequently, a conductor layer (source electrode 19) made of aluminum or the like is formed so as to fill the opening 24 by sputtering or the like. Further, a conductor layer (drain electrode 18) made of titanium, nickel or the like connected to the drain region 12 is formed. As described above, M according to the present embodiment
ISFET 11 is formed.

As described above, in the present invention of the above-described embodiment, the drift region 13 sandwiched between the base regions 14 is provided.
High concentration drift region 1 with high impurity concentration in the surface region of
7 is provided. The high-concentration drift region 17 is adjacent to the base region 14 (channel region) below the gate electrode 21 and constitutes a part of a main current path connecting the source region 15 to the drain region 12. High concentration drift region 17
As a result, the resistance of the main current path is reduced, and a low operating resistance of the device is obtained.

Further, the high concentration drift region 17 has 0.5
It is formed with a narrow width of not more than μm. This makes it possible to increase the conductivity of the high concentration drift region 17 while preventing the breakdown voltage of the device from decreasing. Therefore, the impurity concentration of the high-concentration drift region 17 is set to be higher than that of the drift region 13 and substantially equal to or higher than the order of the base channel region, and in particular, set to an impurity concentration of ⅕ or more thereof to obtain low operating resistance. be able to.

Further, when viewed from the manufacturing side of the MISFET 11, the high-concentration drift region 17 is arranged narrowly between the base regions 14, the spacing between the base regions 14 is substantially narrowed, and high mounting density is achieved. Is obtained.

For example, when a device as shown in FIG. 5 is constructed by using a drift region having a relatively high concentration of about 1.3 × 10 ¹⁶ cm ^{−3, a} drift region having a relatively high concentration is formed. The width needs to be about 3 μm. The width of the high concentration drift region 17 in the above embodiment is 0.3 μm.
It can be seen that it can be reduced to about 1/10 and can be reduced to about 1/10. Therefore, it is possible to obtain a high packaging density while achieving the same or lower operating resistance.

Further, according to the structure of the present embodiment, unlike the trench type vertical MISFET, a low operating resistance similar to that of the trench type can be obtained while having a simple structure. In this way, MIS with good device characteristics such as operating resistance
It is possible to provide the FET 11 with high yield by using equipment with high productivity and low cost.

Further, when mounted on an IC such as a BCD, a process having a high degree of integration with a process of forming other elements and a high productivity can be constructed as compared with the trench type MISFET.

The present invention is not limited to the above embodiment,
Various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

In the above embodiment, the high concentration drift region 17 is formed after forming the polysilicon film forming the gate electrode 21. However, the high concentration drift region 17
After forming, the gate electrode 21 and the like may be formed.

The high-concentration drift region 17 may be formed by forming the base region 14 and then introducing N-type impurities by the high-acceleration ion implantation method. Further, both the base region 14 and the high concentration drift region 17 may be formed by the high acceleration ion implantation method.

At this time, the impurity concentration profile in the depth direction of the high concentration drift region 17 can be controlled by further changing the acceleration voltage of ion implantation stepwise or continuously.

Further, in the contact region of the base region 14 with the source electrode 19, a region having a high impurity concentration can be selectively formed to reduce the contact resistance.

In the above embodiment, the N type semiconductor substrate 1 is used.
The MISFET 11 is formed in No. 6. But,
However, the configuration is not limited to this, and a P-type semiconductor substrate 16 may be used to form a reverse conductivity type device.

In the above embodiment, the base region 1
4 and the high-concentration drift region 17 adjacent thereto were formed in a stripe shape. However, the shape is not limited to this, and other shapes such as a loop shape may be used.

In the above embodiment, the present invention is based on the vertical MI.
It is applied to the SFET 11. However, the present invention is not limited to this, and can also be applied to an insulated gate bipolar transistor (IGBT) or the like.

[0057]

As described above, according to the present invention,
An insulated gate field effect transistor having good device characteristics is provided.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an insulated gate field effect transistor according to an embodiment of the present invention.

FIG. 2 is a top view of the semiconductor substrate shown in FIG.

FIG. 3 is a diagram showing a manufacturing process of the MISFET according to the embodiment of the present invention.

FIG. 4 is a diagram showing a manufacturing process of the MISFET according to the embodiment of the present invention.

FIG. 5 is a diagram showing a comparative example of MISFETs.

[Explanation of symbols]

11 MISFET 12 drain region 13 Drift region 14 Base area 15 Source area 16 Semiconductor substrate 17 High concentration drift region 18 Drain electrode 19 Source electrode 20 insulating film 21 Gate electrode

Claims (10)

[Claims] 1. A drain region of a first conductivity type, a drift region of a first conductivity type provided on the drain region and having an impurity concentration lower than that of the drain region, and a plurality of drift regions provided in the drift region. A second conductivity type base region, a first conductivity type source region provided in the base region and having a higher impurity concentration than the drift region, and a surface of the drift region sandwiched between the base regions adjacent to each other. A high-concentration drift region that is provided in the region and has a higher impurity concentration than the drift region and has an impurity concentration that is substantially the same as or higher than that of the base region. Gate type field effect transistor. 2. A drain region of a first conductivity type, a drift region of a first conductivity type, which is provided on the drain region and has an impurity concentration lower than that of the drain region, and a plurality of drift regions are provided in the drift region. A second conductive type base region in which a channel region is formed when a voltage is applied; a first conductive type source region provided in the base region and having an impurity concentration higher than that of the drift region; A high-concentration drift region which is provided in a surface region of the drift region, which is sandwiched between regions, has a higher impurity concentration than the drift region, and has an impurity concentration of the same order as or higher than that of the channel region, A vertical insulated gate field effect transistor, comprising: 3. The high-concentration drift region has an impurity concentration that is ⅕ or more of the impurity concentration of the channel region.
The vertical insulated gate field effect transistor according to claim 2, wherein 4. The vertical insulated gate field effect according to claim 1, wherein the high concentration drift region is provided in contact with the drift regions on both sides. Transistor. 5. The width of the high-concentration drift region is set to be ⅛ or less of the width of the base region, according to any one of claims 1 to 4. Vertical insulated gate field effect transistor. 6. The depth of the high concentration drift region is set within a range of 0.9 to 1.4 with respect to the width of the base region. The vertical insulated gate field effect transistor according to claim 1. 7. The width of the high-concentration drift region is set to be 1 / 2.5 or less of the depth of the base region, according to claim 1. Vertical insulated gate field effect transistor. 8. The width of the high concentration drift region is 0.5 μm.
The vertical insulated gate field effect transistor according to any one of claims 1 to 7, wherein the vertical insulated gate field effect transistor is m or less. 9. A stripe-shaped gate electrode, which is provided above the channel region and applies a gate voltage to the channel region, wherein the width of the gate electrode is 5/3 of the depth of the base region. The vertical insulated gate field effect transistor according to any one of claims 1 to 8, which is set as follows. 10. A drain region of a first conductivity type, a drift region of a first conductivity type provided on the drain region and having an impurity concentration lower than that of the drain region, and a second region provided in the drift region. A method of manufacturing an insulated gate field effect transistor, comprising: a conductive type base region; a first conductive type source region which is provided in the base region and has an impurity concentration higher than that of the drift region; Between the high-concentration drift region forming step of forming a high-concentration drift region by selectively introducing impurities of the same conductivity type into the first-conductivity-type semiconductor region to be formed, and between the high-concentration drift regions adjacent to each other. And a step of forming a base region by introducing an impurity of a second conductivity type, the method for manufacturing a vertical insulated gate field effect transistor.