JPH065867A - Semiconductor device and its production - Google Patents

Abstract

PURPOSE:To provide a small and low-consumption power MOS transistor without deteriorating the breakdown strength. CONSTITUTION:A plurality of well diffused layers 101 are formed on the semiconductor substrate for a power MOS transistor 100, a source area 104 is formed in the well diffused layer 101 and a semiconductor substrate other than the well diffused layer 101 is formed as a drain substrate layer 103. High concentration impurities are introduced at the top of the drain substrate layer 103 sandwiched by the plurality of well diffused layers 101 from the substrate and a high concentration impurity introducing part 120 is formed. The high concentration impurity introducing part 120 has a larger cross-section in the horizontal direction at the bottom and the higher concentration impurities are introduced at the top. The concentration profile of the high concentration impurity introducing part 120 is formed by two steps and implantation is performed twice by different implantation depths so as to form the profile.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to semiconductor technology and further to M technology.
The present invention relates to a technique particularly effective when applied to a vertical power transistor using an OSFET, and relates to a semiconductor device useful for a vertical power MOS transistor, which is miniaturized and has low power consumption.

[0002]

2. Description of the Related Art A vertical power MOS transistor used for switching a power source or the like and having a withstand voltage of about 300 V to 600 V is known (for example, Electronic Information Communication Handbook 80).
7). In recent years, vertical power MOS transistors can be downsized and have low power consumption while maintaining a sufficient breakdown voltage structure. By the way, in order to miniaturize the power MOS transistor, when forming a large number of well diffusion layers in which a channel region and a source region are formed, the distance between the well diffusion layers may be narrowed. Further, when the well diffusion layer is narrowed in this way, the source region and the base region sandwiching the drain are also narrowed, and the depletion layer formed between them during transistor conduction is likely to be pinched off. The electric field strength is relaxed and the breakdown voltage is improved. Furthermore, since the distance between the upper ends of the drain substrate layers is narrowed, the oxide film capacitance (feedback capacitance) between the drains as viewed from the gate is also reduced. However, it is known that when the size is reduced as described above, on-resistance increases on the other hand. This is because the area of the drain substrate layer immediately below the gate electrode, which is sandwiched between the well diffusion layers, is reduced, and the resistance value in the drain substrate portion is increased. As a result, the power consumption increases.

In order to reduce the resistance of the drain region while reducing the size of the transistor, as shown in FIG. 12, the upper side 203a of the drain substrate layer 203 surrounded by the well diffusion layers 201, 201 ,. U.S. Pat. No. 4,376,286 proposes a vertical power MOS transistor in which impurities are introduced into 203a, ... In a high concentration to suppress the increase of the on-resistance due to the reduction in size. This proposal proposes a well diffusion layer 201, in a power MOS transistor having a drain-source breakdown voltage of 300 V or more.
The drain substrate layers 203a, 203 sandwiched between 201, ...
In view of the fact that the on-resistance of 03a, ... Has the greatest effect on the on-resistance of the entire element that constitutes the power MOS transistor (the resistance value in this region is about half of the total resistance value). , To reduce the on-resistance in this area,
Impurities were introduced into the surface at a high concentration and shallowly under the condition that the breakdown voltage was not lowered (FIG. 13).
Shows the impurity concentration distribution along the line XX in FIG.

[0004]

However, when the proposed vertical power MOS transistor structure is adopted to reduce the on-resistance, the following problems are revealed by the present inventors. Was done. That is, the distance between the well diffusion layers 201, 201, ... Is narrowed, and the upper portions 203a, 203a, ... Of the drain substrate layer formed between the well diffusion layers 201, 201 ,.
When an impurity is introduced into the substrate, the depletion layer is less likely to spread in the drain substrate portion where the impurity is introduced when a voltage is applied, and as a result, the breakdown voltage in this region is likely to decrease. Therefore, when the above-mentioned method is adopted, the concentration and depth of the impurities introduced into the upper part of the drain substrate layer are adjusted to other parameters such as the width of the formed channel layer and the installation interval of the well diffusion layers. You have to select the optimum value. That is, by selecting the above parameters, the power MOS transistor formed according to these parameters is optimized so that the characteristics such as withstand voltage, on-resistance, and feedback capacitance (parasitic capacitance) between the gate electrode and the drain are optimized. It is necessary to determine the concentration and depth of impurities introduced into the substrate layer. Therefore, in order to determine the concentration and depth of impurities introduced into the drain substrate layer, many characteristic items (breakdown voltage, ON resistance, capacitance) must be evaluated for each transistor obtained by the combination of each parameter. Not
It has been difficult to determine the concentration and depth of the impurities in order to obtain the optimum characteristics.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a power MOS transistor which is small in size and low in power consumption without degrading withstand voltage characteristics. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in the semiconductor device according to claim 1, at least two well diffusion layers of the second conductivity type are formed on the semiconductor substrate of the first conductivity type at a predetermined interval, and the well diffusion layer and the channel diffusion layer. A source region of the first conductivity type formed in the layer, a semiconductor substrate portion other than the well diffusion layer is formed as a drain region, and the semiconductor substrate portion sandwiched by the at least two or more well diffusion layers is , A vertical power MO formed by introducing impurities into the first conductivity type in a concentration higher than that of the first conductivity type and increasing the horizontal cross-sectional area as the depth increases.
In the S transistor, impurities are introduced into the semiconductor substrate portion sandwiched by the well diffusion layers so that the concentration becomes higher as the depth becomes shallower. According to the method of manufacturing a semiconductor device of claim 3, the introduction of impurities into the semiconductor substrate portion sandwiched by the two or more well diffusion layers according to claim 1 is performed at least twice with different implantation depths. It is done in the process.

[0007]

According to the invention of claim 1, the installation interval of the well diffusion layer in which the channel region and the source region are formed is narrowed,
Since the upper end of the semiconductor substrate portion (drain substrate layer) is narrowed, the impurity concentration of the semiconductor substrate portion further sandwiched by the well diffusion layers is formed so as to increase as the depth becomes shallower. When conducting,
The depletion layer formed on the semiconductor substrate becomes uniform,
The electric field concentration is prevented at this portion, and the breakdown voltage is prevented from being lowered. Further, according to the third aspect of the present invention, since the impurities are introduced into the semiconductor substrate portion sandwiched between the well regions by two times of impurity implantation with different depths, the mode of the impurity introduction pattern is diversified. It becomes easy to select design parameters for adjusting the withstand voltage, feedback capacitance, and on-resistance value of the transistor to the optimum values.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
Will be described in detail with reference to. FIG. 1 is a vertical sectional view of an n-channel vertical power MOS transistor 100 of this embodiment. In the case of the n-channel power MOS transistor 100 shown in this embodiment, the impurity concentration of the drain substrate layer 103 in which the drain region is formed is 1 × 10 ¹⁴ cm ^{−3 -4.}
× 10 ¹⁴ cm ^-3 and drain withstand voltage of 300V-60
It is formed so as to secure about 0V.

Hereinafter, this power MOS transistor 10 will be described.
The structure of 0 will be described. As shown in FIG. 1, the power MOS transistor 100 is formed on an n-type semiconductor substrate 101, and a drain substrate layer 103 into which an n-type impurity is introduced is formed on the upper side of the substrate 109, while On the lower side of the substrate 109, a back electrode 108 for drain is formed.
Are formed. In addition, the substrate layer 103 has a large number of p
, And channel diffusion layers 101 ', 101', ... are formed at a predetermined interval (LW). The p well diffusion layers 101, 101, ...
The channel diffusion layers 101 ′, 101 ′, ... Have n-type high-concentration impurity regions (source regions) 1 on the substrate surface side.
04, 104 ... Are formed. When the transistor operates, a channel is formed on the surface of the channel diffusion layers 101 ', 101' ... Under the gate electrode 102.

The p-well diffusion layers 101, 101,
, And the n-type drain substrate layer 103 sandwiched between the channel diffusion layers 101 ′, 101 ′, ... An n-type high-concentration impurity introduction part 120 is formed. The high-concentration impurity introduction portion 120 has a shape in which the horizontal cross-sectional area increases as the depth thereof increases, and the concentration of impurities (for example, phosphorus) introduced is increased as the depth thereof decreases. ing. That is, the n-type high-concentration impurity introducing portion 120 is formed by, for example, two times of ion implantation (implantation) having different implantation depths, as will be described later, and therefore the concentration profile thereof is as shown in FIG.
As shown in (2), there are two steps (areas A and B). Then, the region A on the upper layer side (hereinafter referred to as the first high-concentration layer (first layer) 1
20A) impurity concentration (at least maximum value)
Is a region B on the lower layer side (hereinafter, referred to as a second high concentration layer (second layer) 1
The impurity (for example, phosphorus) is introduced so as to have a higher concentration than the impurity concentration (referred to as 20B) (its maximum value).

Further, gate electrodes 102, 102 ... Are formed above the high-concentration impurity introduction portion 120 via a silicon oxide film (gate oxide film) 106. As will be described later, the gate electrodes 102, 102 are formed. The well diffusion layers 101, 101 ... And the channel diffusion layer 10 are arranged at the installation intervals.
The widths of 1 ', 101', ... Are determined. Further, the drain width LW is determined by adjusting the widths of the gate electrodes 102, 102 ... (FIG. 2).

The vertical power MOS transistor 100 having the above-described structure is formed according to the following manufacturing process. First, an impurity (for example, phosphorus) is implanted / diffused in a region where a power MOS transistor is formed to form an n-type high-concentration impurity introduction portion 120 in the surface layer (FIG. 3). Implantation of impurities (phosphorus) at this time is performed at a concentration of about 5 × 10 ¹⁵ cm ⁻³ and an implantation depth of about 4 to 5 μm (solid line I in FIG. 9). Next, the mask material 131 formed on the surface of the drain substrate layer 103 is patterned according to the shape of the diffusion layer to form a reference p-well diffusion layer (for example, the diffusion layer 101a in FIG. 1), and then a p-type impurity ( For example, boron implantation is performed (dashed line II in FIG. 9). Then, the p-type impurity is implanted again into the p-type diffusion layer 101a (dashed line IV in FIG. 9) to form a channel region 101 '(FIG. 4). Further, a mask material 132 is formed on the diffusion layer 101a, and the drain substrate layer 103 other than the diffusion layer 101a is formed.
Then, the n-type impurities (phosphorus) are introduced by being overlapped by implantation and diffusion to form a first high-concentration layer on the upper half side of the high-concentration impurity introduction part 120. This first high concentration layer 120A
The lower layer becomes the second high-concentration layer 120B (FIG. 5).
The impurity (phosphorus) implantation is performed at a peak concentration of about 3 × 10 ¹⁵ cm ⁻³ and a depth of about 2 to 3 μm (see FIG. 9, two-dot chain line III). A gate oxide film 106 is formed on the surface of the drain substrate layer 103 on which the n-type or p-type impurity diffusion layer is formed by an oxidation process, and polycrystalline silicon (102) is formed on the gate oxide film 106.
Are deposited and patterned to form the gate electrodes 102, 102, ... With a gate width LD of 5 to 8 μm.
m, and the distance LS between the gate electrodes is 15 to 24 μm (FIG. 6). Next, using the formed gate electrodes 102, 102 ... As a mask, other n well diffusion layers 101b, 101b, ... Are formed by self-alignment at a predetermined position on the surface of the n-type semiconductor substrate 101 by implantation / diffusion. In this case, the introduction of impurities (boron) is performed by overlapping according to the broken line II and the chain line IV in FIG. In this way, the p-well diffusion layers 101, 101 and the channel diffusion layers 101 ', 101', ... Are formed on the drain substrate layer 103. Further, with respect to the diffusion layers 101, 101, 101 ', 101', the p-well diffusion layers 101, 101 ... And by the implantation / diffusion of n-type impurities using the gate electrodes 102, 102 ,. Channel diffusion layer 10
1 ', 101', ... Forming n-type impurity diffusion layers (source regions) 104, 104 ...
A basic structure of a vertical power MOS transistor is obtained (FIG. 7). After that, an interlayer insulating film (for example, SiO ₂ ) 107 is deposited, and an Al lead electrode through hole 1 is deposited thereon.
11, 111 ... (Only shown for the source electrode) are provided corresponding to the source region and the region where the gate electrode is formed, Al wiring 112 is vapor-deposited, and this is patterned to form respective wiring patterns ( (Figure 8). Then, after Al—Si alloying is performed by heat treatment, a surface protective film 113 is formed, a through hole (not shown) for a bonding pad is formed, and finally, a back electrode 108 is deposited on the back surface of the semiconductor substrate 109. To obtain the power MOS transistor structure shown in FIG.

In the power MOS transistor 100 thus obtained, the p-well diffusion layers 101, 101, ... Of the drain substrate layer 103 and the channel diffusion layer 10 are formed.
A high-concentration impurity introducing portion 120 is formed in a portion surrounded by 1 ', 101', ...
Since the impurity concentration of the first high concentration layer 120A is formed higher (the impurity concentration introduced into the first high concentration layer 120A is higher than the concentration of the second high concentration layer 120B), the transistor is turned on. At times, the depletion layer generated in the high-concentration impurity introducing portion 120 can be made uniform in the introducing portion 120, and electric field concentration can be avoided. In addition, since the manner of introducing impurities in the high-concentration impurity introducing portion 120 is diversified, the impurity concentration / diffusion layer depth, gate electrode width, diffusion layer size, etc. of each component of other transistors can be varied. Even after the manufacturing parameters have been determined to some extent, the characteristics of the power MOS transistor are optimized, that is, the on resistance and the breakdown voltage are prevented from increasing with miniaturization at the same time. The impurity concentrations of the first and second high-concentration layers can be determined.

Actually, when the respective components of the power MOS transistor having the above-mentioned structure and the parameters used for the design thereof were selected as follows, the characteristics were remarkably improved as compared with the conventional power MOS transistor. The details will be described below.

The parameters of each part of the n-channel power MOS transistor (drain breakdown voltage = 300 to 600 V) of this embodiment are determined as follows. (1) Impurity concentration of drain substrate layer = 1 × 10 ¹⁴ cm ⁻³
4 × 10 ¹⁴ cm ⁻³ (2) Impurity concentration of the first high concentration layer 120A = 6 × 10 ¹⁵
cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ ; depth = about 2 to 3 μm (see FIG.
Range indicated by A) (3) Impurity concentration of the second high concentration layer 120B = 1 × 10 ¹⁵
cm ^{−3 to} 5 × 10 ¹⁵ cm ⁻³ ; depth = about 2 to 3 μm (FIG. 10)
(A range indicated by B) (4) Gate widths of gate electrodes 102, 102 LD = 5 to 5
8 μm; Distance between gate electrodes LS = 15 to 24 μm (5) Distance between mutual p well diffusion layers LW = 1.5 to 2.
5 μm (6) Vertical and horizontal width of p well diffusion layer (channel layer) LC =
15 μm or more

As a result of actually constructing the power MOS transistor according to the above conditions, the transistor characteristics (ON resistance RON and source-drain breakdown voltage VDSS) are as shown by the solid line I in FIG. This is a conventional power MOS transistor in which impurities are introduced into a high-concentration impurity introduction portion in one pattern (only one high-concentration layer is formed) (see FIG. 1).
In FIG. 3, the on-resistance is reduced by 4 to 5% as a whole as compared with the characteristics (indicated by the broken line in FIG. 11) of the conventional transistor (FIG. 12 showing the concentration characteristics along the line XX). The structure can reduce the oxide film capacitance (return capacitance) between the drain substrate layer and the gate electrode by about 20% (for comparison, the channel layer 101 ′ and the well diffusion layer 1
The depth of 01, the concentration characteristic of the second layer, the impurity concentration of the drain substrate 103, and the thickness of the substrate were the same. Also, withstand voltage VDSS
Is configured so that the breakdown voltage of the transistor as a whole is the same, and these are compared).

As described above, the impurity concentration of the first high-concentration layer 120A is changed stepwise such that it is higher than the impurity concentration of the second high-concentration layer 120B. The impurity introduction unit 120 as a whole,
By making the impurity concentration high near the substrate surface where the width of the drain substrate layer is narrow, and making the impurity concentration thinner at the lower side where the width is wide (substantially the same concentration as the conventional high concentration layer 203a shown in FIG. 12). The depletion layer generated when the transistor is turned on is made uniform in the introduction part 120, electric field concentration is avoided, and a decrease in breakdown voltage due to high concentration is prevented.

According to the n-type power MOS transistor of this embodiment, the high-concentration impurity introduction part 120 formed on the drain substrate layer 103 is the first high-concentration layer 120A.
And the second high-concentration layer 120B has a two-stage structure.
Since the impurity concentration of the high-concentration layer and the impurity concentration of the second high-concentration layer can be set differently, the high-concentration impurity introduction part 1
By appropriately adjusting the impurity introduction amount of 20, it becomes easy to miniaturize the element while keeping its transistor characteristics (ON resistance RON, source-drain breakdown voltage VDSS, feedback capacitance) at optimum values.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the film thickness, the impurity concentration, and the like of each portion of the transistor shown in this embodiment are listed as an example, and even in a transistor that deviates from these exemplified ranges, the high-concentration impurity region has two stages. The power MOS is formed and various combinations of the concentrations of the impurities introduced into these regions are changed to further reduce the size and reduce the on-resistance.
The transistor design becomes easy. Further, in forming the power MOS transistor of the above embodiment, phosphorus (P) is illustrated as the n-type impurity to be introduced and boron (B) is illustrated as the p-type impurity, but other n-type and p-type impurities are introduced. Even if the same effect is obtained.

[0020]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. According to the present invention, the installation interval of the well diffusion layer and the channel diffusion layer in which the channel region and the source region are formed is narrowed, the upper end of the drain substrate layer is narrowed, and the breakdown voltage of the semiconductor substrate portion is prevented from lowering. Therefore, the power MOS transistor can be downsized and the power consumption can be reduced while preventing the increase of the on-resistance and the reduction of the withstand voltage.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view of an n-channel vertical power MOS transistor 100 of this embodiment.

2 is a vertical cross-sectional view for explaining a gate width LD, a gate electrode interval LS, a channel width LC, and a well diffusion layer installation interval LW of the transistor 100 of FIG.

FIG. 3 is a cross-sectional view showing a state in which an n-type high-concentration impurity introduction portion 120 is formed in the surface layer of the substrate by performing implantation / diffusion in the manufacturing process of the power MOS transistor 100.

FIG. 4 is a cross-sectional view showing a state in which a reference well diffusion layer and a channel diffusion layer are formed in the semiconductor device of FIG.

5 is a cross-sectional view showing a state in which a first high-concentration layer is formed on the upper half side of the high-concentration impurity introducing portion 120 by performing implantation on the semiconductor device of FIG.

6 is a cross-sectional view showing a state in which a gate electrode is formed on the surface of a substrate layer 103 of the semiconductor device of FIG.

7 is a cross-sectional view showing a state in which another well diffusion layer is formed by performing implantation on the semiconductor device of FIG. 6 using a gate electrode as a mask.

8 is a cross-sectional view showing a state in which an Al wiring pattern is formed after depositing an interlayer insulating film on the semiconductor device of FIG.

FIG. 9 is a graph showing the concentration / depth of implants performed in the manufacturing process.

FIG. 10 is a graph showing a concentration profile of the power MOS transistor of the present invention.

FIG. 11 is a graph showing characteristics (ON resistance RON and source-drain breakdown voltage VDSS) of the power MOS transistor of the present invention in comparison with characteristics of a conventional transistor.

FIG. 12 is a vertical cross-sectional view showing a power MOS transistor having a conventional structure.

FIG. 13 is a graph showing a concentration profile of a power MOS transistor having a conventional structure.

[Explanation of symbols]

 100 vertical n-channel power MOS transistor 101 well diffusion layer 101 'channel diffusion layer 102 gate electrode 103 drain substrate layer 120 high concentration impurity introduction part 120A first high concentration layer (first layer) 120B second high concentration layer (second Layer) LW drain width LS gate electrode spacing LC channel width LD gate width

Claims (3)

[Claims] 1. A well diffusion layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type at least two or more at predetermined intervals, and a first conductivity type formed in the well diffusion layer. A semiconductor substrate portion other than the well diffusion layer is formed as a drain region, and the semiconductor substrate portion sandwiched by the at least two or more well diffusion layers has a first conductivity type and is higher than that. A vertical power MO formed by introducing impurities into the concentration and increasing the horizontal cross-sectional area as the depth increases.
In the S-transistor, the semiconductor device is characterized in that impurities are introduced into the semiconductor substrate portion sandwiched by the well diffusion layers so that the concentration becomes higher as the depth becomes shallower. 2. The impurity concentration of the semiconductor substrate is 1 × 10.
The maximum value of the impurity concentration of the semiconductor substrate portion sandwiched between the well regions in the range of ¹⁴ cm ⁻³ to 4 × 10 ¹⁴ cm ⁻³ is 6 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ^−3. The semiconductor device according to claim 1, wherein 3. When introducing impurities into a semiconductor substrate portion sandwiched by the two or more well diffusion layers according to claim 1 or 2, the impurities are overlapped and implanted by at least two implantation steps having different implantation depths. A method of manufacturing a semiconductor device characterized by the above.