JPH07120534A - Lsi tester - Google Patents

Abstract

PURPOSE:To perform an accurate test even if a signal transferred between a tester and an LSI is delayed by preventing the collision between a test pattern and the LSI on a signal line (cable) connecting the tester and the LSI. CONSTITUTION:A pattern buffer 12 for tentatively retaining a test pattern to be output is provided for operating the buffer 12 according to a clock signal and at the same time, output control means (a selector 14. a memory 16 for control, and a register 17) for supplying a control signal for breaking the supply of a clock signal for the pattern buffer 12 by an arbitrary number of cycles when the test pattern changes from an output mode to an input mode for prohibiting reading of the test pattern and for setting the output to a high impedance to an output driver are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for inspecting a semiconductor integrated circuit and, moreover, a technique effectively applied to a timing control for applying a test pattern to a logic LSI (large scale integrated circuit) and determining an output of the LSI. For example, the present invention relates to a technique suitable for use in an LSI tester having signal pins that share input and output.

[0002]

2. Description of the Related Art In a functional test of a logic LSI, a device 1 called a tester as shown in FIG. 2 outputs a test pattern prepared in advance by a driver DRV and applies it to a logic LSI 3 via a cable 2 or the like. The output is read and the comparator CMP compares it with the expected value ED to determine whether or not it is operating normally. In addition, although only one set of the driver DRV and the comparator CMP is shown in FIG. 2 as a representative, in an actual tester,
As many drivers D as there are input / output signal pins of the logic LSI 3
An RV and a comparator CMP are provided.

By the way, some logic LSIs have signal pins that share input and output (for example, peripheral LS connected to a microcomputer via a bus).
There is I). In the functional test of this kind of LSI, it is not possible to apply the test pattern to the logic LSI and read its output at the same time, so the test pattern application cycle (output cycle) and the LSI output read cycle (input cycle) And are repeated alternately.

[0004]

However, when the delay of the signal transmitted between the tester and the LSI can be ignored, the output cycle and the input cycle are changed as shown in FIG. 3 (A). It was possible to perform the test efficiently by alternately repeating the determination and making the determination at the timing indicated by T1 in the input cycle. However, when the number of pins of the logic LSI to be tested increases, the number of wirings (microstrip lines) 5 formed on the test board 4 mounting the LSI also increases, so that the test board itself increases in size and the cable 2 also increases. It will be long. Therefore, the delay of the signal transmitted between the tester 1 and the LSI 3 becomes a non-negligible amount, and the test pattern collides with the output signal of the LSI on the cable, making it impossible to perform an accurate test. Was found to occur.

That is, when the delay of the signal transmitted between the tester and the LSI becomes large, as shown in FIG. 3B, the test pattern output by the tester or the output signal of the LSI reaches the other end. A time difference Tpd occurs. Therefore, even if an attempt is made to make a determination at the same timing T1 as when there is no delay, the output signal of the LSI has not arrived.
It is necessary to delay the determination timing and perform the determination at a timing such as T2 when the output signal of the LSI is effective. However, at this time, when the tester outputs the next test pattern, a collision between the test pattern and the output signal of the LSI occurs on the cable. Therefore, if the tester determines at the timing of T2, the test pattern is read and the LSI malfunctions. It seems to be doing. Therefore, it is impossible to carry out an accurate test.

However, the conventional tester has not been configured to shift the output cycle of the test pattern according to the transmission delay time of such a signal. An object of the present invention is to provide a tester control technique that enables an accurate test to be performed even if there is a delay in a signal transmitted between the tester and the LSI. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in a tester for testing an LSI having a signal pin that shares an input and an output, a pattern buffer that temporarily holds a test pattern to be output is provided, and this buffer is configured to operate with a clock signal, for example. At the same time, when the test pattern changes from the output mode to the input mode, the clock signal supply to the pattern buffer is interrupted for an arbitrary cycle to prohibit the reading of the test pattern and set the output to the output driver high. An output control means for supplying a control signal for controlling the impedance or a predetermined level is provided.

[0008]

According to the above means, the output control means can interrupt the supply of the clock signal to the pattern buffer for a cycle corresponding to the signal transmission delay time to suppress the output of the test pattern. L
It is possible to prevent a collision between the test pattern on the signal line (cable) connecting to the SI and the output signal of the LSI, which allows accurate measurement even if there is a delay in the signal transmitted between the tester and the LSI. It is possible to achieve the above-mentioned object of being able to perform various tests.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of an LSI tester according to the present invention. The tester of this embodiment is suitable for testing an LSI having signal pins that share input and output.

In FIG. 1, 11 is a memory in which a test pattern is stored, 12 is a buffer memory (hereinafter referred to as a pattern buffer) which has a smaller capacity but a higher speed than the memory 11, and the test pattern in the memory 11 is It is divided into a plurality of pieces and stored in the pattern buffer 12 in order.
Reference numeral 13 is a clock generation circuit, which is the pattern buffer 1
The test pattern 2 is sequentially read by the clock signal φ supplied from the clock generation circuit 13 and is supplied to the pin electronics 15 via the selector 14. The pin electronics 15 is composed of a driver DRV and a comparator CMP as shown in FIG.

The memory 1 is not particularly limited.
One step of the test pattern stored in 1 is
It consists of three bits: a bit that specifies input or output, a bit that specifies whether the output data or expected value is "0" or "1", and a mask bit that indicates whether to perform comparison. It In this embodiment, a control memory 16 capable of high-speed operation similarly to the pattern buffer 12 and a control data generation circuit 18 for generating cycle control data to be stored in the control memory 16 are provided. And a register 17 for holding information for instructing the pin electronics 15 to make the output high impedance.

Further, the control memory 16 stores the cycle control data generated by the control data generation circuit 18, and the clock signal φ supplied from the clock generation circuit 13 is the same as the pattern buffer 12. The data is sequentially read out by the.
The cycle control data read from the control memory 16 is supplied to the selector 14 and the data is "0".
When it is, the test pattern read from the pattern buffer 12 is supplied to the pin electronics 15, and when the cycle control data is "1", the information held in the register 17 is the pin electronics 15.
Is supplied to.

Further, in this embodiment, the clock signal φ from the clock generation circuit 13 is supplied to the pattern buffer 12 via the AND gate 19 and read from the control memory 16. The generated cycle control data is also supplied to the AND gate 19 so as to control the supply of the clock signal φ to the pattern buffer 12.

That is, when the cycle control data read from the control memory 16 is "0", the AND gate 19 is opened and the clock signal φ is supplied to the pattern buffer 12 to read the pattern data. When the cycle control data read from the control memory 16 is "1", the AND gate 19 is closed and the supply of the clock signal φ to the pattern buffer 12 is cut off. Therefore, the pattern buffer 12
Reading is suspended and, instead, the information in the register 17 is supplied to the pin electronics 15 through the selector 14 so that a dummy cycle is inserted. That is, the cycle control data is data for inserting the dummy cycle.

On the other hand, the control data generation circuit 18 receives the bit designating the input or output of the test pattern read from the memory 11, and the content thereof is changed from "output" to "input". Sometimes a predetermined number of "1" data is generated. The number of "1" data to be generated is configured in advance from the outside according to the number of clock cycles corresponding to the signal transmission delay time of the signal line (cable) connected to the tester. Therefore,
When the cycle control data of "1" is read from the control memory 16, only during that time, the pattern buffer 12 is read.
The supply of the clock signal φ to the circuit is cut off, and a dummy cycle in which the output becomes high impedance is inserted.

As a result, as shown in FIG. 3B, the determination timing T2 is delayed from the timing T1 of FIG. 3A by the number of dummy cycles and the broken line A
As indicated by, the output cycle is also delayed by that amount, which prevents the test pattern output from the tester and the output signal of the LSI from colliding on the cable. In the above embodiment, the tester is provided with the control data generation circuit 18 for generating the cycle control data for inserting the dummy cycle. However, the cycle control data is created separately in advance like the test pattern. It may be stored in the memory 11.

As described above, in the above embodiment, in the tester for testing the LSI having the signal pin sharing the input and the output, the pattern buffer for temporarily holding the test pattern to be output is provided and this test buffer is used. It is configured to operate by a clock signal, and when the test pattern changes from the output mode to the input mode, the supply of the clock signal to the pattern buffer is interrupted for an arbitrary cycle to prohibit the reading of the test pattern. Output control means (selector 14, control memory 16 and register 1) for supplying a control signal for making the output high impedance to the output driver.
Since 7) is provided, the output of the test pattern can be suppressed by interrupting the supply of the clock signal to the pattern buffer only for the cycle corresponding to the signal transmission delay time, thus connecting the tester and the LSI. It is possible to prevent a collision between the test pattern on the signal line (cable) and the output signal of the LSI, and thereby to perform an accurate test even if there is a delay in the signal transmitted between the tester and the LSI. The effect is that

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above embodiment, the driver DRV in the pin electronics 15 sets the output to the high impedance when the dummy cycle is inserted, but it may output the intermediate level between the high level and the low level. In the above description, the case where the invention made by the present inventor is mainly applied to the tester of the logic LSI which is the field of application which is the background has been described, but the present invention is not limited thereto and the signal transmission delay time Can be widely used for a device that transmits data via a relatively large bidirectional signal line.

[0019]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a tester for testing an LSI having a signal pin that shares an input and an output, an accurate test can be performed even if there is a delay in a signal transmitted between the tester and the LSI.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an LSI tester according to the present invention,

FIG. 2 is an LSI tester and an LSI tested by the LSI tester.
Configuration diagram showing connection with

FIG. 3 is a timing chart showing the relationship between the test cycle of the LSI tester and the output signal of the LSI.

[Explanation of symbols]

 1 Tester 2 Cable 3 LSI 4 Test Board 11 Memory 12 Pattern Buffer 13 Clock Generation Circuit 14 Selector 15 Pin Electronics 16 Control Memory 18 Control Data Generation Circuit DRV Driver CMP Comparator

Claims (3)

[Claims] 1. A tester for testing an LSI having a signal pin that shares an input and an output, and a pattern buffer for temporarily holding a test pattern to be output, and when the test pattern changes from an output mode to an input mode. And output control means for prohibiting the reading of the test pattern from the pattern buffer for an arbitrary number of cycles and supplying a control signal for causing the output driver to have a high impedance or a predetermined level. LSI tester characterized by. 2. The output control means synchronizes with a register for holding information for instructing the output to have a high impedance or a predetermined level, a control memory for storing cycle control data, and the pattern buffer. A selector for selecting either the test pattern read from the pattern buffer or the information in the register on the basis of the cycle control data read from the control memory and supplying it to the output driver. The LSI tester according to claim 1, wherein: 3. The pattern buffer is configured to be operated by a clock signal, and
2. The reading of the test pattern from the pattern buffer is prohibited by cutting off the supply of the clock signal.
Alternatively, the LSI tester described in 2.