JP2005031037A - Control circuit for input-output terminal of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To conduct continuous switching between the input and the output of an input-output terminal in a test. <P>SOLUTION: This circuit is provided with a directional control register 106 for conducting directional control for the input-output terminal 100, based on a directional control signal supplied from an external terminal 116, an OR-gate 111 for conducting selection between a directional control signal supplied from a test-objective block 202 and the directional control signal supplied from the external terminal, and an output side buffer 102 and an input side buffer 101 for conducting switching between input-output directions of the input-output terminal 100, based on the selected directional control signal. The circuit is provided further with a control signal selecting register 113 capable of controlling, from the external terminal, the directional control signal supplied from the test-objective block 202, and the registers 106, 113 are connected respectively on the same scan chain. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an input / output terminal control circuit of a semiconductor device that performs operation verification of an LSI (Large Scale Integrated circuit).

  In recent years, with the progress of LSI miniaturization technology, the density has been increased, and at present, a system LSI having a plurality of processing functions on one LSI has been commercialized. As the functions of the system LSI become more complicated, the test method for performing the function evaluation becomes more complicated, and the dedicated test circuit required for the test contributes to an increase in the area of the entire LSI.

  For example, input / output terminal control at the time of testing requires control for each test item, which is realized by a logic circuit that performs control by an internal signal such as a test mode signal. However, in the current LSI, where the complexity of the system advances and the number of test items increases, the area of the input / output terminal control circuit increases as the LSI scale increases, and the amount of delay increases against the speeding up of the LSI. Therefore, control using a shift register has been proposed as input / output terminal control capable of reducing the area and the delay amount (see, for example, Patent Document 1).

  FIG. 4 shows a conventional input / output terminal control circuit, which uses a shift register to serially input a direction control signal from the outside and controls the direction of each terminal. In FIG. 4, 100 is an input / output terminal, 101 is an output side buffer with input / output restriction, 102 is an input side buffer, 103 is a selector that divides input / output control lines between test and actual operation, and 105 is in normal operation An input / output control line 106 is a direction control register that performs direction control on the input / output terminal 100 based on a direction control signal supplied from the external terminal 114. Each of the direction control registers 106 constitutes a scan chain by serial connection, shifts when a direction control signal is input from the external terminal 114, and sets the input / output direction of the input / output terminal 100 to one direction by the shift operation.

JP-A-11-73340

  However, the conventional input / output terminal control circuit requires a shift operation to reset the value of the shift register when switching the input / output terminal from input to output direction or from output to input direction. It takes time to set the input / output direction of the terminal, and continuous switching of direction control cannot be performed. For this reason, in the test in which the input / output direction of the input / output terminals must be frequently switched during the test, there is a problem that the test time increases in proportion to the number of times of switching. Therefore, the conventional input / output terminal control circuit cannot be used in a test that requires terminal switching control (continuous switching control) that does not allow time until the input / output direction is set.

  At the time of testing the current system LSI, there are cases where continuous switching control of input / output terminals may be required, for example, an isolation test (internal block extraction test). In a large-scale system LSI, an enormous amount of actual operation patterns are required to guarantee all operations as a single chip, which is not realistic considering the capacity load on the tester and the test time. For this reason, a method is used in which operation is guaranteed by extracting a single internal functional block to an input / output terminal and performing unit verification. In this isolation test, the pins of the internal functional block are connected to the input / output terminals, but when the number of input / output terminals is smaller than the number of pins of the internal block, they cannot be connected one-to-one. In such a case, connect the pin of the internal block to the input side and output side of one input / output terminal, and use the internal direction control signal to perform continuous switching synchronized with the input / output of internal data it can. However, in the direction control using the conventional shift register, the continuous switching control of the input / output terminals is impossible, and thus the above-described specification cannot be avoided.

  An object of the present invention is to solve the above-described conventional problems, and to provide an input / output terminal control circuit for a semiconductor device capable of continuously switching input / output terminals during a test.

  An input / output terminal control circuit for a semiconductor device according to the present invention is an input / output terminal control circuit for a semiconductor device that switches a connection between a test target block and an input / output terminal included in the semiconductor device bidirectionally, and is supplied from the outside. A register that performs direction control on the input / output terminal based on a direction control signal, a selection unit that selects a direction control signal supplied from the block to be tested and a direction control signal supplied from the outside; Switching control means for switching the input / output direction of the input / output terminal based on a direction control signal.

  According to the above configuration, since the direction control of the input / output terminals can be performed using the direction control signal supplied from the test target block, the register shift operation is not necessary for the direction control, and the internal data signal of the test target block The input / output terminals can be switched continuously in synchronism with the switching.

  Furthermore, the input / output terminal control circuit of the semiconductor device according to the present invention includes a register capable of externally controlling a direction control signal supplied from the test target block.

  According to the above configuration, the direction control signal supplied from the test target block can be controlled from the outside at an arbitrary timing by providing the register capable of controlling the direction control signal from the outside.

  Furthermore, the input / output terminal control circuit of the semiconductor device of the present invention connects the registers on the same scan chain.

  According to the above configuration, external control is possible even when the number of external terminals is limited by connecting a register for controlling the direction of input / output terminals and a register for controlling the direction control signal from the outside on the same scan chain. This makes it possible to arrange the registers and control them from the outside at an arbitrary timing.

  According to the present invention, since the direction control of the input / output terminals can be performed using the direction control signal supplied from the test target block, the register shift operation is not necessary for the direction control, and the internal data signal of the test target block The input / output terminals can be switched continuously in synchronism with the switching.

  In addition, according to the present invention, the direction control signal supplied from the test target block can be controlled from the outside at an arbitrary timing by providing the register capable of controlling the direction control signal from the outside.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of an input / output terminal control circuit according to Embodiment 1 of the present invention. In FIG. 1, 100 is an input / output terminal, 101 is an output side buffer with input / output restriction, 102 is an input side buffer, 103 is a selector that divides input / output control lines between a test time and an actual operation, and 105 is a normal operation time. An input / output control line 106 is a direction control register for controlling the direction of the input / output terminal 100 based on a direction control signal supplied from the external terminal 114, and 107 is an input / output control line from the internal system.

  Reference numeral 201 denotes a test target block that does not require bidirectional control at the time of testing, and the test is performed by setting the test mode signal 301 to “1” at the time of testing. The test mode signal 301 is a signal indicating that the test target block 201 is independently verified, and uses a direction control signal input from an external terminal and a direction control signal generated by the internal block. Since the test target block 201 does not output a direction control signal for controlling the direction of the input / output terminal 100 during the test, the direction of the input / output terminal 100 is controlled by the direction control register 106 that performs a shift operation according to the direction control signal input from the external terminal. Take control.

  The direction control register 106 is serially connected to the direction control registers of other input / output terminals to form a scan chain. When the direction control signal is input from the external terminal 114, the shift control operation is performed. Set the input / output direction of to one direction.

  Reference numeral 202 denotes a test target block that requires bidirectional control at the time of testing. At the time of testing, the test mode signal 302 is set to “1” to test the block. The test mode signal 302 is a signal indicating that the test target block 202 is independently verified, and uses a direction control signal input from an external terminal and a direction control signal generated by an internal block. Since the test target block 202 outputs an input / output terminal control signal 104 that controls the direction of the input / output terminal 100 during the test, the input / output terminal control signal 104 controls the direction of the input / output terminal 100.

  Reference numeral 204 denotes a data line formed between the input / output terminal 100 and the test target block by a test mode signal, and the normal operation connection block 203 is selected during normal operation.

  In the above configuration, the input / output terminal control signal 104 from the test target block 202 is input to the other of the AND gate 112 to which the test mode signal 302 is input. The output of the AND gate 112 is connected as an input / output control line 107 from the internal system to the other of the OR gate 111 to which the direction control register 106 is connected. The output of the OR gate 111 is connected to the other of the selector 103 to which the normal input / output control line 105 is connected. The output of the selector 300 is connected to a switching control unit (output side buffer 101, input side buffer 102) that switches the input / output direction of the input / output terminal 100, and the input / output control line 105 or the internal system during normal operation is selected by the selector control signal 300. The input / output control line 107 is selected and output to the switching control unit.

  Next, a case where the test target block 201 is tested will be described. When testing the test target block 201, the test mode signal 301 is set to “1” to cause the test target block selection circuit 204 to select the test target block 201. As a result, a data line is formed between the test target block 201 and the input / output terminal 100. The test target block 201 does not output a direction control signal, and the direction control of the input / output terminal 100 is performed by the direction control register 106.

  Since the test mode signal 302 is set to “0” except during the test of the test target block 202, the input / output terminal control signal 104 is masked by the AND gate 112, and the output of the direction control register 106 is enabled by the OR gate 111. Thus, the direction control of the input / output terminal 100 can be performed by the direction control register 106.

  Next, a case where the test target block 202 is tested will be described. When testing the test target block 202, the test mode signal 302 is set to “1” to cause the test target block selection circuit 204 to select the test target block 202. As a result, a data line is formed between the test target block 202 and the input / output terminal 100. Since the test target block 202 outputs a direction control signal, the direction control of the input / output terminal 100 is performed by the input / output terminal control signal 104.

  Since the test mode signal 302 is set to “1”, the input / output terminal control signal 104 is enabled by the AND gate 112. By setting the set value “0” from the external input terminal 104 to the direction control register 106, the output of the AND gate 112 becomes valid, so that the data input / output (input / output to / from the tester, etc.) of the block to be tested 202 The direction control of the input / output terminal 100 can be performed in synchronization.

  According to this embodiment, the direction control of the input / output terminals can be performed using the direction control register, and the direction control of the input / output terminals can be performed using the direction control signal from the test target block.

  FIG. 2 is a block diagram showing the configuration of the input / output terminal control circuit according to the second embodiment of the present invention. The same parts as those in the first embodiment will be described with the same reference numerals. The difference from the first embodiment is that the direction control of the input / output terminals is performed using a dedicated register instead of the test mode signal.

  The input / output terminal control signal 104 from the test target block 202 is input to one of the AND gates 112, and the output of the control signal selection register 113 is input to the other of the AND gates 112.

  The control signal selection register 113 is serially connected to other control signal selection registers to form a scan chain. When a control selection signal is input from the external terminal 115, a shift operation is performed, and the input / output terminal 100 is input by the shift operation. The output direction is set to one direction by the input / output terminal control signal 104 or the output of the direction control register 106.

  The output of the AND gate 112 is connected as an input / output control line from the internal system to the other of the OR gate 111 to which the direction control register 106 is connected. The output of the OR gate 111 is connected to the other of the selector 103 to which the normal input / output line 105 is connected.

  Next, a case where the test target block 201 is tested will be described. When testing the test target block 201, the test mode signal 301 is set to “1” to cause the test target block selection circuit 204 to select the test target block 201. As a result, a data line is formed between the test target block 201 and the input / output terminal 100. The test target block 201 does not output a direction control signal, and the direction control of the input / output terminal 100 is performed by the direction control register 106.

  Since the input / output terminal control signal 104 can be masked by the AND gate 112 according to the set value of the control signal selection register 113, the OR gate 111 is set by setting the set value to “0” when testing the test target block 201. As a result, the output of the direction control register 106 becomes valid, and the direction control register 106 can control the direction of the input / output terminal 100.

  Next, a case where the test target block 202 is tested will be described. When testing the test target block 202, the test mode signal 302 is set to “1” to cause the test target block selection circuit 204 to select the test target block 202. As a result, a data line is formed between the test target block 202 and the input / output terminal 100.

  Since the test target block 202 outputs a direction control signal, when the direction control of the input / output terminal 100 is performed by the input / output terminal control signal 104, the setting value of the control signal selection register 113 is set to "1" The set value of the control register 106 is set to “0”, and the input / output terminal control signal 104 is validated.

  When the test target block 202 is to be tested, if it is desired to fix the input / output terminal 100 in one direction, the setting value of the control signal selection register 113 is set to “0” as in the test of the test target block 201. The input / output terminal control signal 104 is masked by the AND gate 112.

  According to this embodiment, the direction control of the input / output terminals can be performed using the direction control register, and the direction control of the input / output terminals can be performed using the direction control signal from the test target block. Furthermore, by providing the control signal selection register, the direction control signal supplied from the test target block can be controlled from the outside at an arbitrary timing.

  FIG. 3 is a block diagram showing the configuration of the input / output terminal control circuit according to the third embodiment of the present invention. The same parts as those in the second embodiment will be described with the same reference numerals. The difference from the second embodiment is that the control signal selection register 113 is connected on the same scan chain as the direction control register 106.

  The direction control of the input / output terminals is performed by setting set values in the control signal selection register 113 and the direction control register 106 as in the second embodiment. The set value is set by shifting the register by a control selection signal input from the external terminal 116.

  According to this embodiment, the direction control of the input / output terminals can be performed using the direction control register, and the direction control of the input / output terminals can be performed using the direction control signal from the test target block. Furthermore, by providing the control signal selection register, the direction control signal supplied from the test target block can be controlled from the outside at an arbitrary timing. Furthermore, by connecting the registers on the same scan chain, it is possible to arrange registers that can be controlled externally even when the number of external terminals is limited.

It is a block diagram which shows the structure of the input / output terminal control circuit of the semiconductor device of Embodiment 1 of this invention. It is a block diagram which shows the structure of the input / output terminal control circuit of the semiconductor device of Embodiment 2 of this invention. It is a block diagram which shows the structure of the input / output terminal control circuit of the semiconductor device of Embodiment 3 of this invention. It is a block diagram which shows the structure of the input / output terminal control circuit of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Input / output terminal 101 Output side buffer 102 Input side buffer 103 Selector 104 Input / output terminal control signal 105 Input / output control line at normal operation 106 Direction control register 107 Input / output control line from internal system 111 OR gate 112 AND gate 113 control Signal selection registers 114, 115, 116 External input terminals 201, 202 Test target block 203 Connection block during normal operation 204 Test target block selection circuit 300 Selector control signal 301, 302 Test mode signal

Claims (3)

An input / output terminal control circuit for a semiconductor device that switches a connection between a test target block and an input / output terminal included in the semiconductor device bidirectionally,
A register that performs direction control on the input / output terminal based on a direction control signal supplied from the outside;
Selecting means for selecting a direction control signal supplied from the test target block and a direction control signal supplied from the outside;
Switching control means for switching the input / output direction of the input / output terminal based on the selected direction control signal;
An input / output terminal control circuit for a semiconductor device. 2. The input / output terminal control circuit for a semiconductor device according to claim 1, further comprising a register capable of externally controlling a direction control signal supplied from the test target block. 3. The input / output control circuit for a semiconductor device according to claim 2, wherein the registers are connected on the same scan chain.

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