JP2006170963A - Testing circuit for semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To verify the validity of an input pattern, and to detect faults in a test circuit itself, in the test circuit for inputting a serial test pattern. <P>SOLUTION: The test circuit of a semiconductor integrated circuit device comprises a scan flip-flop circuit 10 for connecting a plurality of stages of flip-flops in series and supplies a serial test pattern inputted from the outside to a circuit to be tested; and a validity determining section 40 that is connected to the final stage of the scan flip-flop circuit in series and checks the validity of the inputted serial test pattern. The validity determining section includes a first check value setting circuit 20a for outputting the check result of validity in the serial input direction of the serial test pattern; and a second check value installation circuit 20b for outputting the check value of validity, in the direction of the time of the serial test pattern. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a test circuit for a semiconductor integrated circuit device, and more particularly to a test circuit for a semiconductor integrated circuit device including a scan flip-flop circuit for facilitating the test.

  With the recent increase in scale and complexity of semiconductor integrated circuit devices (LSIs), circuit verification has become difficult. For example, in a logic LSI having 2 million to 3 million gates, verification (failure diagnosis) cannot be performed unless some design for testability is applied.

  As a method for facilitating testing, a flip-flop is connected in a chain (in series) to a function block circuit to form a shift register, and a serial test pattern is input to control the value of each flip-flop from the outside. The scan test method to observe is adopted.

  In LSI function macros etc., it may be difficult to input signals directly from external terminals, but even in such cases, by connecting the flip-flops in series inside the LSI and applying a serial test pattern, A signal can be sent to the function macro.

  In order to suppress the increase in test pattern verification time due to the increase in circuit scale, the logic circuit is divided into multiple blocks, and a scan chain that connects the test input terminal, scan flip-flop, and test output terminal in series for each block A configuration method has also been proposed (see, for example, Patent Document 1). In this method, the verification inside each block scans the test pattern and observes the output of the scan chain. However, between the blocks, the normal mode external terminals are shared to form a parallel scan chain. That is, the scan test is executed in parallel on a plurality of blocks.

  FIG. 1 shows an example of a conventional test circuit using a scan flip-flop. As shown in FIG. 1A, a plurality of first flip-flops (FF1) 111a to 111c are connected in series. The output of the first flip-flop (FF1) is input to the corresponding selector 113a-113c via the second flip-flop (FF2) 112a-112c, respectively. The outputs of the selectors 113a to 113c are connected to a circuit under test that is difficult to access directly from an external terminal.

As shown in FIG. 1B, in each stage corresponding to one bit of the serial signal, the serial test data latched in the previous stage is synchronized with the first test clock (CLK1) in the first flip-flop. Latched at (FF1) 111a. In synchronization with the second test clock (CLK2), the test pattern data latched by the FF1 is output to the functional block 130 to be tested by the second flip-flop FF2. The selector 113 selects either the test pattern output from the second flip-flop FF2 or the signal (DIN) from the user logic, and outputs it to the functional block 130 (DOUT).
JP-A-10-2938

  When an arbitrary pattern is given by such a test circuit, a serial test pattern created manually by an LSI design / developer is input. The input test pattern is not necessarily the same as data generated by a tool such as CAD, and the functional block test is performed without considering the validity of the test pattern itself.

  Further, the circuit block to be tested to which the signal is sent is not always logic, and for example, in the case of an analog circuit, it is difficult to confirm the validity of the serial test pattern by logic simulation.

  Further, when a test is performed using an actual semiconductor device, it is difficult to distinguish between a failure of a circuit block to be tested and a failure of a test circuit.

  Therefore, it is an object to provide a test circuit for a semiconductor integrated circuit device that can confirm the validity of an input test pattern and can detect a failure of the test circuit itself.

In order to solve the above problems, in the present invention, a test circuit for a semiconductor integrated circuit device is provided.
(A) a scan flip-flop circuit in which a plurality of stages of flip-flops are connected in series, and a serial test pattern input from the outside is supplied to the circuit under test;
(B) A validity determination unit that is connected in series to the final stage of the scan flip-flop circuit and checks the validity of the input serial test pattern.

  As a preferable configuration example, the validity determination unit outputs a first check value setting circuit that outputs a validity check result in the serial input direction of the serial test pattern, and a validity check result in the time direction of the serial test pattern. And a second check value setting circuit.

  In a desirable configuration example, the logical sum of the output of the first check value setting circuit and the output of the second check value setting circuit is output to the outside as the check result of the serial test pattern.

  In a semiconductor integrated circuit device test circuit that inputs a serial test pattern, the validity of the input test pattern can be confirmed.

  In addition, a failure of the test circuit itself can be detected.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings.

  2 is a block diagram showing an LSI test circuit according to an embodiment of the present invention, FIG. 3 is a diagram showing a scan flip-flop circuit 10 used in the circuit of FIG. 2, and FIG. 4 is used in the circuit of FIG. It is a figure which shows the check value setting circuit 20 to be performed.

  The LSI test circuit is a circuit for testing a test target circuit 30 such as a functional macro (block) formed on a semiconductor substrate (not shown). The LSI test circuit includes scan flip-flop circuits 10a to 10c for facilitating the test, and a validity determination unit 40 connected in series to the final-stage scan flip-flop circuit. The validity determination unit includes a second check value setting circuit 20a and a second check value setting circuit 20b. The scan flip-flop circuits 10 a to 10 c are connected in series to form a scan chain, and supply a serial test pattern supplied from the outside to the test target circuit 30 during a test. The check value setting circuits 20a and 20b respectively check the validity of the serial input direction and the validity of the time direction of the input serial test pattern.

  Each scan flip-flop 10 includes a first input terminal DIN that receives data from a preceding functional block such as user logic, a serial input terminal HTSI that receives serial test data (pattern), and first and second clock input terminals. CLK1 and CLK2 and check value input terminals CI0 and CI1 for receiving check values used for validity check of the input serial test pattern are provided. In the first-stage scan flip-flop circuit 10a of the scan chain, fixed check values “0” (LOW) are set to the check value input terminals CI0 and CI1.

  The scan flip-flop circuit 10 also has an internal output terminal DOUT that outputs either input data from the functional block or serial test data to the test target circuit 30, and a serial output terminal that sends a serial test pattern to the next scan flip-flop. HTSO and check value output terminals CO0 and CO1 for outputting a check result using the check value to the next-stage scan flip-flop. Check value output terminals CO0 and CO1 are connected to check value input terminals CI0 and CI1 in the next stage, respectively.

  The check value output terminal CO0 of the last-stage scan flip-flop 10c is connected to the check value input terminal CI of the first check value setting circuit 20a. Another check value output terminal CO1 is connected to the check value input terminal CI of the second check value setting circuit 20b.

  The first check value setting circuit 20a stores the check value of the test pattern in the serial input direction. The second check setting circuit 20b stores a check value in the time direction.

  The OR circuit 31 calculates the logical sum of the check outputs of all the check value setting circuits 20. The logical operation result and the serial output HTSO are selectively output to the outside via the selector 33. Specifically, the selector 33 outputs the serial test signal HTSO to the outside in normal times, and outputs the validity check result of the input serial test pattern to the outside for one cycle when the second clock CLK2 rises.

  The selection signal of the selector 33 is sent from the flip-flop 32 in synchronization with the first clock CLK1. The second clock is input to the reset terminal of the flip-flop 32, and the data input terminal is fixed to “1” (HI).

  FIG. 3 is a block diagram of the scan flip-flop circuit 10 used in the LSI test circuit of FIG.

  The scan flip-flop circuit 10 includes a first flip-flop 11, a second flip-flop 12, a selector 13, an AND circuit 14, a first EXOR circuit 15, and a second EXOR circuit 16.

  The serial test data HTSI input to the scan flip-flop circuit 10 is latched by the first flip-flop (FF1) 11 in synchronization with the first clock CLK1. The latched serial test data is output from the second flip-flop (FF2) 12 in synchronization with the second clock, and is supplied from the internal output terminal DOUT to the functional block 30 to be tested via the selector 13. The selector 13 selects either the signal DIN from the user logic or the serial test data output from the second flip-flop 12 according to the control signal HTMODE and outputs the selected signal to the functional block 30 to be tested.

  The current serial test pattern output from the second flip-flop 12 via the selector 13 is supplied to the first EXOR circuit 15 and is subjected to an exclusive OR operation with a preset check value CI0. When the scan flip-flop circuit 10 is the first stage circuit 10a, the check value CI0 is fixed to “0”, so that the value of the serial test data output from the second flip-flop 12 via the selector 13 is “1”. ", The output of the EXOR circuit 15 is" 1 ". This first EXOR output is connected to the check value input CI0 of the next-stage scan flip-flop as the check value output CO0.

  The current serial test pattern output from the second flip-flop 12 via the selector 13 is also supplied to the AND circuit 14. The AND circuit 14 performs a logical product of the serial test pattern output from the selector 13 and the next serial test pattern latched by the first flip-flop 11.

  The output of the AND circuit 14 is connected to one input terminal of the second EXOR circuit 16. The second EXOR circuit 16 obtains an exclusive OR of the AND operation result and a preset check value CI1. When the AND output and the check value CI1 match, the output of the EXOR circuit 16 becomes “0”, and when they do not match, “1” is output. The second EXOR output indicates the check result of the input serial data in the time direction, and is connected to the check value input CI1 of the scan flip-flop 10 at the next stage.

  In this way, the scan flip-flop 10 supplies both the check result CO0 in the serial input direction and the check result CO1 in the time direction in which the transition of the previous and current patterns is observed to the next scan flip-flop.

  FIG. 4 is a block diagram of the check value setting circuit 20 used in the LSI test circuit of FIG. The check value setting circuit 20 includes an AND circuit 23 that takes a logical product of the third flip-flop 21, the fourth flip-flop 22, and the third and fourth flip-flops 21 and 22.

  The third flip-flop 21 latches the serial test data latched in the previous stage in synchronization with the first clock CLK1. The fourth flip-flop 22 operates in synchronization with the second clock CLK2, and latches either CI0 input from the first EXOR or CI1 input from the second EXOR of the last-stage scan flip-flop 10c.

  In the present embodiment, the fourth flip-flop 22 of the first check value setting circuit 20a latches the input CI0 from the first EXOR at the timing of CLK2, and the fourth flip-flop 22 of the second check value setting circuit 20b The input CI1 from 2EXOR is latched at the timing of CLK2.

  The AND output EO output from the AND circuit 23 is a check result indicating whether the input serial test pattern is correct. The check output EO of the first check value setting circuit 20a is CHECK0 indicating the validity of the serial input direction, and the check output EO of the second check value setting circuit 20b is the time direction (previous serial test pattern and current serial test pattern). CHECK1 indicating the validity of the transition.

  As described above, in the test mode, the check result EO is output in synchronization with the second clock CLK2. More specifically, as described above with reference to FIG. 2, the output CHECK0 of the first check value setting circuit 20a and the check result CHECK1 of the second check value setting circuit 20b are ORed at the timing of CLK2. Externally output via the selector 33.

  FIG. 5 is a timing chart showing the operation of the LSI test circuit of FIG. First, the test circuit is reset by the reset signal HTXRST. Data DIN0, DIN1, and DIN2 from the user logic are respectively input to the scan flip-flop circuits 10a to 10c in FIG.

  At the rising edge of the mode signal HTMODE, the test mode is entered. At the timing of the first clock signal CLK1, the input serial test pattern HTSI is latched, and the check value C1 is set in FF1. During the test mode, the serial test pattern HTSI is sequentially input to the FF1 connected in a chain (series), and serial data is sequentially set in the scan flip-flop circuits at each stage at the timing of CLK1.

  At the rise of the second clock signal CLK2, the check value setting circuit 20 outputs the OR operation result of the check value setting circuits 20a and 20b to the outside as the check result of the validity of the input serial test pattern (HTSO is stand up). At the same time, serial test patterns are loaded from the scan flip-flop circuits 10a to 10c to the test target circuit 30 (DOUT0, DOUT1, DOUT2). This completes one cycle. After outputting the check value of the first cycle, the second cycle is started at the next rising edge of the first clock CLK1.

  As described above, in the test mode, the check result is output from the external output HTSO of the semiconductor integrated circuit device only during the check period from the rising edge of the second clock CLK2 to the next serial input. Data is output.

FIG. 6 shows an example of state setting set in the LSI test circuit of FIG. In the initial state, the internal outputs DOUT0, DOUT1, and DOUT2 output from the scan flip-flop circuits 10a to 10c to the test target circuit 30 are zero. In the first cycle, the states of the internal outputs DOUT0, DOUT1, and DOUT2 to the circuit under test 30 are S0 ₁ , S1 ₁ , and S2 ₁ , respectively. At this time, the outputs CHECK0 and CHECK1 of the check value setting circuits 20a and 20b are C0 ₁ and C1 ₁ , respectively. In the second cycle, the states of the internal output terminals DOUT0, DOUT1, and DOUT2 to the test target circuit 30 are S0 ₂ , S1 ₂ , and S2 ₂ , and the output terminals CHECK0 and CHECK1 of the check value setting circuits 20a and 20b are respectively C0 ₂ and C1 ₂ are obtained.

The first and second check results C0 ₁ and C0 ₂ output from the first check value setting circuit 20a are expressed by the following equations.

C0 ₁ = S0 ₁ + S1 ₁ + S2 ₁
C0 ₂ = S0 ₂ + S1 ₂ + S2 ₂
First and second check result C1 ₁ and C1 ₂ output from the second check value setting circuit 20b is expressed by the following equation.

C1 ₁ = (S0 ₁ +0) + (S1 ₁ +0) + (S2 ₁ +0)
C1 ₂ = (S0 ₂ + S0 ₁ ) + (S1 ₂ + S1 ₁ ) + (S2 ₂ + S2 ₁ )
As described above, in the LSI test circuit of this embodiment, the validity of the serial test pattern inputted every time can be confirmed as an external output, and a failure of the test circuit itself can be detected.

Finally, the following notes are disclosed regarding the above description.
(Supplementary note 1) A scan flip-flop circuit in which a plurality of stages of flip-flops are connected in series, and a serial test pattern input from the outside is supplied to the circuit under test;
A test circuit including a validity determination unit that is connected in series to the final stage of the scan flip-flop circuit and checks the validity of the input serial test pattern.
(Supplementary Note 2) The validity judgment unit
A first check value setting circuit for outputting a check result of validity of the serial input direction of the serial test pattern;
The test circuit according to claim 1, further comprising a second check value setting circuit that outputs a result of checking the validity of the serial test pattern in the time direction.
(Supplementary Note 3) An OR circuit that takes a logical sum of the output of the first check value setting circuit and the output of the second check value setting circuit;
The test circuit according to claim 2, further comprising a selector that selectively outputs the logical sum and the serial test pattern to the outside.
(Appendix 4) Each of the scan flip-flop circuits is
A first flip-flop that latches the current serial test pattern input from the previous stage in synchronization with the first clock signal;
A second flip-flop that outputs the previously latched serial test pattern in synchronization with the second clock signal;
The test circuit according to claim 1, further comprising a first EXOR circuit that performs an exclusive OR of an output of the second flip-flop and a first setting check value.
(Supplementary Note 5) Each of the scan flip-flop circuits includes:
An AND circuit that takes the logical product of the output of the second flip-flop and the output of the first flip-flop;
5. The test circuit according to appendix 4, further comprising a second EXOR circuit that performs an exclusive OR of an output of the AND circuit and a second setting check value.
(Additional remark 6) The said validity judgment part has a check value setting circuit which checks the validity of the said input serial test pattern,
The check value setting circuit
A third flip-flop for latching a serial test pattern input from the previous stage in synchronization with the first clock signal;
A fourth flip-flop that latches the output of the first EXOR circuit in synchronization with the second clock signal;
The test circuit according to claim 4, further comprising an AND circuit that takes a logical product of outputs of the third and fourth flip-flops.
(Appendix 7)
The validity determination unit has a check value setting circuit for checking the validity of the input serial test pattern,
The check value setting circuit
A third flip-flop for latching a serial test pattern input from the previous stage in synchronization with the first clock signal;
A fourth flip-flop that latches the output of the second EXOR circuit in synchronization with the second clock signal;
The test circuit according to claim 5, further comprising an AND circuit that takes a logical product of outputs of the third and fourth flip-flops.
(Appendix 8) Functional blocks formed on the semiconductor substrate;
A scan flip-flop circuit that connects a plurality of flip-flops in series and supplies a serial test pattern input from the outside to the functional block;
A semiconductor integrated circuit device comprising: a validity determination unit that is connected in series to the final stage of the scan flip-flop circuit and checks the validity of the serial test pattern.
(Supplementary Note 9) The validity determination unit
A first check value setting circuit for outputting a check result of validity of the serial input direction of the serial test pattern;
The semiconductor integrated circuit device according to appendix 8, further comprising a second check value setting circuit that outputs a result of checking the validity of the serial test pattern in the time direction.

FIG. 1B is a configuration diagram of a conventional test circuit using a scan flip-flop, and FIG. 1B is a diagram in which a circuit portion for one bit of a serial signal in the test circuit of FIG. It is a figure which shows the structure of the LSI test circuit based on one Embodiment of this invention. FIG. 3 is a block diagram of a scan flip-flop circuit used in the test circuit of FIG. 2. It is a figure which shows the structure of the check value setting circuit used with the circuit of FIG. 3 is a timing chart showing the operation of the LSI test circuit of FIG. FIG. 3 is a diagram showing an example of state setting set in the LSI test circuit of FIG. 2.

Explanation of symbols

10a to 10b scan flip-flop circuit (testability circuit)
11 First flip-flop 12 Second flip-flop 13 Selector 14, 23 AND circuit 15, 16 EXOR circuit 20a, 20b Check value setting circuit 21 Third flip-flop 22 Fourth flip-flop 30 Functional block (test target circuit)
40 Validity judging unit CLK1 First clock signal CLK2 Second clock signal DIN Input data DOUT from user logic Internal output terminal HTSI Serial test pattern input terminal HTSO External output terminal HTMODE mode switching signal to function block

Claims (5)

A scan flip-flop circuit that connects a plurality of flip-flops in series, and supplies a serial test pattern input from the outside to the test target circuit;
A test circuit including a validity determination unit that is connected in series to the final stage of the scan flip-flop circuit and checks the validity of the input serial test pattern. The validity determination unit includes:
A first check value setting circuit for outputting a check result of validity of the serial input direction of the serial test pattern;
The test circuit according to claim 1, further comprising a second check value setting circuit that outputs a result of checking the validity of the serial test pattern in the time direction. An OR circuit that takes the logical sum of the output of the first check value setting circuit and the output of the second check value setting circuit;
The test circuit according to claim 2, further comprising a selector that selectively outputs the logical sum and the serial test pattern to the outside. Each of the scan flip-flop circuits
A first flip-flop that latches the current serial test pattern input from the previous stage in synchronization with the first clock signal;
A second flip-flop that outputs the previously latched serial test pattern in synchronization with the second clock signal;
The test circuit according to claim 1, further comprising a first EXOR circuit that performs an exclusive OR of an output of the second flip-flop and a first setting check value. Functional blocks formed on a semiconductor substrate;
A scan flip-flop circuit that connects a plurality of flip-flops in series and supplies a serial test pattern input from the outside to the functional block;
A semiconductor integrated circuit device comprising: a validity determination unit that is connected in series to the final stage of the scan flip-flop circuit and checks the validity of the serial test pattern.

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