JP2008298618A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve timing in signal transition from a flip-flop for controlling a hard macro to the hard macro, reduce a circuit area, reduce power, and further reduce the limitations in arrangement of a selection logic circuit. <P>SOLUTION: A part or the whole of the flip-flop in a peripheral logic circuit of the hard macro 110 is constituted of a scan flip-flop 131 for outputting a predetermined value by scan shift. In the peripheral logic circuit, a first combination logic circuit 141 for outputting a value, corresponding to an output from the scan flip-flop 131 and a second combination logic circuit 142 that propagates the hard macro signal to the hard macro 110, when the output from the circuit 141 is fixed to a predetermined value by the scan shift, are provided. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device equipped with a hard macro such as a RAM.

  Many semiconductor devices are equipped with a hard macro such as a RAM (Random Access Memory).

  As a method of testing this hard macro, there is a method of mounting a test circuit such as a BIST circuit (Built-in Self Test).

As an example of a semiconductor device in which a test circuit such as a BIST circuit is mounted on a semiconductor device equipped with a hard macro, a test such as a selector logic (referred to as a selection logic circuit) is used during normal operation and a test. Some switch signal paths depending on the time (see, for example, Patent Document 1).
JP 2004-12374 A

  Many flip-flops and hard macros in a semiconductor device operate in synchronization with a clock signal input thereto, and the next clock signal arrives at the hard macro as a signal output from the flip-flop by the clock signal. Need to be propagated to a hard macro. Also, the hard macro output signal is output by the clock signal and needs to reach the flip-flop at the subsequent stage before the next clock signal arrives.

  However, in the conventional semiconductor device described above, by mounting the selection logic circuit, it takes time to propagate the signal from the selection logic circuit to the hard macro, and the signal is output from the flip-flop in the previous stage of the hard macro in synchronization with the clock. The signal may not reach the hard macro by the next clock. In this case, it is necessary to take measures such as lowering the cycle of the clock signal, leading to a decrease in the operation speed of the semiconductor device.

  In particular, there are many combinational logic circuits between the flip-flops located in the previous stage of the hard macro and the hard macro, and the timing of signal transition is often severe. Therefore, an increase in delay due to the addition of the selection logic circuit cannot be ignored.

  Further, since it is necessary to mount a selection logic circuit on most of the signals input to the hard macro, an increase in area and power due to the addition of the selection logic circuit and an increase in wiring are caused.

  If the selection logic circuit is implemented before the combinational logic, the logic must be implemented so that the combinational logic can propagate the test signal during the test, so the selection logic circuit is placed immediately before the input of the hard macro. Often done. That is, there are many restrictions on the arrangement of the selection logic circuit.

  The present invention has been made by paying attention to the above-mentioned problems. The timing of signal transition from the flip-flop that controls the hard macro to the hard macro is improved, the circuit area is reduced, the power is reduced, and the selection logic circuit is further improved. The purpose is to reduce the restrictions on the arrangement.

  In order to solve the above problems, some or all of the flip-flops in the peripheral logic circuit of the hard macro are configured by scan flip-flops, and the hard macro test signal from the test circuit is transferred to the hard macro by the scan operation of the scan flip-flop. Fixed the peripheral logic circuit to propagate to

For example, one embodiment of the present invention provides:
Hard macro,
A peripheral logic circuit for propagating output to the hard macro;
A test circuit for outputting a hard macro test signal for testing the hard macro;
With
The peripheral logic circuit is
At least one scan flip-flop that outputs a predetermined value by scan shift;
A first combinational logic circuit that outputs a value corresponding to the output of the scan flip-flop;
A second combinational logic circuit that propagates the hard macro test signal to the hard macro when the output of the first combinational logic circuit is fixed to a predetermined value by a scan shift;
It is characterized by having.

One embodiment of the present invention includes
Hard macro,
A peripheral logic circuit having a scan flip-flop having an output connected to the hard macro;
A test circuit for outputting a hard macro test signal for testing the hard macro;
With
The hard macro test signal is input to a scan data input terminal of the scan flip-flop.

One embodiment of the present invention includes
Hard macro,
A peripheral logic circuit for propagating output to the hard macro;
With
The peripheral logic circuit is
At least one scan flip-flop that outputs a predetermined value by scan shift;
A first combinational logic circuit that outputs a value corresponding to the output of the scan flip-flop;
When the output of the first combinational logic circuit is connected to the output and the external input terminal, and the output of the first combinational logic circuit is fixed to a predetermined value, the signal input from the external input terminal is A second combinational logic circuit propagating to the hard macro;
It is characterized by having.

One embodiment of the present invention includes
Hard macro,
A peripheral logic circuit having a scan flip-flop having an output connected to the hard macro;
With
The scan data input terminal of the scan flip-flop is connected to an external input terminal.

  According to the present invention, it is possible to improve the timing of signal transition from the flip-flop that controls the hard macro to the hard macro, reduce the circuit area, reduce the power, and reduce the restrictions on the arrangement of the selection logic circuit. Become.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of each embodiment, components having the same functions as those described once are given the same reference numerals and description thereof is omitted.

Embodiment 1 of the Invention
FIG. 1 is a block diagram showing a configuration of a semiconductor device 100 according to Embodiment 1 of the present invention.

  In the figure, a hard macro 110 is a hard macro such as a RAM, and operates upon receiving an output of a peripheral logic circuit (described later). The test circuit 120 is a circuit that outputs a hard macro test signal for testing the hard macro 110.

  In the peripheral logic circuit of the hard macro 110, a part or all of the internal flip-flops are constituted by scan flip-flops. In the example of FIG. 1, a portion constituted by a scan flip-flop in the peripheral logic circuit is illustrated as a scan flip-flop group 130, and the other part is illustrated as a combination logic circuit group 140.

  The scan flip-flop group 130 has one or a plurality of scan flip-flops 131.

  Each scan flip-flop 131 has a scan enable terminal NT, a clock terminal CK, a data output terminal Q, a data input terminal D, and a scan data input terminal DT.

  The scan enable terminal NT is a terminal to which a logical value for selecting an input signal from the scan data input terminal DT and the data input terminal D is given, and a scan enable signal (S04) is input thereto. In this embodiment, when the scan enable terminal NT is fixed to the L level by the scan enable signal S04, the scan flip-flop 131 selects the value of the data input terminal D as an output, and the scan enable terminal NT is set to the H level. When it is fixed, a signal given to the scan data input terminal DT is selected as an output. When scan enable terminal NT is fixed at L level, a signal applied to scan data input terminal DT is selected, and when scan enable terminal NT is fixed at H level, it is applied to data input terminal D. Needless to say, the signal may be selected.

  The clock terminal CK is a terminal to which a clock signal (S01) is given. The scan flip-flop 131 operates in synchronization with the clock signal S01, and outputs a signal selected by the scan enable terminal NT to the data output terminal Q.

  The data output terminal Q is connected to the scan data input terminal DT of another scan flip-flop 131. Thereby, the scan flip-flops 131 are connected in a daisy chain. In the example of FIG. 1, two scan flip-flops 131 are connected.

  The data input terminal D in the scan flip-flop 131 in the foremost stage is a terminal for inputting data given during normal operation. The scan enable signal S04 is fixed at the L level, and a predetermined data signal (S02) is input from the data input terminal D in the scan flip-flop 131 at the most previous stage, so that each scan data input terminal DT and data output terminal Q are connected. Can be fixed at any level. This is called a scan shift. This structure is typically used to perform a scan test.

  The scan data input terminal DT (scan chain input) in the scan flip-flop 131 at the foremost stage fixes the level of each data output terminal Q and the scan data input terminal DT in the other scan flip-flop 131 when the hard macro 110 is tested. This is a terminal for inputting data for the purpose. The scan enable signal S04 is fixed to the H level, and a predetermined signal (scan data signal S03) is input from the scan data input terminal DT in the scan flip-flop 131 at the most previous stage, whereby each scan data input terminal DT and data output are output. The terminal Q can be fixed at a level corresponding to the scan data input terminal DT.

  The combinational logic circuit group 140 includes a first combinational logic circuit 141 and a second combinational logic circuit 142.

  The first combinational logic circuit 141 is connected to the data output terminal Q of the scan flip-flop 131 and outputs according to the logic value of the data output terminal Q. Therefore, a signal from the first combinational logic circuit 141 to the second combinational logic circuit 142 can be controlled by scan shift.

  The second combinational logic circuit 142 outputs either the output of the first combinational logic circuit 141 or the hard macro test signal to the hard macro 110. In the present embodiment, the second combinational logic circuit 142 is an OR circuit. Therefore, the second combinational logic circuit 142 propagates the hard macro test signal to the hard macro 110 when the output of the first combinational logic circuit 141 is fixed at the L level. Note that the configuration of the second combinational logic circuit 142 may be changed as appropriate using an AND circuit, a NAND circuit, an OR circuit, a NOR circuit, or the like according to the configuration of the combinational logic circuit group 140.

  The semiconductor device 100 controls the scan enable signal S04 to L level during normal operation. As a result, data applied to the data input terminal D from another logic circuit or an external terminal is output to the data output terminal Q in synchronization with the clock signal S01 input to the clock terminal CK. Then, the first combinational logic circuit 141 outputs a logic value corresponding to the output of the scan flip-flop 131 to the second combinational logic circuit 142. At this time, the hard macro test signal is fixed so that the output of the first combinational logic circuit 141 propagates to the hard macro 110. In this example, if the output of the test circuit 120 is fixed at the L level, the output of the first combinational logic circuit 141 is propagated to the hard macro 110.

  Further, when the hard macro 110 is tested, the scan enable signal S04 is controlled to the H level. The value of the scan data input terminal DT in the scan flip-flop 131 in the foremost stage is fixed to a predetermined value, and the clock signal S01 is given to the clock terminal CK. As a result, the output of the data output terminal Q is fixed, and the output of the first combinational logic circuit 141 is also fixed. That is, if the scan data signal S03 is given to the scan data input terminal DT so that the output of the first combinational logic circuit 141 is fixed at the L level, the hard macro test signal is propagated from the test circuit 120 to the hard macro 110. The

  As described above, according to the present embodiment, it is possible to switch the input to the hard macro 110 to the hard macro test signal at the time of testing only by mounting a simple logic circuit (second combinational logic circuit 142). That is, the signal propagation delay between the scan flip-flop 131 and the hard macro 110 is improved. In addition, since the logic circuit to be mounted as the selection logic circuit is small, the circuit area and power can be reduced.

  Further, since control logic for switching between normal operation and test is not required, control can be facilitated and wiring can be reduced.

  The combinational logic circuit group can be mounted anywhere between the hard macro input and the scan flip-flop as long as it can be controlled by the scan flip-flop.

<< Embodiment 2 of the Invention >>
FIG. 2 is a block diagram showing a configuration of the semiconductor device 200 according to the second embodiment of the present invention. The semiconductor device 200 is obtained by adding a third combinational logic circuit 210 to the combinational logic circuit group 140 of the semiconductor device 100 as shown in FIG. With this addition, a scan flip-flop 131 is newly added in the scan flip-flop group 130.

  The third combinational logic circuit 210 is disposed between the second combinational logic circuit 142 and the hard macro 110. The third combinational logic circuit 210 receives the output of the second combinational logic circuit 142 and outputs a signal having a logical value corresponding to the output of the second combinational logic circuit 142 to the hard macro 110. When given a signal, the output of the second combinational logic circuit 142 is propagated to the hard macro 110 as it is.

  The newly added scan flip-flop 131 outputs the output of the data output terminal Q to the third combinational logic circuit 210 as the predetermined control signal.

  If the third combinational logic circuit 210 can be controlled as described above, the hard macro 110 can be tested even if the third combinational logic circuit 210 exists between the second combinational logic circuit 142 and the hard macro 110. . That is, according to the present embodiment, it is possible to select the mounting location of the second combinational logic circuit 142 so that the signal arrival time from each scan flip-flop 131 to the hard macro 110 is as short as possible.

<< Embodiment 3 of the Invention >>
FIG. 3 is a block diagram showing a configuration of a semiconductor device 300 according to Embodiment 3 of the present invention. The semiconductor device 300 is obtained by adding a flip-flop 310 to the semiconductor device 100 as shown in FIG.

  In this embodiment, the output of the combinational logic circuit group 140 is connected to the hard macro 110 via the flip-flop 310.

  At the time of testing the hard macro 110, the flip-flop 310 outputs the output of the combinational logic circuit group 140 input to the D terminal as it is in synchronization with the clock signal input to the CK terminal. Therefore, the flip-flop 310 does not need to be a scan flip-flop. The flip-flop 310 may be a flip-flop used for logic other than the test as long as it is a flip-flop located in the preceding stage of the hard macro 110. That is, it is not necessary to add a new one to test the hard macro 110.

  As described above, in this embodiment, since the flip-flop 310 is provided between the second combinational logic circuit 142 and the hard macro 110, even when the signal propagation time of the scan flip-flop 131 and the hard macro 110 is severe, the first The influence on the signal propagation time by the combinational logic circuit 142 of 2 can be avoided.

  Further, in a test circuit configuration in a normal BIST circuit (Built-in Self Test), the test circuit is mounted immediately before the hard macro, so the timing of signal propagation from the flip-flop used for other than the test to the hard macro is verified. I can't. However, in the present embodiment, since the output signal of the test circuit 120 is connected to the hard macro via the flip-flop 310 (a flip-flop used for logic other than the test), the flip-flop 310 to the hard macro 110 is connected. The timing of signal propagation can be verified.

  Similar to the second embodiment, a combinational logic circuit may exist between the flip-flop 310 and the hard macro 110. In this case, the output of the combinational logic circuit between the flip-flop 310 and the hard macro 110 can be controlled by the scan flip-flop 131 so that the output of the flip-flop 310 is propagated to the hard macro 110.

<< Embodiment 4 of the Invention >>
FIG. 4 is a block diagram showing a configuration of a semiconductor device 400 according to Embodiment 4 of the present invention. As shown in the figure, the semiconductor device 400 is obtained by adding a flip-flop 410 to the semiconductor device 100.

  In this embodiment, the output of the hard macro 110 is input to the D terminal of the flip-flop 410, and the output of the data output terminal Q of the flip-flop 410 is connected to the test circuit 120.

  The signal propagation time of the hard macro 110 is often long, and signal propagation from the hard macro 110 to the flip-flop inside the test circuit 120 may take time. At this time, the timing can be relaxed by transmitting the signal to the test circuit 120 in the next clock cycle after the data is once received by the flip-flop 410.

  Further, in the test circuit configuration in a normal BIST circuit, since the test circuit is mounted immediately after the hard macro, the timing of signal propagation from the flip-flop other than the test to the hard macro cannot be verified. However, in the present embodiment, since the output signal of the test circuit is connected to the hard macro via the flip-flop 410 (a flip-flop used for logic other than the test), the signal from the flip-flop 410 to the hard macro 110 The timing of propagation can be verified.

<< Embodiment 5 of the Invention >>
FIG. 5 is a block diagram showing a configuration of a semiconductor device 500 according to Embodiment 5 of the present invention. As shown in the figure, the semiconductor device 500 includes a hard macro 110, a scan flip-flop 131, and a test circuit 120.

  In the present embodiment, the scan flip-flop 131 is connected to the hard macro 110 directly or via a combinational logic circuit (not shown).

  A hard macro test signal output from the test circuit 120 is input to the scan data input terminal DT of the scan flip-flop 131. A scan enable signal S04 is input to the scan enable terminal NT.

  With this configuration, the test is performed by fixing the scan enable signal S04 to the H level and inputting it to the scan flip-flop 131 and propagating the hard macro test signal from the scan flip-flop 131 to the hard macro 110 during the test.

  In the conventional configuration and the second embodiment, the second combinational logic circuit 142 must be mounted in the combinational logic circuit group 140. In the second embodiment, the second combinational logic circuit 142 has to be mounted between the previous stage and the previous stage flip-flop of the hard macro 110. However, in this embodiment, a test circuit can be mounted between the scan flip-flop 131 and the hard macro 110 without mounting any combinational logic circuit. In other words, the test circuit can be mounted without affecting the signal propagation timing in the logic operation other than the test.

  Note that the scan flip-flop 131 may be a flip-flop used for logic other than the test. That is, it is not necessary to add a new one to test the hard macro 110.

  Further, a combinational logic circuit may be provided between the hard macro 110 and the scan flip-flop 131. In this case, the combinational logic circuit is controlled by another scan flip-flop, and the output of the scan flip-flop 131 connected to the test circuit 120 is propagated to the hard macro 110.

Embodiment 6 of the Invention
FIG. 6 is a block diagram showing a configuration of a semiconductor device 600 according to Embodiment 6 of the present invention. As shown in the figure, the semiconductor device 600 is obtained by adding a flip-flop 410 to the semiconductor device 500.

  In this embodiment, the output of the hard macro 110 is input to the D terminal of the flip-flop 410. The output of the data output terminal Q of the flip-flop 410 is connected to the test circuit 120.

  Therefore, also in this embodiment, the timing can be relaxed by transmitting the signal to the test circuit 120 in the next clock cycle after the data is once received by the flip-flop 410.

<< Embodiment 7 of the Invention >>
FIG. 7 is a block diagram showing a configuration of a semiconductor device 700 according to Embodiment 7 of the present invention. As shown in the figure, the semiconductor device 700 is configured so that the second combinational logic circuit 142 of the semiconductor device 100 can be controlled from the outside.

  In the semiconductor device 700, one terminal of the second combinational logic circuit 142 is connected to the first combinational logic circuit 141, and the other terminal is connected to the external input terminal 710.

  Further, the test circuit 120 receives the output of the hard macro 110.

  When the second combinational logic circuit 142 is controlled by the test circuit 120, only a predetermined control signal is given, but according to the present embodiment, the hard macro 110 can be freely controlled from the external input terminal 710. Become.

  That is, in the present embodiment, it is possible to freely control a hard macro from an external terminal.

  Note that the external input terminal 710 may be an external input / output terminal having an input function and an output function.

<< Embodiment 8 of the Invention >>
FIG. 8 is a block diagram showing a configuration of a semiconductor device 800 according to Embodiment 8 of the present invention. As shown in the figure, the semiconductor device 800 is obtained by adding a flip-flop 310 to the semiconductor device 700.

  In this embodiment, the output of the combinational logic circuit group 140 is connected to the hard macro 110 via the flip-flop 310.

  Also in this embodiment, as in the third embodiment, the flip-flop 310 does not need to be a scan flip-flop. The flip-flop 310 may be a flip-flop used for logic other than the test as long as it is a flip-flop located in the preceding stage of the hard macro 110. That is, it is not necessary to add a new flip-flop 310 in order to test the hard macro 110.

  With the above configuration, similarly to the third embodiment, even when the signal propagation time of the scan flip-flop 131 and the hard macro 110 is severe, the influence on the signal propagation time by the second combinational logic circuit 142 can be avoided.

  Note that a combinational logic circuit may be provided between the flip-flop 310 and the hard macro 110 or between the second combinational logic circuit 142 and the external input terminal 710 as in the second embodiment. In this case, the output of the combinational logic circuit can be controlled by the scan flip-flop 131 so that the output of the flip-flop 310 is propagated to the hard macro 110.

<< Ninth Embodiment of the Invention >>
FIG. 9 is a block diagram showing a configuration of a semiconductor device 900 according to Embodiment 9 of the present invention. As shown in the figure, the semiconductor device 900 is obtained by adding a flip-flop 410 to the semiconductor device 800.

  Accordingly, also in the present embodiment, the timing can be relaxed by causing the signal to be propagated to the test circuit 120 in the next clock cycle after the data is once received by the flip-flop 410.

<< Embodiment 10 of the Invention >>
FIG. 10 is a block diagram showing a configuration of a semiconductor device 1000 according to the tenth embodiment of the present invention. The semiconductor device 1000 is configured by connecting the output of the hard macro 110 to an external output terminal 1010 as shown in FIG. In this case, the test circuit 120 may be omitted.

  As a result, the output of the hard macro 110 can be directly observed from the external output terminal 1010.

  The external output terminal 1010 may be an external input / output terminal having an input function and an output function.

<< Embodiment 11 of the Invention >>
FIG. 11 is a block diagram showing a configuration of a semiconductor device 1100 according to Embodiment 11 of the present invention. The semiconductor device 1100 is obtained by connecting the output of the hard macro 110 to an external output terminal 1010 as shown in FIG. In this case, the test circuit 120 may be omitted.

  Accordingly, also in the present embodiment, the timing can be relaxed by causing the signal to be propagated to the external output terminal 1010 in the next clock cycle after the data is once received by the flip-flop 410.

<< Embodiment 12 of the Invention >>
FIG. 12 is a block diagram showing a configuration of a semiconductor device 1200 according to the twelfth embodiment of the present invention.

  In the fifth embodiment, the output of the test circuit 120 is connected to the scan data input terminal DT of the scan flip-flop 131. However, in the semiconductor device 1200, the scan data input terminal DT of the scan flip-flop 131 is connected to the external input terminal 710. ing. The test circuit 120 is connected to the output of the hard macro 110.

  Thereby, the input signal of the hard macro 110 can be easily controlled from the external input terminal 710.

<< Embodiment 13 of the Invention >>
FIG. 13 is a block diagram showing a configuration of a semiconductor device 1300 according to Embodiment 13 of the present invention.

  In the semiconductor device 1300, the output of the hard macro 110 is connected to the test circuit 120 via the flip-flop 410 as shown in FIG.

  Also in the present embodiment, the timing can be relaxed by transmitting the signal to the test circuit 120 in the next clock cycle after the data is once received by the flip-flop 410.

<< Embodiment 14 of the Invention >>
FIG. 14 is a block diagram showing a configuration of a semiconductor device 1400 according to Embodiment 14 of the present invention. The semiconductor device 1400 is configured by connecting the output of the hard macro 110 to an external output terminal 1010 as shown in FIG. In this case, the test circuit 120 may be omitted.

  As a result, the output of the hard macro 110 can be directly observed from the external output terminal 1010.

  The external output terminal 1010 may be an external input / output terminal having an input function and an output function.

<< Embodiment 15 of the Invention >>
FIG. 15 is a block diagram showing a configuration of a semiconductor device 1500 according to the fifteenth embodiment of the present invention. The semiconductor device 1500 is obtained by adding a flip-flop 410 to the semiconductor device 1400. In the semiconductor device 1500, the output of the hard macro 110 is connected to the external output terminal 1010 via the flip-flop 410.

  With the above configuration, also in the present embodiment, the timing can be relaxed by transmitting the signal to the external output terminal 1010 in the next clock cycle after the data is once received by the flip-flop 410.

  In the above-described fourth, sixth, ninth, eleventh, thirteenth, and fifteenth embodiments, the flip-flop 410 need not be dedicated to the test. Even if the flip-flop 410 is a flip-flop that performs logic control other than the test, it can be used for timing relaxation if the input data can be output to the data output terminal Q as it is by supplying a clock during the test. Can do.

  Further, the flip-flop 410 need not be a scan flip-flop as long as a shift operation can be performed at the time of testing.

  A combinational logic circuit may exist between the hard macro 110 and the flip-flop 410. In this case, the output of the combinational logic circuit can be controlled by the scan flip-flop 131 so that the output of the hard macro 110 is propagated to the flip-flop 410. That is, in these embodiments, a flip-flop provided for logic control other than testing can be used without providing a flip-flop for testing. Therefore, the timing of signal propagation between the hard macro 110 and the test circuit 120 can be relaxed without adding a new circuit.

  In addition, the number of scan flip-flops in each embodiment is an exemplification, and increases or decreases depending on the combinational logic configuration in the combinational logic circuit group 140.

  Further, the scan flip-flop does not need to be mounted only for the hard macro test, and may be shared for use in logic operations other than the test.

  Further, when there are a plurality of scan flip-flops, it is not necessary to connect them to the same scan chain and scan enable signal as long as the output of the data output terminal Q of each scan flip-flop can be controlled during the test.

  The semiconductor device according to the present invention can improve the timing of signal transition from the flip-flop that controls the hard macro to the hard macro, reduce the circuit area, reduce the power, and reduce the restrictions on the arrangement of the selection logic circuit. It has the effect of becoming possible, and is useful as a semiconductor device or the like equipped with a hard macro such as a RAM.

1 is a block diagram showing a configuration of a semiconductor device 100 according to Embodiment 1. FIG. 6 is a block diagram showing a configuration of a semiconductor device 200 according to Embodiment 2. FIG. FIG. 6 is a block diagram illustrating a configuration of a semiconductor device 300 according to a third embodiment. FIG. 6 is a block diagram illustrating a configuration of a semiconductor device 400 according to a fourth embodiment. FIG. 10 is a block diagram illustrating a configuration of a semiconductor device 500 according to a fifth embodiment. FIG. 10 is a block diagram illustrating a configuration of a semiconductor device 600 according to a sixth embodiment. FIG. 10 is a block diagram illustrating a configuration of a semiconductor device 700 according to a seventh embodiment. FIG. 10 is a block diagram illustrating a configuration of a semiconductor device 800 according to an eighth embodiment. FIG. 10 is a block diagram illustrating a configuration of a semiconductor device 900 according to a ninth embodiment. FIG. 10 is a block diagram illustrating a configuration of a semiconductor device 1000 according to a tenth embodiment. It is a block diagram which shows the structure of the semiconductor device 1100 which concerns on Embodiment 11. FIG. FIG. 16 is a block diagram illustrating a configuration of a semiconductor device 1200 according to a twelfth embodiment. It is a block diagram which shows the structure of the semiconductor device 1300 which concerns on Embodiment 13. FIG. FIG. 16 is a block diagram showing a configuration of a semiconductor device 1400 according to a fourteenth embodiment. FIG. 16 is a block diagram showing a configuration of a semiconductor device 1500 according to a fifteenth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 110 Hard macro 120 Test circuit 130 Scan flip flop group 131 Scan flip flop 140 Combination logic circuit group 141 1st combination logic circuit 142 2nd combination logic circuit 200 Semiconductor device 210 3rd combination logic circuit 300 Semiconductor device DESCRIPTION OF SYMBOLS 310 Flip-flop 400 Semiconductor device 410 Flip-flop 500 Semiconductor device 600 Semiconductor device 700 Semiconductor device 710 External input terminal 800 Semiconductor device 900 Semiconductor device 1000 Semiconductor device 1010 External output terminal 1100 Semiconductor device 1200 Semiconductor device 1300 Semiconductor device 1400 Semiconductor device 1500 Semiconductor device S01 Clock signal S02 Data signal S03 Scan data signal S04 Scan enable Signal

Claims (14)

Hard macro,
A peripheral logic circuit for propagating output to the hard macro;
A test circuit for outputting a hard macro test signal for testing the hard macro;
With
The peripheral logic circuit is
At least one scan flip-flop that outputs a predetermined value by scan shift;
A first combinational logic circuit that outputs a value corresponding to the output of the scan flip-flop;
A second combinational logic circuit that propagates the hard macro test signal to the hard macro when the output of the first combinational logic circuit is fixed to a predetermined value by a scan shift;
A semiconductor device comprising: The semiconductor device according to claim 1,
The hard macro is a semiconductor device in which an output of the peripheral logic circuit is propagated through a flip-flop. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the output of the hard macro is input to the test circuit via a flip-flop. Hard macro,
A peripheral logic circuit having a scan flip-flop having an output connected to the hard macro;
A test circuit for outputting a hard macro test signal for testing the hard macro;
With
The semiconductor device, wherein the hard macro test signal is input to a scan data input terminal of the scan flip-flop. The semiconductor device according to claim 4,
The semiconductor device according to claim 1, wherein the output of the hard macro is input to the test circuit via a flip-flop. Hard macro,
A peripheral logic circuit for propagating output to the hard macro;
With
The peripheral logic circuit is
At least one scan flip-flop that outputs a predetermined value by scan shift;
A first combinational logic circuit that outputs a value corresponding to the output of the scan flip-flop;
When the output of the first combinational logic circuit and the external input terminal are connected, and the output of the first combinational logic circuit is fixed to a predetermined value, the signal input from the external input terminal is A second combinational logic circuit propagating to the hard macro;
A semiconductor device comprising: The semiconductor device according to claim 6, comprising:
The hard macro is a semiconductor device in which an output of the peripheral logic circuit is propagated through a flip-flop. The semiconductor device according to claim 6, comprising:
A semiconductor device, further comprising a test circuit to which the output of the hard macro is input via a lip flop. The semiconductor device according to claim 6, comprising:
An output of the hard macro is connected to an external output terminal. The semiconductor device according to claim 6, comprising:
In the semiconductor device, the output of the hard macro is connected to an external output terminal via a flip-flop. Hard macro,
A peripheral logic circuit having a scan flip-flop having an output connected to the hard macro;
With
A scan data input terminal of the scan flip-flop is connected to an external input terminal. The semiconductor device according to claim 11, comprising:
A semiconductor device further comprising a test circuit to which the output of the hard macro is input via a flip-flop. The semiconductor device according to claim 11, comprising:
An output of the hard macro is connected to an external output terminal. The semiconductor device according to claim 11, comprising:
In the semiconductor device, the output of the hard macro is connected to an external output terminal via a flip-flop.

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