JP2001042007A - Test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce gate lag by providing a system logic having a test select function comprising system data I/O terminals, and a boundary scan cell comprising an output buffer. SOLUTION: A system logic 10 having a test select function switches a path for delivering signals from system data input terminals A(1)-A(n) through an output I/F buffer 15 to a system data output terminal 16 and a path for delivering a signal from a test data input terminal B through the output I/F buffer 15 to the system data output terminal depending on the signal at a test mode input terminal MOD. The shift MUX 11 of a boundary scan cell 100 selects input signals PIN, SIN based on a shift mode signal SFD and delivers a selected signal. A shift FF 12 delivers output from the shift MUX 11 to a terminal D and delivers a signal CLD to a terminal C. An update FF 13 has a terminal D receiving a signal from the terminal Q of the shift FF 12 and a terminal C receiving an update signal UPD.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a test circuit, and more particularly, to a test circuit to which a boundary scan is applied.

[0002]

2. Description of the Related Art With the recent development of integrated circuit technology, LS
I is becoming larger and more complex. Accordingly, LSI testing has become extremely difficult.

On the other hand, with the progress of surface mounting technology in recent years,
The surface mounting density of printed circuit boards has been increasing.
As a result, the in-circuit test, which has been widely used as a test method for a printed circuit board, cannot be applied.

Therefore, in order to facilitate the test of the printed circuit board, a test method called “JTAG boundary scan” has been standardized by IEEE. According to this standard, it is necessary to provide a boundary scan mechanism inside an LSI for a printed circuit board test.

FIGS. 16 and 6 show a configuration of a test circuit including a boundary scan cell, which is one configuration of the JTAG boundary scan method.

Referring to FIG. 16, this test circuit comprises:
System logic 20 and boundary scan cell 20
0, a buffer 25, and an output terminal 26.

[0007] The boundary scan cell 200 is
Shift MUX 21 for selecting and outputting input signal PIN and input signal SIN based on shift mode signal SFD
And a shift FF 22 receiving the output of the shift MUX 21 at the data input terminal D, receiving the shift clock signal CLD at the clock input terminal C, and sending out the output signal SOT from the data output terminal Q, and a shift FF at the data input terminal D.
22; a signal from the data output terminal Q of 22; an update clock signal UPD at the clock input terminal C;
Further, an update FF 23 for updating which outputs a signal from the data output terminal Q, and an input signal P supplied to the input terminal A
An output MUX 24 that selects one of the IN and the output signal from the data output terminal Q of the update FF 23 given to the input terminal B based on the test mode signal MOD and sends it out as the output signal POT.

Next, the operation of the conventional test circuit including the boundary scan cell 200 will be described.

In the operation mode of this test circuit, a signal applied to input terminals A (1) to A (n) of the system logic 20 is output from an output Y, and this signal is output to an output MUX2.
4 and the normal operation mode of sending to the output terminal 26 via the output buffer 25, the shift MUX 21 of the boundary scan cell 200, the shift FF 22, and the update FF 23 for update, and the data from the data output terminal Q of the update FF 23 There are two types of test modes in which an output signal is selected based on a test mode signal MOD and transmitted as an output signal POT.

When operating in the normal operation mode, the test mode signal MOD is set to "0". Thus, the logic value of the input signal PIN can be output as the output signal POT through the input terminals A (1) to A (n) of the system logic. As a result, the system logic can output the value to the external terminal without being affected by the output value of the boundary scan cell (update FF). On the other hand, when operating in the test mode, the data of the boundary scan cell 200 is output to the output signal POT.
, The test mode signal MOD is set to “1”.
To As a result, the output from the data output terminal Q of the update FF 23, which is provided to the input terminal B of the output MUX 24 and operates based on the update clock signal UPD, can be introduced as the output signal POT.

That is, the data from the boundary scan cell is output to the output signal P without affecting the logic of the input signal PIN.
It can be OT.

Further, to observe the logical value of the input signal PIN, the shift mode signal SFD may be set to "0".
As a result, the input signal PIN is passed through the input terminal A of the shift MUX 21 to the data input terminal D of the shift FF 22.
To the clock input terminal C of the shift FF 22
Is input with the shift clock signal CLD. Thus, the data of the input signal PIN can be taken into the shift FF 22.

The boundary scan cell 200
Data setting and observation are performed as follows. That is, by switching the input selection to the input terminal B side by the shift MUX 21, data from another boundary scan cell is taken in from the input terminal B as an input signal SIN. The output of the shift register stage constituted by the shift FF 22 is connected as an output signal SOT to the input signal SIN of another boundary scan cell to operate the shift register.

FIG. 6 shows a conventional test circuit to which a boundary scan cell 600 is applied on the input side.
The operation is the same as that of the test circuit of FIG.

[0015]

In the boundary scan cell 200 shown in FIG. 16, an output MUX is inserted in a path from an input signal PIN to an output signal POT.
As shown in FIG. 17, the wiring delay of the net a and the output MUX
This causes a delay in input and output in the normal operation mode, such as a gate delay of the device. The wiring delay of the net a is from the output terminal Y of the system logic to the input terminal A of the output MUX 24.
And the wiring length to the input terminal A of the shift MUX 21. That is, the shorter the wiring length of the net a, the smaller the wiring delay.

In the design of an ASIC, it is general that the layout and wiring of blocks are automatically laid out using a layout tool in view of the development schedule. However, in the automatic layout, the wiring length is not always short, and there is a problem of having a large wiring delay. In other words, if only a simple additional circuit, for example, an output MUX is added, there is a problem that the wiring becomes longer due to the addition of the test circuit, which causes a large delay overhead.

Accordingly, an object of the present invention is to provide a wiring delay for a signal path between an external terminal and an internal logic, and a gate delay arranged for individually driving the external terminal to either the test logic or the internal logic. It is an object of the present invention to provide a test circuit capable of reducing the propagation delay between an external terminal and internal logic.

[0018]

The test circuit of the present invention comprises:
A system block with a test function including a system data input terminal, a system data output terminal, a test data input terminal, a test mode input terminal, and a test data output terminal; an output I / F buffer;
A boundary scan cell including a shift MUX, a shift FF, and an update FF, wherein the system block with a test function transmits a signal from a system data input terminal to the system when the signal at the test mode input terminal is in a non-test mode. The path is configured to be transmitted from a data output terminal and output to a system external output terminal via an output I / F buffer. When the signal of the test mode input terminal is in a test mode, the boundary scan cell has the test function. The output of the test data output terminal of the system block is received, and this output is sent to a second boundary scan cell connected to the next stage of the boundary scan cell, and further, the boundary scan cell is connected to a previous stage of the boundary scan cell. Of the third boundary scan cell connected to Receiving a signal to force, and sends the signal to the test data input terminal, and outputs a signal of the test data input terminal from the system data output terminal, the output I /
The path is configured to output to the system external output terminal via the F buffer.

Further, another test circuit of the present invention includes an input I / F buffer having a system external input terminal, a first system data input terminal, a first system data output terminal, and a test data output terminal. A shift MUX, a shift FF, and an update FF for receiving a signal from the test data output terminal
And a system block with a test function including a second system data input terminal, a test data input terminal, a test mode input terminal, and a second system data output terminal. The / F buffer has a function of outputting a signal of the first system data input terminal to a first system data output terminal and a test data output terminal, and the system logic with a test function has a function of outputting the signal of the test mode input terminal. When the signal is in the non-test mode, the path is configured to output the signal of the second system data input terminal to the second system data output terminal, and when the signal of the test mode input terminal is in the test mode, the boundary is set. A scan cell receiving an output of the test data output terminal of the input I / F buffer; Sending the output to the boundary scan chain; further, the boundary scan cell receives a signal output from the boundary scan chain, sends this signal to the second test data input terminal, and outputs a signal from the test data input terminal to the system data input terminal. In this configuration, the path is switched to a path to be output to the output terminal.

Further, the boundary scan cell of the test circuit according to the present invention may be arranged such that an output of the shift MUX is input to a data terminal of the shift FF, and the shift FF is clocked by a first clock signal to operate the shift FF.
An output signal is output, the shift FF output signal is input to a data terminal of the update FF, and the update FF is clocked by a second clock signal to be an output signal of the boundary scan cell. Can also.

The system block with a test function of the test circuit of the present invention may have a configuration having a flip-flop, a configuration having an OR circuit, and a configuration having a NOR circuit. Furthermore, the system block with a test function of the test circuit of the present invention may have a configuration having an AND circuit, a configuration having a NAND circuit, and a configuration having an EXOR circuit. E
An XNOR circuit may be used.

That is, as means for realization, FIGS.
When configuring a test circuit for a circuit composed of system logic and an I / F buffer shown in FIG. 1, the circuit configuration shown in FIGS. 1 and 7 is adopted.

[0023]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a circuit diagram of the test circuit according to the first embodiment of the present invention.

Referring to FIG. 1, a test circuit according to a first embodiment of the present invention includes a system data input terminal A (1).
-A (n), a system data output terminal Y, a test data input terminal B, a test mode input terminal MOD and a test data output terminal Y ', a system block with a test function, an output I / F buffer 15, Terminal 16, shift MUX 11, shift FF 12, and update FF
13, the system logic 10 with the test selection function outputs the signals of the system data input terminals A (1) to A (n) to the output I.
/ F buffer 15 via system data output terminal 16
And a path for outputting the signal of the test data input terminal B to the system data output terminal via the output I / F buffer according to the signal of the test mode input terminal MOD.

Further, the test circuit according to the first embodiment of the present invention has system data input terminals A (1) to A (n).
To the test data output terminal Y ′.

Next, the operation of the test circuit according to the first embodiment of the present invention will be described.

Shift M of boundary scan cell 100
The UX 11 selects and outputs the input signal PIN and the input signal SIN based on the shift mode signal SFD. On the other hand, the shift FF 12 supplies the shift MU to the data input terminal D.
The output of X11 is provided, and the shift clock signal CLD is input to the clock input terminal C. Further, an output signal SOT is transmitted from the data output terminal Q.

The update FF 13 for update is
The data output terminal Q of the shift FF 12 is connected to the data input terminal D.
And the update clock signal UPD is input to the clock input terminal C. Further, a signal output POT 'is output from the data output terminal Q.

Then, the system logic 10 with the test selection function includes the logic values of the input signals applied to the input terminals A (1) to A (n) and the update FF 13 applied to the input terminal B.
Is selected based on the test mode signal MOD and transmitted as an output signal POT. In the configuration described above, the operation modes of the test circuit include the input terminals A (1) to A (A) of the system logic 10 with the test selection function.
(N) is output from the output Y as a signal POT, and the signal POT is transmitted to the output terminal 16 via the output buffer 15; the shift MUX 11 of the boundary scan cell 100;
2 and the update FF 13 for the update,
The output signal POT ′ from the data output terminal Q of F13 is
There are two types of test modes, which are selected based on the test mode signal MOD and transmitted as an output signal POT.

When operating the test circuit in the normal operation mode, the test mode signal MOD may be set to "0". Thus, the logic values of the input signals given to the input terminals A (1) to A (n) of the system logic 10 with the test selection function can be output as the output signal POT through. As a result, even when such a boundary scan cell is placed on the external terminal of the integrated circuit chip, it is possible to prevent the external terminal from being logically affected.

On the other hand, when operating the test circuit in the test mode, the boundary scan cell 100
Is output as the output signal POT, the test mode signal MOD may be set to “1”. Thus, the output POT ′ from the data output terminal Q of the update FF 13 that operates based on the update clock signal UPD and that is supplied to the input terminal B of the system logic with the test function can be introduced as the output signal POT. That is, the output signal POT ′ from the boundary scan cell 100 is used as the output signal POT instead of the logical value of the input signal given to the input terminals A (1) to A (n) of the system logic 10 with the test selection function. Can be.

Further, in order to observe the logical values of the input signals applied to the input terminals A (1) to A (n) of the system logic 10 with a test selection function, the shift mode signal SFD
To “0”. Thereby, the logic values of the input signals given to the input terminals A (1) to A (n) of the system logic 10 with the test selection function are input to the data input terminal D of the shift FF 12 through the input terminal A of the shift MUX 11, Further, the shift clock signal CLD is applied to the clock input terminal C of the shift FF 12. Thus, the data of the input signal PIN can be taken into the shift FF 12. (The output terminal Y ′ of the system logic 10 with the test selection function is the logic value of the input signal given to the input terminals A (1) to A (n) of the system logic 10 with the test selection function. Input terminal B
And is output without being affected by the input signal MOD. The data setting and observation of the boundary scan cell 100 are performed as follows. That is, shift MU
By switching the input selection to the input terminal B side at X11, data from another boundary scan cell is taken in from the input terminal B of the shift MUX 11 as the input signal SIN. The output of the shift register stage constituted by the shift FF 12 is connected as the output signal SOT to the output signal SIN of another boundary scan cell to operate the shift register.

That is, the test circuit according to the first embodiment of the present invention as shown in FIG. 1 can be realized with respect to the circuit before the test circuit shown in FIG. 2 is added.

When the system logic has a flip-flop configuration as shown in FIG. 3, when configuring a test circuit, the system logic (flip-flop) is a flip-flop with a test selection function shown in FIG. A test circuit is realized as a circuit configuration. Further, the flip-flop with the test selection function can be realized by the circuit configuration of FIG.

The system logic with a test selection function is an OR circuit with a test selection function having the logic shown in FIG.
R circuit, AND circuit with test selection function having logic shown in FIG. 14, NAND circuit with test selection function, or EX with test selection function having logic shown in FIG.
A configuration including an OR circuit and an EXNOR circuit with a test selection function can also be employed.

Next, a test circuit according to a second embodiment of the present invention will be described.

Referring to FIG. 7, the test circuit according to the second embodiment of the present invention has a test circuit configuration on the external input terminal side, and passes through an input signal supplied to input terminal 85 of the I / F buffer. An I / F buffer 86 with a dedicated test output having a dedicated test output terminal for outputting, and an input terminal A
(1) A system logic 80 with a test selection function that selects one of the input signal given to A (n) and the test input signal and outputs a logic value of the system logic. When the I / F buffer has the configuration shown in FIG.
The test-dedicated output I / F buffer 86 has the configuration shown in FIG.

More specifically, the test circuit according to the second embodiment of the present invention comprises a system external input terminal 85.
An input I / F buffer 86 with a dedicated test output having a system data input terminal, a system data output terminal, and a test data output terminal; a boundary scan cell 700 including a shift MUX 81, a shift FF 82, and an update FF 83; The system block 80 with a test selection function includes a system data input terminal, a test data input terminal, a test mode input terminal, and a system data output terminal.

Input I / F buffer 86 with dedicated test output
Has a function of outputting a signal of a system data input terminal to a system data output terminal and a test data output terminal. The system logic 80 with a test selection function outputs signals of the system data input terminals A (1) to A (n). A path to be output to the system data output terminal Y and a test data input terminal B
Of the test mode input terminal MOD.

Furthermore, the test circuit according to the embodiment of the present invention has been described with respect to the circuit configuration of the output terminal and the circuit configuration of the input terminal. However, by combining the circuit configuration of the output terminal and the circuit configuration of the input terminal, It goes without saying that the present invention can be applied to a bidirectional terminal.

Although the description has been made on the assumption that the boundary scan is used, the present invention can be applied to other than the boundary scan.

That is, in the field of ASIC, when testing a core and other logic integrated into one function,
The present invention can also be applied to a separated test method for separately testing a core and logic.

The operations required in the isolation test method are to apply an input signal of an external terminal to an input terminal of the core and to output a signal of an output terminal of the core to the external terminal. In order to apply the input signal of the external terminal to the input terminal of the core, an I / F buffer with a dedicated test output is used, and the wiring to the input terminal of the core is taken from the dedicated test output terminal.

With this configuration, it is possible to prevent an increase in the delay time to the normal operation due to a longer wiring to the input terminal of the core. To output the signal of the output terminal of the core to the external terminal, a system block with a test selection function is used.
The output terminal of the core is connected to the test data input terminal of the system block with the test selection function, and a mode signal indicating whether the mode is the normal mode or the test mode is input to the test mode input terminal. The signal of the test data output terminal is
Not used because it is unnecessary for core testing.

[0045]

As described above, the test circuit of the present invention has the following effects.

First, there is an effect of preventing an increase in delay time.

The operation frequency in the normal operation mode requires a high speed operation of several tens MHz to several hundreds MHz, whereas the operation frequency in the test mode is a low speed operation of several MHz. It is well known that the density of the arrangement / wiring around the external terminals of a semiconductor chip is extremely high. If the boundary scan cells are arranged around the external terminals of the semiconductor chip, there is a problem that the path wiring in the normal operation mode becomes longer and the delay time increases. If a boundary scan cell that operates only at a low speed is placed away from the area around the external terminals that are crowded, it is possible to prevent the path wiring in the normal operation mode from becoming longer, and as a result, to prevent an increase in delay time. There is. Even if the wiring of the path of the boundary scan cell which is a low-speed operation becomes long and the delay becomes large, there is no significant effect.

Second, there is an effect that the problem of increase in libraries (blocks) can be solved. The logic required in the normal operation mode is AND, NAND, OR, NOR,
EXOR, EXNOR, FF, etc. Including these logics in the boundary scan cell increases the types of boundary scan cells. Here, FF is simply expressed as FF, but there are many types of FF such as those with a preset function and those with a reset function. In the present invention, boundary scan cells are separated from system logic.
The boundary scan cells can be shared, and only the system logic that is the minimum configuration needs to be designed as a library (block).
There is also the effect of preventing an increase in the number.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a test circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram before the test circuit shown in FIG. 1 is added.

FIGS. 3A and 3B are diagrams showing flip-flops. FIG. 3A is a circuit diagram, and FIG. 3B is a truth table.

FIG. 4 is a diagram showing a flip-flop with a test function;
The diagram (a) is a circuit diagram, and the diagram (b) is a truth table.

FIG. 5 is a specific circuit diagram of a flip-flop with a test function.

FIG. 6 is a circuit diagram of a conventional test circuit.

FIG. 7 is a circuit diagram of a test circuit according to a second embodiment of the present invention.

8 is a circuit diagram before the test circuit shown in FIG. 7 is added.

FIGS. 9A and 9B are diagrams showing an I / F buffer. FIG. 9A is a circuit diagram, and FIG. 9B is a truth table.

FIG. 10 is a diagram showing an I / F buffer with a test-dedicated output. FIG. 10 (a) is a circuit diagram, and FIG. 10 (b) is a truth table.

11A and 11B are diagrams showing flip-flops, wherein FIG. 11A is a circuit diagram and FIG. 11B is a truth table.

FIG. 12 is a diagram showing a flip-flop with a test function. FIG. 12 (a) is a circuit diagram, and FIG. 12 (b) is a truth table.

FIG. 13 is a diagram showing a truth table of a circuit with a test function.
(A) is a truth table of the OR circuit with the test function, and (b) is a truth table of the NOR circuit with the test function.

FIG. 14 is a diagram showing a truth table of a circuit with a test function;
(A) is a truth table of an AND circuit with a test function.
FIG. 3B is a truth table of the NAND circuit with the test function.

FIG. 15 is a diagram showing a truth table of a circuit with a test function;
FIG. 4A is a truth table of the EXOR circuit with the test function, and FIG. 4B is a truth table of the EXNOR circuit with the test function.

FIG. 16 is a circuit diagram of another conventional test circuit.

17 is a diagram illustrating a delay of another conventional test circuit shown in FIG.

[Explanation of symbols]

1, 20, 70, 89 System logic 5, 15, 25 Output buffer 76, 88 Input buffer 86, 92 Input buffer with dedicated output for test 6, 16, 26, 75, 85, 87 Terminal 10, 41, 80, 93 Test System logic with selection function 11, 21, 71, 81 Shift MUX 12, 22, 72, 82 Shift FF 13, 23, 73, 83 Update FF 24, 74 Output MUX 31 Flip-flop 51-63 Inverter 64-69 Transfer gate 100 , 200, 600, 700 Boundary scan

Claims (10)

[Claims] 1. A system block with a test function having a system data input terminal, a system data output terminal, a test data input terminal, a test mode input terminal, and a test data output terminal, an output I / F buffer, and a system external terminal. And a boundary scan cell composed of a shift MUX, a shift FF, and an update FF. The system block with a test function is configured such that, when the signal at the test mode input terminal is in the non-test mode, the signal at the system data input terminal From the system data output terminal,
A path for outputting to a system external output terminal via an output I / F buffer, wherein when the signal at the test mode input terminal is in a test mode, the boundary scan cell is used to output the test data of the system block with the test function. Receiving the output of the terminal and sending this output to a second boundary scan cell connected to the next stage of the boundary scan cell, wherein the boundary scan cell is connected to a third stage connected to a preceding stage of the boundary scan cell. Receiving the signal output by the boundary scan cell,
This signal is sent to the test data input terminal, the signal of the test data input terminal is output from the system data output terminal, and the path is configured to be output to the system external output terminal via the output I / F buffer. And test circuit. 2. An input I / F buffer having a system external input terminal, a first system data input terminal, a first system data output terminal, and a test data output terminal, and receives a signal from the test data output terminal. A system having a boundary scan cell composed of a shift MUX, a shift FF, and an update FF, and a test function having a second system data input terminal, a test data input terminal, a test mode input terminal, and a second system data output terminal. A block, wherein the input I / F buffer has a function of outputting a signal of the first system data input terminal to a first system data output terminal and a test data output terminal,
When the signal at the test mode input terminal is in the non-test mode, the system logic with the test function
And a path for outputting the signal of the system data input terminal to the second system data output terminal. When the signal of the test mode input terminal is in the test mode, the boundary scan cell is connected to the input I / F buffer. Receiving the output of the test data output terminal, sending this output to the boundary scan chain, further receiving the signal output from the boundary scan chain, and sending this signal to the second test data input terminal And a test circuit for switching a signal from a test data input terminal to a path for outputting the signal to the system data output terminal. 3. The boundary scan cell inputs an output of the shift MUX to a data terminal of the shift FF, causes the shift FF to perform a clock operation with a first clock signal, and outputs a shift FF output signal. 3. The test circuit according to claim 1, wherein the shift FF output signal is input to a data terminal of the update FF, and the update FF is clocked by a second clock signal to generate an output signal of the boundary scan cell. 4. 4. The system block with a test function according to claim 1, further comprising a flip-flop.
Test circuit as described. 5. The test circuit according to claim 1, wherein said system block with a test function has an OR circuit. 6. The system block with a test function according to claim 1, further comprising a NOR circuit.
Test circuit as described. 7. The test circuit according to claim 1, wherein the system block with a test function includes an AND circuit. 8. The system block with a test function according to claim 1, further comprising a NAND circuit.
The test circuit according to 6 or 7. 9. The system block with a test function according to claim 1, further comprising an EXOR circuit.
The test circuit according to 6, 7, or 8. 10. The system block with a test function having an EXNOR circuit.
The test circuit according to 5, 6, 7, 8 or 9.